SVE: Extract Intermediate Address for SVE Vector Memory Operations
This patch introduces an optimization that extracts and factorizes
the "base + offset" common part for the address computation when
performing an SVE vector memory operation (VecStore/VecLoad).
With SVE enabled by default:
Test: ./art/test.py --simulate-arm64 --run-test --optimizing \
(With the VIXL simulator patch)
Test: ./art/test.py --target --64 --optimizing \
(On Arm FVP with SVE - See steps in test/README.arm_fvp.md)
Test: 527-checker-array-access, 655-checker-simd-arm.
Change-Id: Icd49e57d5550d1530445a94e5d49e217a999d06d
5 files changed