| commit | 5512b4e610f1edba745803053358b07760019f33 | [log] [tgz] |
|---|---|---|
| author | Roman Artemev <roman.artemev@syntacore.com> | Wed Nov 22 15:56:43 2023 +0300 |
| committer | Santiago Aboy Solanes <solanes@google.com> | Wed Feb 07 15:55:21 2024 +0000 |
| tree | 2165eb6e75175aa27be192846c59d958af1eeca1 | |
| parent | 3025c7fddfcc2b0d23eebc3a8cbc4cdc3b1f1463 [diff] |
riscv64: Support RISC-V RVV in disassembler Support Vector instructions in disassembler - Vector Load/Store instructions - Vector ALU control instructions - Vector Arithmetic instructions - add missed flh/flq/fsh/fsq Test: No test avaliable for now Change-Id: I5e5e56ba068fe9d53a8c502590a466f9fabd55a0