)]}'
{
  "commit": "8e5bc2dc0e70142811ae792c2b56af48c1eb7d4c",
  "tree": "bd81f98c59fff92129f423be2c48366df71d20ec",
  "parents": [
    "349d1377aa300512177729e7988d824b67638552"
  ],
  "author": {
    "name": "Shalini Salomi Bodapati",
    "email": "shalini.salomi.bodapati@intel.com",
    "time": "Wed Oct 24 11:50:56 2018 +0530"
  },
  "committer": {
    "name": "Shalini Salomi Bodapati",
    "email": "shalini.salomi.bodapati@intel.com",
    "time": "Wed Oct 24 20:29:38 2018 +0530"
  },
  "message": "Add support for vex coding scheme in x86 assembler\n\nThis patch adds support to emit VEX prefix which is needed\nto emit instructions namely andn, blsmsk, blsr, blsi\non a cpu that has AVX2.\n\nTest: ./test.py --host --64, test-art-host-gtest\nChange-Id: I6b4902caf8560e4406c5053b142686ed28ba5404\nSigned-off-by: Shalini Salomi Bodapati \u003cshalini.salomi.bodapati@intel.com\u003e\n",
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