)]}' { "log": [ { "commit": "322b389a74177c9d938f1f73d53110623dfc61b6", "tree": "b2437d4cdce399ce462d587d9c9c47a8fceb8953", "parents": [ "272bf7e60add5f741fb9a2589eaa71945257afcc", "af88835231c2508509eb19aa2d21b92879351962" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 23 17:19:34 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 23 17:19:34 2015 +0000" }, "message": "Merge \"Remove unnecessary null checks in CheckCast and InstanceOf\"" }, { "commit": "af88835231c2508509eb19aa2d21b92879351962", "tree": "4ef1c8fb3c5b78175767999a888b0c2cb1ea6485", "parents": [ "da93333d568f3c5bd8eeb58341d10a332e1d42bf" ], "author": { "name": "Guillaume \"Vermeille\" Sanchez", "email": "guillaumesa@google.com", "time": "Mon Apr 20 14:41:30 2015 +0100" }, "committer": { "name": "Guillaume \"Vermeille\" Sanchez", "email": "guillaumesa@google.com", "time": "Thu Apr 23 17:53:17 2015 +0100" }, "message": "Remove unnecessary null checks in CheckCast and InstanceOf\n\nChange-Id: I6fd81cabd8673be360f369e6318df0de8b18b634\n" }, { "commit": "c2ea806908e205a808182b2255b6ef5433695375", "tree": "0bf39dc59d0c43c1649aba6703112e779e1d40a9", "parents": [ "769f2d32e4b04758e4dd6ce967f779cbfa74dbcb", "97833a0d26e265c5885e27af4b8e8969ccb9612a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 21 11:24:52 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 21 11:24:52 2015 +0000" }, "message": "Merge \"Opt compiler: Minor object store optimizations for ARM64.\"" }, { "commit": "97833a0d26e265c5885e27af4b8e8969ccb9612a", "tree": "e5529452a170d4819159b0b08a435b3078dcb082", "parents": [ "d921d64c09b9222b8422f78da6b34b0a61e305c9" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Apr 16 15:07:12 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Apr 20 15:54:04 2015 +0000" }, "message": "Opt compiler: Minor object store optimizations for ARM64.\n\nThis is an adaptation of af07bc121121d7bd7e8329c55dfe24782207b561 for\nARM64.\n\nChange-Id: I5f4984ac86ede89cdf7c915f4bbf8d091059a0eb\n" }, { "commit": "27eac12a66a73eb38b5ccb45b62350cf341299d0", "tree": "7cc7eea6dd543720da2921c11f68296f5df37b07", "parents": [ "e40d82ffe388458c2674ec051f1dd897362692eb", "ad4450e5c3ffaa9566216cc6fafbf5c11186c467" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 20 15:20:15 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 20 15:20:15 2015 +0000" }, "message": "Merge \"Opt compiler: Implement parallel move resolver without using swap.\"" }, { "commit": "e40d82ffe388458c2674ec051f1dd897362692eb", "tree": "bd4ebb602abc6bb7c8d5792f34c8c7eb1ba36fb1", "parents": [ "90078eec8b676d363a8116f487df3596c9f23ea8", "d921d64c09b9222b8422f78da6b34b0a61e305c9" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 20 15:13:07 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 20 15:13:08 2015 +0000" }, "message": "Merge changes Ib9648605,I34a3bd17\n\n* changes:\n Opt compiler: ARM64: Block VIXLpools when recording the pc.\n Opt compiler: ARM64: Follow other archs for a few codegen stubs.\n" }, { "commit": "d921d64c09b9222b8422f78da6b34b0a61e305c9", "tree": "7009b178312c6f96ca56d01082ff8000cb47873c", "parents": [ "09a99965bb27649f5b1d373f76bfbec6a2500c9e" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Apr 16 15:07:16 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Apr 20 14:45:15 2015 +0100" }, "message": "Opt compiler: ARM64: Block VIXLpools when recording the pc.\n\nVIXL automatically handles and generate literal and veneer pools when\nusing the MacroAssembler. In general, the pools can be emitted\nanywhere. Helpers are provided to forbid VIXL from emitting pools\nlocally.\n\nSo when writing the pseudo-code\n\n __ Fmov(d0, 1.2345);\n __ Ldr(dst, MemOperand(src, offset));\n FunctionRecordingCurrentPC();\n __ Add(x0, x1, x2);\n\nVIXL might generate code looking like\n\n 0x00: ldr s0, [pc, 0xc]\n 0x04: ldr dst, [src, offset]\n 0x08: b #0x10\n 0x0c: \u003cliteral 1.2345\u003e\n 0x10: add x0, x1, x2\n\nand the program counter recorded by the helper will point after the\nliteral pool.\nSo we explicitly stop VIXL from emitting pools when dealing with code\nwhere we care about the program counter.\n\nChange-Id: Ib964860539bdb10f5704c290bdf74e5db149e462\n" }, { "commit": "09a99965bb27649f5b1d373f76bfbec6a2500c9e", "tree": "a1584b26a5b6f3dee692d0b21373de27734c965f", "parents": [ "2e0f89b1b61685f7c322a4c6ec3e3b4839e76d64" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Apr 15 11:47:56 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Apr 20 14:45:01 2015 +0100" }, "message": "Opt compiler: ARM64: Follow other archs for a few codegen stubs.\n\nCode generation for HInstanceFieldGet, HInstanceFieldSet,\nHStaticFieldGet, and HStaticFieldSet are refactored to follow the\nstructure used for other backends.\n\nChange-Id: I34a3bd17effa042238c6bf199848cbc2ec26ac5d\n" }, { "commit": "36aafd94af64d6f1ba603392f66959998f2a93a2", "tree": "13de8641b36380015b80dac1a231b58d08b3de29", "parents": [ "aff3f0a0a2a080e313ae80c9b0216aa26a668623", "27df758e2e7baebb6e3f393f9732fd0d064420c8" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Apr 20 13:03:14 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 20 13:03:14 2015 +0000" }, "message": "Merge \"[optimizing] Add memory barriers in constructors when needed\"" }, { "commit": "27df758e2e7baebb6e3f393f9732fd0d064420c8", "tree": "261207281fd574deffb4dc1c1bc6bea8f150993e", "parents": [ "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Apr 17 19:12:31 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Apr 20 14:02:51 2015 +0100" }, "message": "[optimizing] Add memory barriers in constructors when needed\n\nIf a class has final fields we must add a memory barrier before\nreturning from constructor. This makes sure the fields are visible to\nother threads.\n\nBug: 19851497\nChange-Id: If8c485092fc512efb9636cd568cb0543fb27688e\n" }, { "commit": "88c13cddc3a4184908662b0f3de796565d348c76", "tree": "6986849099ff7afc042eac31a3e53df0c468962b", "parents": [ "f458ba7d9c04bc8d499532b5470af28db18e4149" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Apr 14 17:35:39 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 20 11:35:44 2015 +0100" }, "message": "Opt compiler: Correctly require register or FPU register.\n\nAlso add a check that location summary are correctly typed\nwith the HInstruction.\n\nChange-Id: I699762ff4e8f4e321c7db01ea005236ea1934af9\n" }, { "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467", "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab", "parents": [ "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:48:56 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:54:08 2015 +0800" }, "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n" }, { "commit": "13b4718ecd52a674b25eac106e654d8e89872750", "tree": "34d6efd2cda3ceb233118e4d135c4a897f02ea12", "parents": [ "da93333d568f3c5bd8eeb58341d10a332e1d42bf" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Apr 15 16:29:32 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 16 11:09:55 2015 +0100" }, "message": "ART: Remove DCHECKs for boolean type\n\nSince bool and int are interchangeable types, checking whether an\ninput is kPrimBoolean can fail when replaced with 0/1 constant or\na phi. This patch removes the problematic DCHECKs, adds a best-effort\nverification into SSAChecker but leaves the phi case empty until a\nsuitable analysis is implemented.\n\nChange-Id: I31e8daf27dd33d2fd74049b82bed1cb7c240c8c6\n" }, { "commit": "a76a08fed88bd081bcc4d240f1ba3472a2acbbab", "tree": "cd016bb007c3757ab2a6df28bc1a65d6a8e78e44", "parents": [ "acf9b7b7616a9b104e6f2146051d8e14d9cb9030", "9021825d1e73998b99c81e89c73796f6f2845471" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 14:10:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 15 14:10:29 2015 +0000" }, "message": "Merge \"Type MoveOperands.\"" }, { "commit": "9021825d1e73998b99c81e89c73796f6f2845471", "tree": "13e1038931cbb8bf8b8d0f4e3f51553ba1bfa983", "parents": [ "858d28ca2e73a785977f53141e775a7d4841b89d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 11:56:51 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 12:53:42 2015 +0100" }, "message": "Type MoveOperands.\n\nThe ParallelMoveResolver implementation needs to know if a move\nis for 64bits or not, to handle swaps correctly.\n\nBug found, and test case courtesy of Serguei I. Katkov.\n\nChange-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506\n" }, { "commit": "66d126ea06ce3f507d86ca5f0d1f752170ac9be1", "tree": "8e247db17ef085b55725b21c64d292414fd00b32", "parents": [ "9bb3e8e10d7d9230a323511094a9e260062a1473" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Apr 03 16:02:44 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Apr 15 12:51:49 2015 +0100" }, "message": "ART: Implement HBooleanNot instruction\n\nOptimizations simplifying operations on boolean values (boolean\nsimplifier, instruction simplifier) can benefit from having a special\nHInstruction for negating booleans in order to perform more transforms\nand produce faster machine code.\n\nThis patch implements HBooleanNot as \u0027x xor 1\u0027, assuming that booleans\nare 1-bit integers and allowing for a single-instruction negation on\nall supported platforms.\n\nChange-Id: I33a2649c1821255b18a86ca68ed16416063c739f\n" }, { "commit": "cd5bc14b1aa77c4c1e84b5edd800a577411992aa", "tree": "596640bd9066d6f218665dd0adce897bf9d5855e", "parents": [ "6508158f8388847f4cc3693e2cc1dbee6c2c7d18", "69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 15 08:28:59 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 15 08:28:59 2015 +0000" }, "message": "Merge \"ARM64: Remove suspend register.\"" }, { "commit": "8d20011a9de7cd94bee59db3ae8c0cbbf55911d9", "tree": "e8f0656ae879c27175c7287086ee8fd70c24b93a", "parents": [ "85806723695120d183e85e9d12d52340b839b781", "760d8efd535764e54500bf65a944ed3f2a54c123" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 14 16:34:44 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 14 16:34:45 2015 +0000" }, "message": "Merge \"Opt Compiler: ARM64 goodness\"" }, { "commit": "69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d", "tree": "b7f99172f921d7100959ab48210097906794d043", "parents": [ "e015a31e509c3f4de8a90b57b77329ba6609ce2f" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Tue Apr 14 20:04:41 2015 +0800" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 14 17:29:08 2015 +0100" }, "message": "ARM64: Remove suspend register.\n\nIt also clean up build/remove frame used by JNI compiler and generates\nstp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and\noptimizing compiler.\n\nChange-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d\n" }, { "commit": "c34dc9362b9ec624b3bdd97d36b6b2098814cd73", "tree": "c2049b2dc19d318e3917b52ef66608b985d7ac69", "parents": [ "58565098b2298041ccc97371a3cc486df88d51b3" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Sun Apr 12 09:27:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Sun Apr 12 09:30:57 2015 +0100" }, "message": "Move \u0027ret\u0027 instruction generation inside GenerateFrameExit.\n\nChange-Id: I0c594d9a2356a006a5ce8dfd41d307cf7c3704ba\n" }, { "commit": "917f0866f66d3465fa41ddcf9ab09eba2fa78dd3", "tree": "08bc03c6ac1a3d06672edaf4b74ce89db4c28da5", "parents": [ "467e33616472fe92051c75b65327aad87a639f3f", "c6b4dd8980350aaf250f0185f73e9c42ec17cd57" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 17:27:31 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 17:27:31 2015 +0000" }, "message": "Merge \"Implement CFI for Optimizing.\"" }, { "commit": "c6b4dd8980350aaf250f0185f73e9c42ec17cd57", "tree": "ef8d73e37abc04aecb430072a8bc463c73398fee", "parents": [ "dd97393aca1a3ff2abec4dc4f78d7724300971bc" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:32:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 16:47:50 2015 +0100" }, "message": "Implement CFI for Optimizing.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2\n" }, { "commit": "4388dcc30e2a8aa6897a57c44e6865960712a007", "tree": "defbd28425cb5fabfc15fcc365181cd216f6f132", "parents": [ "1b8e8cac2c96f6d2af8e7217f997a30e11c098b5" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Feb 03 10:28:33 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Apr 08 10:39:16 2015 +0100" }, "message": "Opt compiler: ARM64: Use TBZ and TBNZ in VisitIf.\n\nTBZ and TBNZ have a short range. Now that VIXL supports\nveneers, we can use them safely without the danger of\nrunning out of range.\n\nChange-Id: Iaf77a441ccf86282c1793a2213a69a2091ca829a\n" }, { "commit": "760d8efd535764e54500bf65a944ed3f2a54c123", "tree": "70038c0f55dc41f833b24f6528daedddf0f72e34", "parents": [ "fc67542a93be3381f9c6cf226a6c5a6f30ed6e82" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sat Mar 28 18:09:56 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Apr 02 17:27:02 2015 +0100" }, "message": "Opt Compiler: ARM64 goodness\n\nThis patch:\n* Switches on PreferAcquireRelease() (used to decide if load/store\nvolatile should use acquire release-semantics or explicit memory\nbarriers). Note that for ARMv8 CPUs we should always prefer this\n(as proved by synthetic benchmarks on A53, A57 and Denver).\n\n* Enables the use of constants for HBoundsCheck\n\nChange-Id: I42524451772c05a1c74af73e97a59a95f49ba6d4\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "fc3ee8f0c1fa0a5a6ca87c0f9c4320c5bc00e062", "tree": "b00517ce55d2b24e491695f2be8b5b3dcfdde3b0", "parents": [ "fc67542a93be3381f9c6cf226a6c5a6f30ed6e82" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Apr 02 12:27:30 2015 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Apr 02 17:25:27 2015 +0100" }, "message": "Revert \"ART: Valgrind hotfix for VIXL 1.9\"\n\nFixed in external/vixl and upstream VIXL.\n\nChange-Id: I7d1901da06a7c1517c88a2583bc668a3e23ef852\n" }, { "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648", "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b", "parents": [ "a109632b240f3c9355ca95500f6f48e4478e3c51" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:03:04 2015 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:05:13 2015 -0700" }, "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n" }, { "commit": "75fda57d0aa3106c7ebad88656c3eea056e5ea6a", "tree": "dc7c9fadb547a0cab87528e09de808d0b07f78c6", "parents": [ "3360a990b79e4f7759b28d351908982d1953572e" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Apr 01 00:36:42 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Apr 01 00:36:42 2015 -0700" }, "message": "ART: Valgrind hotfix for VIXL 1.9\n\nMake sure recommended_checkpoint_ is initialized in the VIXL macro\nassembler by calling EmitLiteralPool with an empty pool.\n\nChange-Id: I08589b8fb092a33a8f4aad824e91b5c16ff761b6\n" }, { "commit": "d75948ac93a4a317feaf136cae78823071234ba5", "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d", "parents": [ "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 09:53:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 12:01:40 2015 +0000" }, "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n" }, { "commit": "46e2a3915aa68c77426b71e95b9f3658250646b7", "tree": "2b0a4470b05291894db73c631fe94f0fdff8c46b", "parents": [ "bce0855ca1dbb1fa226c5b6a81760272ce0b64ef" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Mar 16 17:31:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 24 17:28:37 2015 +0000" }, "message": "ART: Boolean simplifier\n\nThe optimization recognizes the negation pattern generated by \u0027javac\u0027\nand replaces it with a single condition. To this end, boolean values\nare now consistently assumed to be represented by an integer.\n\nThis is a first optimization which deletes blocks from the HGraph and\ndoes so by replacing the corresponding entries with null. Hence,\nexisting code can continue indexing the list of blocks with the block\nID, but must check for null when iterating over the list.\n\nChange-Id: I7779da69cfa925c6521938ad0bcc11bc52335583\n" }, { "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430", "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0", "parents": [ "e295e6ec5beaea31be5d7d3c996cd8cfa2053129" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n" }, { "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129", "tree": "4d8a657d23d511743ce35bee596544d7f652efdb", "parents": [ "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Sat Mar 07 06:37:59 2015 -0800" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Mar 23 16:39:37 2015 -0700" }, "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n" }, { "commit": "5af26bd446660bc5d13dd6ff9470e6920a51e26e", "tree": "a7a8ffcef09783b7ca91c70aa90e48efaf650b38", "parents": [ "af2bec33e5f124e37e9dbbe0fef1261411bd372d", "2d35d9d7490ef3880ee366ccbf8f6e791f398c47" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 23 16:44:35 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Mar 23 16:44:36 2015 +0000" }, "message": "Merge \"Opt Compiler: Materialise constants that cannot be encoded\"" }, { "commit": "68e15009173f92fe717546a621b56413d5e9fba1", "tree": "460f18693f53bcbcc6f79b03f8a211f271c973a7", "parents": [ "1311ef7226f6147f2ef8c491321972a79d73914a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 17 16:16:49 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 17 16:23:17 2015 +0000" }, "message": "PREOPT compiles using dex2oatd so don\u0027t emit debug instructions.\n\nChange-Id: I8d2ab8d956ad0ce313928918c658d49f490ad081\n" }, { "commit": "2d35d9d7490ef3880ee366ccbf8f6e791f398c47", "tree": "5e512b5da7d7c290d69e4437436feb15ccad5ffc", "parents": [ "8fff8c66738b35bafc5318e408afa21c34c57ff3" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sun Feb 22 22:08:01 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Mar 17 10:47:51 2015 +0000" }, "message": "Opt Compiler: Materialise constants that cannot be encoded\n\nThe VIXL MacroAssembler deals gracefully with any immediate. However\nwhen the constant has multiple uses and cannot be encoded in the\ninstruction\u0027s immediate field we are better off using a register for\nthe constant and thus sharing the constant generation between multiple\nuses.\n\nEg:\n var +\u003d #Const; // #Const cannot be encoded.\n var +\u003d #Const;\n\nBefore: After:\n mov wip0, #Const mov w4, #Const\n add w0, w0, wip0 add w0, w0, w4\n mov wip0, #Const add w0, w0, w4\n add w0, w0, wip0\n\nChange-Id: Ied8577c879845777e52867aced16b2b45e06ac6c\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "eeefa1276e83776f08704a3db4237423b0627e20", "tree": "d7c647ca77703f3712f567704f40b00d59a125de", "parents": [ "02c0bac34c246c1bd974dbb86d292d4b52ba98e4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:52:59 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 16 10:48:21 2015 +0000" }, "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n" }, { "commit": "a8ac9130b872c080299afacf5dcaab513d13ea87", "tree": "2bd0a2a88cbb6e7a3ae79dff84c466bed9189eb5", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:36:36 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:47:44 2015 +0000" }, "message": "Refactor code in preparation of correct stack maps in slow path.\n\nMove the logic of saving/restoring live registers in slow path\nin the SlowPathCode method. Also add a RecordPcInfo helper to\nSlowPathCode, that will act as the placeholder of saving correct\nstack maps.\n\nChange-Id: I25c2bc7a642ef854bbc8a3eb570e5c8c8d2d030c\n" }, { "commit": "3ce57abd8fe50a0a772d14e033a9e7c34beff6cb", "tree": "4be0ac5a10e6fd0c1d9e52feb169e89b1f77206c", "parents": [ "758c2f65805564e0c51cccaacf8307e52a9e312b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 12 11:06:03 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 12 11:06:03 2015 +0000" }, "message": "Revert \"Opt Compiler: Materialise constants that cannot be encoded\"\n\nFails building the core image.\n\nThis reverts commit 758c2f65805564e0c51cccaacf8307e52a9e312b.\n\nChange-Id: Ic3ebd8a08a3d17a513d820035b430f6de4125866\n" }, { "commit": "758c2f65805564e0c51cccaacf8307e52a9e312b", "tree": "ec8bbbe69fa3f263dd91763fe1bef81cf090f468", "parents": [ "637455782147a41fbde2e284c49ca5e02d3444c2" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sun Feb 22 22:08:01 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Wed Mar 11 17:45:09 2015 +0000" }, "message": "Opt Compiler: Materialise constants that cannot be encoded\n\nThe VIXL MacroAssembler deals gracefully with any immediate. However\nwhen the constant has multiple uses and cannot be encoded in the\ninstruction\u0027s immediate field we are better off using a register for\nthe constant and thus sharing the constant generation between multiple\nuses.\n\nEg:\n var +\u003d #Const; // #Const cannot be encoded.\n var +\u003d #Const;\n\nBefore: After:\n mov wip0, #Const mov w4, #Const\n add w0, w0, wip0 add w0, w0, w4\n mov wip0, #Const add w0, w0, w4\n add w0, w0, wip0\n\nChange-Id: I8d1f620872d1241cf582fb4f3b45b5091b790146\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "579885a26d761f5ba9550f2a1cd7f0f598c2e1e3", "tree": "58d144157b7a24bbdf7f8892631a15abeefa2c9f", "parents": [ "2eb5168bd9e43b80452eaee5be32c063e124886e" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sun Feb 22 20:51:33 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Mon Mar 02 14:16:56 2015 +0000" }, "message": "Opt Compiler: ARM64: Enable explicit memory barriers over acquire/release\n\nImplement remaining explicit memory barrier code paths and temporarily\nenable the use of explicit memory barriers for testing.\n\nThis CL also enables the use of instruction set features in the ARM64\nbackend. kUseAcquireRelease has been replaced with PreferAcquireRelease(),\nwhich for now is statically set to false (prefer explicit memory barriers).\n\nPlease note that we still prefer acquire-release for the ARM64 Optimizing\nCompiler, but we would like to exercise the explicit memory barrier code\npath too.\n\nChange-Id: I84e047ecd43b6fbefc5b82cf532e3f5c59076458\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "d8ef2e991a1a65f47a26a1eb8c6b34c92b775d6b", "tree": "d3aa88b42db86584724a2566da304aff70be5613", "parents": [ "a48c573d2351177d878e36e003f0cdf4d7f9328f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 24 16:02:06 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 24 16:04:07 2015 +0000" }, "message": "not-int can also take non-int (byte and short) instructions.\n\nSo we should use the result-type instead if the input type\nfor knowning what instruction to use.\n\nBug: 19454010\nChange-Id: I88782ad27ae8c8e1b7868afede5057d26f14685a\n" }, { "commit": "36fb59b15fbca20c22e9daf2943fcfeebc97848f", "tree": "1d254d5abd062512efaad2c03f97b592f3031808", "parents": [ "1382e569b31f4fab61fcfca5aa93275a2a3cb757", "b1498f67b444c897fa8f1530777ef118e05aa631" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Feb 20 14:27:00 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Feb 20 14:27:01 2015 +0000" }, "message": "Merge \"Improve type propagation with if-contexts\"" }, { "commit": "b1498f67b444c897fa8f1530777ef118e05aa631", "tree": "7ff4709329b0ba752a6111103a76fcea896a3adb", "parents": [ "acf735c13998ad2a175f5a17e7bfce220073279d" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Feb 16 13:13:29 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Feb 20 14:26:08 2015 +0000" }, "message": "Improve type propagation with if-contexts\n\nThis works by adding a new instruction (HBoundType) after each `if (a\ninstanceof ClassA) {}` to bound the type that `a` can take in the True-\ndominated blocks.\n\nChange-Id: Iae6a150b353486d4509b0d9b092164675732b90c\n" }, { "commit": "1382e569b31f4fab61fcfca5aa93275a2a3cb757", "tree": "b093c19c98c0cf397cda84a1fcb30dbf4ed8fc0c", "parents": [ "4fe292e2b6ba3980605373f183055a374084c65b", "9341546f1e5177a0328c67c5899ee81d19bd5d88" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Feb 20 11:21:28 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Feb 20 11:21:30 2015 +0000" }, "message": "Merge \"Opt compiler: ARM64: Optimise floating-point comparison with 0.0.\"" }, { "commit": "d6138ef1ea13d07ae555542f8898b30d89e9ac9a", "tree": "a8ffd5fd966512fd280bc1b3214f4e57a9e1805f", "parents": [ "92095533ac28879ddd8b44b559d700527ca12b8a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 14:48:53 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 19 14:01:18 2015 +0000" }, "message": "Ensure the graph is correctly typed.\n\nWe used to be forgiving because of HIntConstant(0) also being\nused for null. We now create a special HNullConstant for such uses.\n\nAlso, we need to run the dead phi elimination twice during ssa\nbuilding to ensure the correctness.\n\nChange-Id: If479efa3680d3358800aebb1cca692fa2d94f6e5\n" }, { "commit": "9341546f1e5177a0328c67c5899ee81d19bd5d88", "tree": "80ffb6a99abae69d9a6b1b4ef17ee6d4f68c02d6", "parents": [ "6e27f82193a8f54cd8ecdc8fb2c4c1adadafbaf4" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Feb 17 15:08:20 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Feb 17 15:08:20 2015 +0000" }, "message": "Opt compiler: ARM64: Optimise floating-point comparison with 0.0.\n\nChange-Id: I297ed92445f20fae2ebf301e90e97772072da364\n" }, { "commit": "a3ec39425e09f92421775d1485660eb633f97aec", "tree": "6b260d01cf8aa3bb0eaa4e45792302902f54952c", "parents": [ "e5f5953e744060fde3b4489cea4d934d529e3e32" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Sun Feb 15 18:39:46 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Mon Feb 16 19:20:16 2015 +0800" }, "message": "Opt compiler: ARM64: Fix blocking fp registers.\n\nVIXL reserved float point registers has not been blocked correctly.\n\nChange-Id: Ie7131d86bbaff48c431e3e26abd2fa26389ac687\n" }, { "commit": "c0572a451944f78397619dec34a38c36c11e9d2a", "tree": "2cc6f3c6f5ad45b4b85fb62627e797fe7e7734e1", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 14:35:25 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 17:37:57 2015 +0000" }, "message": "Optimize leaf methods.\n\nAvoid suspend checks and stack changes when not needed.\n\nChange-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628\n" }, { "commit": "3d087decd1886b818adcccd4f16802e5e54dd03e", "tree": "2be4d4a62d972e33150b517ff71b3023a095c8bd", "parents": [ "ca9a26859d2ca8e106316dd5f16b60a325f0533c" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Wed Jan 28 11:57:05 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Feb 05 20:12:31 2015 +0000" }, "message": "Opt Compiler: ARM64: Enable Callee-saved register, as defined by AAPCS64.\n\nFor now we block kQuickSuspendRegister - x19, since Quick and the runtime\nuse this as a suspend counter register.\n\nChange-Id: I090d386670e81e7924e4aa9a3864ef30d0580a30\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "cb1b00aedd94785e7599f18065a0b97b314e64f6", "tree": "fdde101b239c66325243bcc60d3d94f07ff56492", "parents": [ "9544368685b4aa65e746332e602491a3e8e5b247" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 28 14:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 30 17:43:16 2015 +0000" }, "message": "Use the non access check entrypoint when possible.\n\nChange-Id: I0b53d63141395e26816d5d2ce3fa6a297bb39b54\n" }, { "commit": "69b56b2f747992028ea838377422327a2bec49d6", "tree": "d5eea7c618cfc3fefc275eb58747875cef82797b", "parents": [ "193f785e471b38009f7406a030d741ae415c8bb0", "542361f6e9ff05e3ca1f56c94c88bc3efeddd9c4" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 29 18:52:34 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 29 18:52:35 2015 +0000" }, "message": "Merge \"Introduce primitive type helpers.\"" }, { "commit": "542361f6e9ff05e3ca1f56c94c88bc3efeddd9c4", "tree": "f9c914c1ca168d1c93148b95bec7f3e8b0659542", "parents": [ "c9ff6b112d25657128f9a7251e253b1382b0f1b9" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Jan 29 16:57:31 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Jan 29 16:57:31 2015 +0000" }, "message": "Introduce primitive type helpers.\n\nChange-Id: I81e909a185787f109c0afafa27b4335050a0dcdf\n" }, { "commit": "0a299b9305d42074a47a7922aff855c840a76cfd", "tree": "3e31c006b7906447a3e5576f9d15b588b4c5a97d", "parents": [ "c9ff6b112d25657128f9a7251e253b1382b0f1b9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 11:39:44 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 11:39:44 2015 +0000" }, "message": "Fix bad rebase.\n\nChange-Id: Ia66c5ec4a612908b749b058d85f374d1f1b72a2a\n" }, { "commit": "1cf95287364948689f6a1a320567acd7728e94a3", "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed", "parents": [ "4a50662eeaa0b1a26be66e7584fb765151dabc59" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 10:52:14 2015 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n" }, { "commit": "878d58cbaf6b17a9e3dcab790754527f3ebc69e5", "tree": "1c1af4ef938ad06a783da51e2c6276d6b0628da6", "parents": [ "b80c3154d3b6359d8ad4ce50d3a6a68224400cdd" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 23:24:00 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 28 15:32:40 2015 -0800" }, "message": "ART: Arm64 optimizing compiler intrinsics\n\nImplement most intrinsics for the optimizing compiler for Arm64.\n\nChange-Id: Idb459be09f0524cb9aeab7a5c7fccb1c6b65a707\n" }, { "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c", "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8", "parents": [ "c698b78a17043d8898deb817098181595fbe734e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 22 13:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 09:20:42 2015 +0000" }, "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n between backends.\n- Remove explicit stack overflow check support: we need to adjust\n them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "b6b114c02b8bacd3b5d64e646fdaefa03c069c61", "tree": "cd702f32a9241c94d9e0d12828f3bcb0291b087b", "parents": [ "73d8fe409fbf2cb9665779690660ccc852d60431", "fa93b504b324784dd9a96e28e6e8f3f1b1ac456a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 17:33:43 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 21 17:33:43 2015 +0000" }, "message": "Merge \"Do not use HNot for creating !bool.\"" }, { "commit": "fa93b504b324784dd9a96e28e6e8f3f1b1ac456a", "tree": "8a3e691268657db75a69c8d644e5a963abee66d6", "parents": [ "1147eeed2ffc82ac9b1405f9fb0a6cbc8560c42b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 15:44:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 17:03:29 2015 +0000" }, "message": "Do not use HNot for creating !bool.\n\nHNot folds to ~, not !.\n\nChange-Id: I681f968449a2ade7110b2f316146ad16ba5da74c\n" }, { "commit": "6c2dff8ff8e1440fa4d9e1b2ba2a44d036882801", "tree": "da2d48b3d84733ac6b29194cb2f624693a643d48", "parents": [ "22c9285142169691eb2a9e2d4a49751fc7e57c2a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 14:56:54 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 15:19:06 2015 +0000" }, "message": "Revert \"Revert \"Fully support pairs in the register allocator.\"\"\n\nThis reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f.\n\nChange-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5\n" }, { "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea", "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242", "parents": [ "4d2c611bf17ff309abfa152e56c0b98a21ec8787" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 12 18:45:46 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 14:26:35 2015 +0000" }, "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n" }, { "commit": "c399fdc442db82dfda66e6c25518872ab0f1d24f", "tree": "6f0841ad5e8e80b09e34e084ae8eac336bce73a2", "parents": [ "41aedbb684ccef76ff8373f39aba606ce4cb3194" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "message": "Revert \"Fully support pairs in the register allocator.\"\n\nLibcore tests fail.\n\nThis reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194.\n\nChange-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c\n" }, { "commit": "41aedbb684ccef76ff8373f39aba606ce4cb3194", "tree": "94929237a0fe9b24dda7409d9433f07e82af4461", "parents": [ "97c89e4c081dcf4bacbde70b6609e366c9da417e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 10:49:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 11:27:57 2015 +0000" }, "message": "Fully support pairs in the register allocator.\n\nEnabled on ARM for longs and doubles.\n\nChange-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b\n" }, { "commit": "93edf73a5fecd526920fbd870068fa592376ac8a", "tree": "c24e0223e6ff0d1ec2eefeb1d863c1c32ca5f65c", "parents": [ "97d9f286971a4c1eec70e08f9f18f990d21780d5" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Jan 20 20:14:07 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Jan 20 20:14:07 2015 +0000" }, "message": "Use CompilerOptions for implicit stack overflow checks\n\nChange-Id: I52744382a7e3d2c6c11a43e027d87bf43ec4e62b\n" }, { "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f", "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f", "parents": [ "12c03ac7575db242a6f35739bb459e8277115da4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Jan 08 17:35:35 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Jan 16 17:27:03 2015 +0000" }, "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n" }, { "commit": "71fb52fee246b7d511f520febbd73dc7a9bbca79", "tree": "444d91e910433aaf887bbdada28dfaa3160bebc2", "parents": [ "420457e6040184a6e1639a4c84fcc8e237bd8a3d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 29 17:43:08 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 10:21:11 2015 -0800" }, "message": "ART: Optimizing compiler intrinsics\n\nAdd intrinsics infrastructure to the optimizing compiler.\n\nAdd almost all intrinsics supported by Quick to the x86-64 backend.\nFurther intrinsics require more assembler support.\n\nChange-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807\n" }, { "commit": "3d5872eb090a04a9444b5621d381eec3846f47a3", "tree": "121bc995f1bb702cf1a01e7279dfeb46fda054ba", "parents": [ "b994c437ae8ec6b9d85ceb1fb11e4c97eace32ef", "1cc7dbabd03e0a6c09d68161417a21bd6f9df371" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jan 05 19:26:08 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 05 19:26:09 2015 +0000" }, "message": "Merge \"ART: Reorder entrypoint argument order\"" }, { "commit": "02d81cc8d162a31f0664249535456775e397b608", "tree": "8bce70d3d44dcc9384d72e4edc1505e4d1a6ea07", "parents": [ "8558375377946aabbbda6ab584e13f754590bd89" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Mon Jan 05 16:08:49 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 05 18:23:33 2015 +0000" }, "message": "Opt Compiler: ARM64: Add support for rem-float, rem-double and volatile.\n\nAdd support for rem-float, rem-double and volatile memory accesses\nusing acquire-release and memory barriers.\n\nChange-Id: I96a24dff66002c3b772c3d8e6ed792e3cb59048a\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "1cc7dbabd03e0a6c09d68161417a21bd6f9df371", "tree": "8557bdff971e366909351af95a7c8ead82792986", "parents": [ "5e0a9849d4e353c3726095b65ab07cefce40a636" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Dec 17 18:43:01 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 29 10:52:02 2014 -0800" }, "message": "ART: Reorder entrypoint argument order\n\nShuffle the ArtMethod* referrer backwards for easier removal.\n\nClean up ARM \u0026 MIPS assembly code.\n\nChange some macros to make future changes easier.\n\nChange-Id: Ie2862b68bd6e519438e83eecd9e1611df51d7945\n" }, { "commit": "6048838af46f41c08c4132ba242040dc49bd5f23", "tree": "5124300bf9a7106d534e126b1926cc9d787ae2dc", "parents": [ "ca747ea9951188dbc6f5217d49aca34aeadcc2a6", "5b4b898ed8725242ee6b7229b94467c3ea3054c8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:46:12 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 18 17:46:13 2014 +0000" }, "message": "Merge \"Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\"" }, { "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8", "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519", "parents": [ "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n" }, { "commit": "e408f8c6ac0ee80543ee1a695695e8917e45eaf3", "tree": "8637636ea603b134b410cf535281fb56249f9d55", "parents": [ "452a8bec86e7795c99f774e81c02f12f1b1e502f", "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 15:49:52 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 18 15:49:53 2014 +0000" }, "message": "Merge \"Don\u0027t block quick callee saved registers for optimizing.\"" }, { "commit": "6004796d6c630696127df2494dcd4f30d1367a34", "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97", "parents": [ "407d77f344cfbdbbfb50531c5f0766bc0892e2fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 00:01:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 14:59:50 2014 +0000" }, "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n" }, { "commit": "4e44c829e282b3979a73bfcba92510e64fbec209", "tree": "42375a128b28bb886955214336f63391dfc41d5c", "parents": [ "390f59f9bec64fd81b05e796dfaeb03ab6d4cc81" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 17 12:25:12 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 17 12:25:12 2014 +0000" }, "message": "Revert \"Small optimization for recursive calls: avoid dex cache.\"\n\nFails on target.\n\nThis reverts commit 390f59f9bec64fd81b05e796dfaeb03ab6d4cc81.\n\nChange-Id: Ic3865b8897068ba20df0fbc2bcf561faf6c290c1\n" }, { "commit": "390f59f9bec64fd81b05e796dfaeb03ab6d4cc81", "tree": "d418b4a488390d718144bf5a5a180d965d1d762e", "parents": [ "240016da1d6615b26c8342bdeb4bae381570ac47" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 17 11:53:33 2014 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: Ic4054b6c38f0a2a530ba6ef747647f86cee0b1b8\n" }, { "commit": "e53798a7e3267305f696bf658e418c92e63e0834", "tree": "8979bbed96b107a5a6bbae9285ff4e0c362dad95", "parents": [ "e6c0cdd11097dd72275ac24f1e98217c299d973e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 10:31:54 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 22:52:27 2014 +0000" }, "message": "Inlining support in optimizing.\n\nCurrently only inlines simple things that don\u0027t require an\nenvironment, such as:\n- Returning a constant.\n- Returning a parameter.\n- Returning an arithmetic operation.\n\nChange-Id: Ie844950cb44f69e104774a3cf7a8dea66bc85661\n" }, { "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c", "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955", "parents": [ "776b880f66edb21cb3b4225877e494ec7a9ec1a2" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 10:36:50 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 14:36:14 2014 +0000" }, "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7" }, { "commit": "01fcc9ee556f98d0163cc9b524e989760826926f", "tree": "db932611fcfb1390c761ae589a99dee5e956c271", "parents": [ "dff1069220465f93dc2e3636a0acd7522a5ba639" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 14:16:20 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 14:38:56 2014 +0000" }, "message": "Remove type conversion nodes converting to the same type.\n\nWhen optimizing, we ensure these conversions do not reach the\ncode generators. When not optimizing, we cannot get such situations.\n\nChange-Id: I717247c957667675dc261183019c88efa3a38452\n" }, { "commit": "02164b352a1474c616771582ca9a73a2cc514c1f", "tree": "6c124ec6e19f18343b69df8cddcb74e17447f294", "parents": [ "32f5b4d2c8c9b52e9522941c159577b21752d0fa" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Nov 13 14:05:07 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 13:10:25 2014 +0000" }, "message": "Opt Compiler: Arm64: Add support for more IRs plus various fixes.\n\nAdd support for more IRs and update others.\n\nChange-Id: Iae1bef01dc3c0d238a46fbd2800e71c38288b1d2\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa", "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Nov 25 20:05:46 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 12:02:58 2014 +0000" }, "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "eace45873190a27302b3644c32ec82854b59d299", "tree": "73fbf327839263b6847bdc4359ac1dbea2b897e3", "parents": [ "8ac8d5556fae9c728bcebcc9036a1bbf40087c76" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Nov 24 18:29:54 2014 -0800" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Nov 25 16:02:04 2014 -0800" }, "message": "Move dexCacheStrings from ArtMethod to Class\n\nAdds one load for const strings which are not direct.\n\nSaves \u003e\u003d 60KB of memory avg per app.\nImage size: -350KB.\n\nBug: 17643507\nChange-Id: I2d1a3253d9de09682be9bc6b420a29513d592cc8\n\n(cherry picked from commit f521f423b66e952f746885dd9f6cf8ef2788955d)\n" }, { "commit": "9aec02fc5df5518c16f1e5a9b6cb198a192db973", "tree": "fe924b37f395af1bb50f55ee6c87c66b727f00af", "parents": [ "20032e512c003a8f42735c4e1eca19c1472bb95e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 18 23:06:35 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 24 16:06:55 2014 +0000" }, "message": "[optimizing compiler] Add shifts\n\nAdded SHL, SHR, USHR for arm, x86, x86_64.\n\nChange-Id: I971f594e270179457e6958acf1401ff7630df07e\n" }, { "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6", "tree": "3db61320369973e463f67927a8983d7eb0d9f860", "parents": [ "255a5bde2f0014dc86a564555106a4291c0867b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n" }, { "commit": "4a962e5373bc0992d6e9ba6a43bb65845e7a8783", "tree": "21728df3c8be24b1ad132055ee8652bbb03b0f29", "parents": [ "f90866a4966eda94d1b28767c62504ef97974e51" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Nov 18 13:48:34 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Nov 18 13:48:34 2014 -0800" }, "message": "ART: Build fix\n\nChange-Id: I0c4d1c2981bdfb95e12c8c624826349281ada0cf\n" }, { "commit": "2d7210188805292e463be4bcf7a133b654d7e0ea", "tree": "7705a3bf841ae44b2396728fa22ed0b5dcb44dbf", "parents": [ "e0491682d101c69bf88c3c24a965312129cbfa38" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Nov 10 11:08:06 2014 -0800" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Nov 18 12:27:37 2014 -0800" }, "message": "Change 64 bit ArtMethod fields to be pointer sized\n\nChanged the 64 bit entrypoint and gc map fields in ArtMethod to be\npointer sized. This saves a large amount of memory on 32 bit systems.\nReduces ArtMethod size by 16 bytes on 32 bit.\n\nTotal number of ArtMethod on low memory mako: 169957\nImage size: 49203 methods -\u003e 787248 image size reduction.\nZygote space size: 1070 methods -\u003e 17120 size reduction.\nApp methods: ~120k -\u003e 2 MB savings.\n\nSavings per app on low memory mako: 125K+ per app\n(less active apps -\u003e more image methods per app).\n\nSavings depend on how often the shared methods are on dirty pages vs\nshared.\n\nTODO in another CL, delete gc map field from ArtMethod since we\nshould be able to get it from the Oat method header.\n\nBug: 17643507\n\nChange-Id: Ie9508f05907a9f693882d4d32a564460bf273ee8\n\n(cherry picked from commit e832e64a7e82d7f72aedbd7d798fb929d458ee8f)\n" }, { "commit": "67555f7e9a05a9d436e034f67ae683bbf02d072d", "tree": "9a01b7c69032b08b3c55c18076f68c1e397d8a35", "parents": [ "bf75c5cf32a47eecadcc5e4a324237c1f1d09cde" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Nov 18 10:55:16 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 18 15:36:36 2014 +0000" }, "message": "Opt compiler: Add support for more IRs on arm64.\n\nChange-Id: I4b6425135d1af74912a206411288081d2516f8bf\n" }, { "commit": "bacfec30ee9f2f6fdfd190f11b105b609938efca", "tree": "1fb08fa38b27627ab59a54895ef098b43bb70ce1", "parents": [ "ff5298ff1640b730ee62c90ca78fc96b7ee82ec4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Nov 14 15:54:36 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 17 11:19:35 2014 +0000" }, "message": "[optimizing compiler] Add REM_INT, REM_LONG\n\n- for arm, x86, x86_64\n- minor cleanup/fix in div tests\n\nChange-Id: I240874010206a5a9b3aaffbc81a885b94c248f93\n" }, { "commit": "9574c4b5f5ef039d694ac12c97e25ca02eca83c0", "tree": "2ad3cb7ffaf3579b9ca2a7bb0d7d7e99b3c758b6", "parents": [ "59321e0e10ea09694efecf6154704e2743b9bffd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 13:19:37 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 13:55:36 2014 +0000" }, "message": "Implement and/or/xor in optimizing.\n\nChange-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec\n" }, { "commit": "b7baf5c58d0e864f8c3f889357c51288aed42e61", "tree": "a665b8b4935f99eab4bb81ad703fe0ec4efc1d10", "parents": [ "15136cb06f0a0fd5f60a832c33870de53c74696a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 11 16:29:44 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 11:41:19 2014 +0000" }, "message": "Implement monitorenter/monitorexit.\n\nPretty simple as they just invoke the runtime.\n\nChange-Id: I5fcb2c783deac27e55e28d8b3da3e68ea4b77363\n" }, { "commit": "57a88d4ac205874dc85d22f9f6a9ca3c4c373eeb", "tree": "af321a2f2d4555f56e0ffcbe31cb4e313b8d35c7", "parents": [ "401da919c67ceb8fbcac81596327ecc10b73389b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 10 15:09:21 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 09:18:41 2014 +0000" }, "message": "Implement checkcast for optimizing.\n\n- Ended up not using HTypeCheck because of how\n instanceof and checkcast end up having different logic\n for code generation.\n\n- Fix a x86_64 assembler bug triggered by now enabling\n more methods to be compiled. Difficult to test today\n without b/18117217.\n\nChange-Id: I3022e7ae03befb1d10bea9637ad21fadc430abe0\n" }, { "commit": "fc19de8b201475231751b9df08fce01a093e5c2b", "tree": "7c0e9c923a37d059f1707156d69f4908aca308ac", "parents": [ "a89086e3be94fb262c4c4feb15241b30616c3b8f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 17:13:31 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Nov 10 17:31:38 2014 +0000" }, "message": "Opt compiler: Add arm64 support for a few more IRs.\n\nChange-Id: I781ddcbc61eb2b04ae80b1c7697e1ed5694bd5b9" }, { "commit": "a89086e3be94fb262c4c4feb15241b30616c3b8f", "tree": "82878d8a6c5418c43ff45857b81db7c88af7d455", "parents": [ "974bc2747b345667e07692109d63675ec50955a3" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 17:13:25 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Nov 10 17:31:17 2014 +0000" }, "message": "Opt compiler: Add arm64 support for floating-point.\n\nChange-Id: I0d97ab0f5ab770fee62c819505743febbce8835e" }, { "commit": "9806199033fc2fb61bfd2260f0156d1b38d56beb", "tree": "14a5cd067fb01ace19fb5e0f7d494bd9e8744845", "parents": [ "255507d9c695aa9c774b882308faa8278382006b", "52839d17c06175e19ca4a093fb878450d1c4310d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 10 10:36:59 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 10 10:37:00 2014 +0000" }, "message": "Merge \"Support invoke-interface in optimizing.\"" }, { "commit": "52839d17c06175e19ca4a093fb878450d1c4310d", "tree": "552ea632ad4d1f688bdfd04b66102e25312bd237", "parents": [ "a453307957afdc3ef0a7988025539ab8919464bc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 17:47:25 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 10 10:33:37 2014 +0000" }, "message": "Support invoke-interface in optimizing.\n\nChange-Id: Ic18d7c3d2810557231caf0571956e0c431f5d384\n" }, { "commit": "582271847f58fd88db95894984f8d6b83dd90719", "tree": "ded34db8f18c80aa5751762fd8385637e969b911", "parents": [ "da6b3e5417d3d14849a70bea818dec56bbb25e6f", "4e5965100bd508162c4990fc8e779d6c25e38b9c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 15:59:41 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Nov 07 15:59:42 2014 +0000" }, "message": "Merge \"Opt compiler: Fix HNot on ARM64.\"" }, { "commit": "da6b3e5417d3d14849a70bea818dec56bbb25e6f", "tree": "55f87dd39618b627ff331293f7b4ed2abd91fc31", "parents": [ "6b80013e5fb8c858e1a249ae6fcfd27a8f1e817a", "6f5c41f9e409bc4da53b5d7c385202255e391e72" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 15:57:49 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Nov 07 15:57:50 2014 +0000" }, "message": "Merge \"Implement instanceof in optimizing.\"" }, { "commit": "4e5965100bd508162c4990fc8e779d6c25e38b9c", "tree": "b40656b04506e3f56e398dd4f04880a330676559", "parents": [ "6b80013e5fb8c858e1a249ae6fcfd27a8f1e817a" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 15:56:50 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 15:56:50 2014 +0000" }, "message": "Opt compiler: Fix HNot on ARM64.\n" }, { "commit": "5dffc05f6a64d44b4045f3bc00ca40082452875d", "tree": "c3235fd9776ef857c3df59705956b1f479f57632", "parents": [ "8d7ef0f6a443676c00c5df0ae97f1090296b1ec5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 15:36:32 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 15:36:32 2014 +0000" }, "message": "Fix codegen_test: HNot has only one input.\n\nChange-Id: I13e54d39dfbf80593f2e9592dbd286c54938e95a\n" }, { "commit": "6f5c41f9e409bc4da53b5d7c385202255e391e72", "tree": "bea48b3f23fdac7d566dd3b32dde1f86014b5a02", "parents": [ "86fe4e41720cab85e3e40c45c0436521e56b25d5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 06 08:59:20 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 15:32:37 2014 +0000" }, "message": "Implement instanceof in optimizing.\n\n- Only fast-path for now: null or same class.\n- Use pQuickInstanceofNonTrivial for slow path.\n\nChange-Id: Ic5196b94bef792f081f3cb4d15157058e1381e6b\n" }, { "commit": "fb4e5fac5fbaf9171a38aeb4bc082f3c2b3122dd", "tree": "05c6b632ce21725821e060890feb4bcad8ca3a00", "parents": [ "86fe4e41720cab85e3e40c45c0436521e56b25d5" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Nov 06 12:41:16 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 15:05:38 2014 +0000" }, "message": "Opt compiler: specify that inputs and outputs don\u0027t overlap on arm64.\n\nChange-Id: I062b70c6534c0d203674dccddbf11f94da72cdb4\n" }, { "commit": "f43083d560565aea46c602adb86423daeefe589d", "tree": "6c812e88723c40ee77ab5c9ba38625a10cc9b364", "parents": [ "de87f405a5f8a4ffd57f01d0d667188e8f0ca8cd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 10:48:10 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 14:43:19 2014 +0000" }, "message": "Do not update Out after it has a valid location.\n\nSlow paths use LocationSummary to know where to move\nthings around, and they are executed at the end of the\ncode generation.\n\nThis fix is needed for https://android-review.googlesource.com/#/c/113345/.\n\nChange-Id: Id336c6409479b1de6dc839b736a7234d08a7774a\n" } ], "next": "e257d2c27f5565fb55de9122e093371ea2671271" }