)]}' { "log": [ { "commit": "c778226256bced7105fcbb1a028dfbba135c6c29", "tree": "0191f8a968593112bcc66d8dd6efb572b888a0ed", "parents": [ "8799ea0a82bbe7d4fbd2375ae20fa8a720c887d4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 13 16:20:08 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 13 17:05:02 2017 -0800" }, "message": "Introduce a number of SIMD extensions for x86/x86_64 (SSE).\n\nRationale:\nAs a first step exploring how useful an ART vectorizer may be,\nintroducing a number of floating-point SIMD instructions.\n\nTest: assembler_x86[_64]_test\nBug: 34083438\nChange-Id: I0285dd9fca51f31875a6bbe728f873c48089940d\n" }, { "commit": "ae7ff92c430aa12484ff8258ee4ed13421ac7934", "tree": "32774f5b3b0f96b921145a4af62dce182882fb7c", "parents": [ "6e5fa09510c7280168e040382d27dd8b55760d9a" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Thu Oct 06 14:59:19 2016 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Thu Oct 13 17:26:37 2016 +0000" }, "message": "jni: Add read barrier fast path to jni compiler\n\nStatic method dispatch via JNI requires a read barrier\nfor the ArtMethod::GetDeclaringClass() load before adding it to the\nJNI StackHandleScope.\n\nWe used to call ReadBarrierJni unconditionally but add a branch\nto skip calling it if the GC is not currently in the marking phase.\n\nTest: ART_USE_READ_BARRIER\u003dtrue make test-art-host test-art-target\nBug: 30437917\nChange-Id: I4f505ebde17c0a67209c7bb51b3f39e37a06373a\n" }, { "commit": "d9c90373d640a5e08072cf469c372e24a8c0fc35", "tree": "35615699aa6c12b21d9c0de7d11ccf0f088ba0d8", "parents": [ "b180b893b5acb5c55251522465f9d20ed45c3b5a" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Sep 14 16:53:55 2016 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Sep 14 19:57:21 2016 +0100" }, "message": "Move ArrayRef to runtime/base\n\nWill be used in upcoming CLs regarding VDEX and VerifierDeps.\n\nTest: m test-art-host\nChange-Id: I68e611a4a52246c2bdf45eab7c61f3212908afd4\n" }, { "commit": "b03d640c78acad1cf1f8fbeb894ac3366aa164be", "tree": "11bcaea60278962806c211ae8520cb3217f929ea", "parents": [ "a1be503a70c5d0038cfbf917a978c108e2e8b4bd" ], "author": { "name": "jessicahandojo", "email": "jessicahandojo@google.com", "time": "Wed Sep 07 12:16:53 2016 -0700" }, "committer": { "name": "jessicahandojo", "email": "jessicahandojo@google.com", "time": "Wed Sep 07 14:47:33 2016 -0700" }, "message": "Adding x86 compiler utils instructions and tests\n\nInstructions added are (repne scasb), (repne movb),\nand (repne cmpsb) for x86.\nInstructions added is (repne scasb) for x86_64.\n\nTest: m -j31 test-art-host-gtest-assembler_x86_test\n m -j31 test-art-host-gtest-assembler_x86_64_test\n\nChange-Id: I137bf5fe1174b1dcc0166f7f2e0cffadbc0ca7f5\n" }, { "commit": "953437bd51059801d92079295f728d0260efca31", "tree": "b52816b5092a143361ea3878ef0e06d311c4a56f", "parents": [ "c67d22ac6db73aaa9540294c86344bf8021495b3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 08:30:46 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 13:20:32 2016 +0100" }, "message": "Revert \"Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\"\n\nFixed the fault handler recognizing the TEST instruction and\nfault address within the lock word. Added tests to 439-npe.\n\nBug: 29966877\nBug: 12687968\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\n\nThis reverts commit ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15.\n\nChange-Id: I8990def5f719c9205bf6e5fdba32027fa82bec50\n" }, { "commit": "ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15", "tree": "8e271269eb0f3e40388311478fe441bfeb47ab47", "parents": [ "ccf06d8f19a37432de4a3b768747090adfbd18ec" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "message": "Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\n\nFault handler does not recognize the instruction\n F6 /0 ib TEST r/m8, imm8\nso we get crashes instead of NPEs.\n\nBug: 29966877\nBug: 12687968\n\nThis reverts commit ccf06d8f19a37432de4a3b768747090adfbd18ec.\n\nChange-Id: Ib7db3b59f44c0d3ed5e24a20b6c6ee596a89d709\n" }, { "commit": "ccf06d8f19a37432de4a3b768747090adfbd18ec", "tree": "fcb3ba46184db6882e695cecf1cfe495417593ae", "parents": [ "cf834d00de838272cf28f2382ffc26fe716aae5c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 12 13:37:55 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 11:41:44 2016 +0100" }, "message": "x86/x86-64: Avoid temporary for read barrier field load.\n\nAdd TEST instructions for memory and immediate. Use the byte\nversion to avoid a temporary in read barrier field load.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\nBug: 29966877\nBug: 12687968\nChange-Id: Ia415d3c2e1ae1ff6dff11d72bbb7d96d5deed6ee\n" }, { "commit": "0b671c0408e98824e1f92b1ee951b210c090fe7a", "tree": "0bc58c031cd899aa856677fe8c9ffa376228806f", "parents": [ "36bf3a2d281892e7906d3eaf9d7455b0656c9a25" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 12:02:34 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 16:00:09 2016 +0100" }, "message": "Add support for Baker read barriers in SystemArrayCopy intrinsics.\n\nBenchmarks (ARM64) score variations on Nexus 5X with CPU\ncores clamped at 960000 Hz (aosp_bullhead-userdebug build):\n- Ritzperf - average (lower is better): -3.03% (slightly better)\n- CaffeineMark - average (higher is better): +1.26% (slightly better)\n- DeltaBlue (lower is better): -10.50% (better)\n- Richards - average (lower is better): -3.36% (slightly better)\n- SciMark2 - average (higher is better): +0.26% (virtually unchanged)\n\nDetails about Ritzperf benchmarks with meaningful variations\n(lower is better):\n- FormulaEvaluationActions.EvaluateAndApplyChanges: -13.26% (better)\n- FormulaEvaluationActions.EvaluateCascadingSums: -10.94% (better)\n- FormulaEvaluationActions.EvaluateComplexFormulas: -15.50% (better)\n- FormulaEvaluationActions.EvaluateFibonacci: -10.41% (better)\n- FormulaEvaluationActions.EvaluateLargeSums: +6.02% (worse)\n\nBoot image code size variation on Nexus 5X\n(aosp_bullhead-userdebug build):\n- total ARM64 framework Oat files size change:\n 107047632 bytes -\u003e 107154128 bytes (+0.10%)\n- total ARM framework Oat files size change:\n 90932028 bytes -\u003e 91009852 bytes (+0.09%)\n\nTest: ART host and target (ARM, ARM64) tests + Nexus 5X boot.\nBug: 29516905\nBug: 29506760\nBug: 12687968\nChange-Id: I85431368d09965687a0301ae2eb3c991f276ce5d\n" }, { "commit": "2b3201a04dd7894dc916bc59e5a52427e4d1a3b2", "tree": "523549575272d006bd4a9d231c183b5e6c577f2c", "parents": [ "dce74be0c49e8a540affc0b5649a9cf8756b809b" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 12 14:26:15 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 12 14:30:44 2016 +0100" }, "message": "Fix duplicate checks in JNI macro assemblers.\n\nInstead of checking one register twice, check the other\nregister passed to the function.\n\nTest: Run ART test suite on host and Nexus 5.\nBug: 30739460\nChange-Id: If868ea14f5c192982488ed065b279a019b5b7cf4\n" }, { "commit": "961ea1286f670a9ac9fc673308a9cf56137acb95", "tree": "e4158b237c7527d18be3e9fbf5bac322df935aee", "parents": [ "33699c9529add1c1ec4bb5dcb0807942709de224" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 11 14:16:57 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 11 14:17:21 2016 +0100" }, "message": "x86/x86-64: Shorter fast-path for read barrier field load.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nBug: 29966877\nBug: 12687968\nChange-Id: I73359495910dacb2cc28f1a21ef9e610bab5a476\n" }, { "commit": "1ace16bfe8727430809f1e83745e13c52f9610cd", "tree": "02f785b32920a10907753b8154f7b2f2232483de", "parents": [ "95a976a3d1842384ed71bcc6e6449de95ec69961" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 05 09:01:50 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 08 11:44:25 2016 -0700" }, "message": "ART: Extract JNI macro assembler for x86-64\n\nExtract the JNI assembler parts from the regular assembler.\n\nTest: m test-art-host\nChange-Id: I291fb76ad9232123b4c1992488ee81fec3c1db47\n" }, { "commit": "3b165bc53c2f063e3a9c644d0edc7bc30c634884", "tree": "a408bcb65e848d76a22fcd0367a96ed2630a50b8", "parents": [ "11a59a48474caa818ddf344575aa6afc51f45590" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 22:07:04 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 05 17:57:26 2016 -0700" }, "message": "ART: Extract macro assembler\n\nExtract macro assembler functionality used by the JNI compiler from\nthe assembler interface. Templatize the new interface so that\ntype safety ensures correct usage.\n\nChange-Id: Idb9f56e5b87e43ee6a7378853d8a9f01abe156b2\nTest: m test-art-host\n" }, { "commit": "542451cc546779f5c67840e105c51205a1b0a8fd", "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a", "parents": [ "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 26 09:02:02 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 18:54:48 2016 -0700" }, "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n" }, { "commit": "3224838dfe9c95330ad963286f2c47e9546d3b5c", "tree": "50d1b8759c61d392ecc159ede7efab94ecbfcde8", "parents": [ "db9fcb30402a2726564905c206fa23ee86e146c3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 19 10:37:24 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 19 18:12:22 2016 +0100" }, "message": "Clean up JNI calling convention callee saves.\n\nPrecalculate callee saves at compile time and return them\nas ArrayRef\u003c\u003e instead of keeping then in a std::vector\u003c\u003e.\n\nChange-Id: I4fd7d2bbf6138dc31b0fe8554eac35b0777ec9ef\n" }, { "commit": "3b62593ba55f6bdb37ca84f64930654ff4f09464", "tree": "8b521397c856259c9049b52d86e40bfd2c84f0f4", "parents": [ "9858f04577d2ca7400660dba9b3abe8b33bab96c" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Fri May 06 10:24:17 2016 +0600" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Fri May 06 17:55:14 2016 +0600" }, "message": "Add cmpb instruction to x86 and x86_64 assembler\n\nChange-Id: I43f41ef2fdf6475238f0987842aefb1c2eb6a36d\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "bb661c0f0cb72d4bbfc2e251f6ded6949a713292", "tree": "4fe7e66f3385b1955934d3ec6f02e00bde6e13b8", "parents": [ "f7cda8088ec57ab1422f85f08df78e217a9f7094" ], "author": { "name": "Bilyan Borisov", "email": "bilyan.borisov@linaro.org", "time": "Mon Apr 04 16:27:32 2016 +0100" }, "committer": { "name": "Bilyan Borisov", "email": "bilyan.borisov@linaro.org", "time": "Fri Apr 22 13:33:30 2016 +0100" }, "message": "Refactor use of __ANDROID__ macro\n\nWe use the __ANDROID__ macro, which is provided by the toolchain, in\nnumerous places. This patch refactors the usage of this by defining a\nnew macro, ART_TARGET_ANDROID, that is being passed during build to\nART_TARGET_CFLAGS in Android.common_build.mk on the same line as\nART_TARGET. The codebase currently assumes that the existence of the\n__ANDROID__ macro implies that we are compiling art for an android\ntarget device. This is because, currently, target builds are compiled\nwith target toolchains that provide the macro, while host toolchains\ndo not. With this change this assumption is still preserved. However,\nin a future patch we will add the ability to compile art for a linux\ntarget, and in that case the ART_TARGET_ANDROID macro won\u0027t be passed\nanymore.\n\nChange-Id: I1f3a811aa735c87087d812da27fc6b08f01bad51\n" }, { "commit": "93205e395f777c1dd81d3f164cf9a4aec4bde45f", "tree": "1d08efd9b7bca9fe23df9ae9489c5dd575d3c6df", "parents": [ "6990775e323cd9164d6cc10955a047b9d9f15f32" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 13 11:59:46 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 13 17:50:16 2016 +0100" }, "message": "Move Assemblers to the Arena.\n\nAnd clean up some APIs to return std::unique_ptr\u003c\u003e instead\nof raw pointers that don\u0027t communicate ownership.\n\nChange-Id: I3017302307a0253d661240750298802fb0d9585e\n" }, { "commit": "abdac47c3c471d034a5b81aec35bf4201ba86a88", "tree": "f55cb2462ed5e8f79871b96ed5ff0bc6f6d52da6", "parents": [ "b9adbf63f880f246d83b3af4ca03aca07711f857" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Feb 12 13:49:03 2016 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Feb 12 14:45:35 2016 -0500" }, "message": "Add X86/X86_64 support for CMOV from memory.\n\nAdd support for the memory form of CMOV. Add tests.\n\nChange-Id: Ib9f5dbd3031c7e235ee3f2afdb7db75eed46277a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "4fda4eb799c95be266f52aaf3461a440ea86b841", "tree": "54a7e56b5633caf2b868f6028010b488eb1923ce", "parents": [ "3c258f4d7a6492af733a9351ba430d876a3e5ccf" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Feb 05 13:34:46 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Feb 08 11:33:50 2016 +0000" }, "message": "Move code related to debug info generation to its own directory.\n\ndebug/dwarf/ contains helper classes which hide the details\nof the DWARF file format. It acts as independent DWARF library.\n\ndebug/ contains ART-specific code which generates ELF debug\nsections (which includes non-DWARF sections like .symtab).\n\nChange-Id: Id351f604e4e64be2ca395a78324ea02e30481497\n" }, { "commit": "3f67e692860d281858485d48a4f1f81b907f1444", "tree": "a14d3bdc1416dc3db74983d34a408a8b48cbce9c", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 15 14:35:12 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 20 20:14:00 2016 -0800" }, "message": "Implemented BitCount as an intrinsic. With unit test.\n\nRationale:\nRecognizing this important operation as an intrinsic has\nvarious advantages:\n(1) having the no-side-effects/no-throw allows for\n much more GVN/LICM/BCE.\n(2) Some architectures, like x86_64, provide direct\n support for this operation.\n\nPerformance improvements on X86_64:\nCheckersEvalBench (32-bit bitboard): 27,210KNS -\u003e 36,798KNS \u003d + 35%\nReversiEvalBench (64-bit bitboard): 52,562KNS -\u003e 89,086KNS \u003d + 69%\n\nChange-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f\n" }, { "commit": "6ce017304099d1df97ffa016ce0efce79c67f344", "tree": "6c8265acb94f17e78371191809fe67d8101c2c4e", "parents": [ "e38e4b467bdcca1bf5f8b80adc66d3064fa9cf45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 30 14:10:13 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 30 14:22:11 2015 +0000" }, "message": "On x64, cmpl can never take a int64 immediate.\n\nFix a wrong type widening in x64 code generator and add\nCHECKs in the assembler.\n\nChange-Id: Id35f5d47c6cf78ed07e73ab783db09712d3c437f\n" }, { "commit": "9c86b485bc6169eadf846dd5f7cdf0958fe1eb23", "tree": "83196e6888b6fca881bfb63bb0e007453a2821ed", "parents": [ "df3456007702b0dea01ffd1adfa74244857712af" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Sep 18 13:36:07 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Oct 14 08:50:07 2015 -0400" }, "message": "X86_64 jump tables for PackedSwitch\n\nImplement PackedSwitch using a jump table of offsets to blocks.\n\nBug: 24092914\nBug: 21119474\nChange-Id: I83430086c03ef728d30d79b4022607e9245ef98f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "7bfd7ee880785ef383f6434eb4eb35fcaac5ad5a", "tree": "42b5d6ea600edac939677ee8e021d91ac12da1c0", "parents": [ "819a9c5638b6d6b579c89fe36df96acc1f378182", "46fe0650be6a69f63b54c0967194350c6a145557" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Sep 18 13:51:30 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Sep 18 13:51:30 2015 +0000" }, "message": "Merge \"Fix x64\u0027s cmpw.\"" }, { "commit": "46fe0650be6a69f63b54c0967194350c6a145557", "tree": "951c08c8993ad0da72dd96a651617a00a00d102e", "parents": [ "46aa836b632b5f01e8b4c8e5d8eed2199e8f35d0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Sep 18 14:36:49 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Sep 18 14:47:38 2015 +0100" }, "message": "Fix x64\u0027s cmpw.\n\nChange-Id: If700f2994990864c8b34aa52eb7a767153a1f917\n" }, { "commit": "85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d", "tree": "c916b01b1608558a7d8c9d100274c4c6b6706386", "parents": [ "6766eae2d91e894b4ceab9f29cc983900e7bc0c7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 09 13:15:38 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 17 14:41:52 2015 -0700" }, "message": "ART: Refactor intrinsics slow-paths\n\nRefactor slow paths so that there is a default implementation for\ncommon cases (only arm64 with vixl is special). Write a generic\nintrinsic slow-path that can be reused for the specific architectures.\nMove helper functions into CodeGenerator so that they are accessible.\n\nChange-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550\n" }, { "commit": "bcee092d7b0cbb7181d428115ad98d25ce844061", "tree": "dab00e7f7dc19b002948020a8c2cbde665203c0e", "parents": [ "b505997b2176bd29a108cb6c33d06d4ef29ba001" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "message": "Add X86 bsf and rotate instructions\n\nThese are for use in new intrinsics. Bsf (Bit Scan Forward) is used in\n{Long,Integer}NumberOfTrailingZeros and the rotates are used in\n{Long,Integer}Rotate{Left,Right}.\n\nChange-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "73f455ecb76d063846a82735eb80596ceee8cee3", "tree": "8cbf4d0b94a2d75980481b4542c021da4477373b", "parents": [ "9dc601eb65da0cd5f53172699dacd6e5dd38ab44" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 21 09:30:05 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Aug 26 11:18:40 2015 -0400" }, "message": "X86: Assembler support for near labels\n\nThe optimizing compiler uses 32 bit relative jumps for all forward\njumps, just in case the offset is too large to fit in one byte. Some of\nthe generated code knows that the jumps will in fact fit.\n\nAdd a \u0027NearLabel\u0027 class to the x86 and x86_64 assemblers. This will be\nused to generate known short forward branches.\n\nAdd jecxz/jrcxz instructions, which only handle a short offset. They\nwill be used for intrinsics.\n\nAdd tests for the new instructions and NearLabel.\n\nChange-Id: I11177f36394d35d63b32364b0e6289ee6d97de46\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "8ae3ffb29489a127f2a6242c33845dac8d50e508", "tree": "cb5cc72e4a699a8ef6b044d530539c13b02604b7", "parents": [ "f67ab129d868b8355a8403a9627f96ac1e41a796" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Aug 12 21:16:41 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 12:58:40 2015 -0400" }, "message": "Add \u0027bsr\u0027 instruction to x86 and x86_64\n\nAdd support for \u0027bsr\u0027 instruction. Add tests.\n\nChange-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b9c4bbee9364a9351376fd1fec9604e7c84778d8", "tree": "2e0fb139b709cb0bb10f4a15067c9b302eeb0dce", "parents": [ "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jul 01 14:26:52 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 11:07:57 2015 -0400" }, "message": "Add rep movsw to x86 and x86_64 instructions.\n\nAdd \u0027REP MOVSW\u0027 as a supported instruction for x86 32 and 64 bit.\n\nAdded tests.\n\nChange-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "cfa410b0ea561318f74a76c5323f0f6cd8eaaa50", "tree": "80d989b8b26e3fd1afc232c5ecb9a0919823d15b", "parents": [ "1a5625be743a4a84329930ac1c7e96425e24ca8d" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon May 25 16:02:44 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Aug 11 10:32:47 2015 -0400" }, "message": "[optimizing] More x86_64 code improvements\n\nUse the constant area some more, use 32-bit immediates in movq\ninstructions when possible, and other small tweaks.\n\nRemove the commented out code for Math.Abs(float/double) as it would\nfail for baseline compiler due to the output being the same as the\ninput.\n\nChange-Id: Ifa39f1865b94cec2e1c0a99af3066a645e9d3618\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "3fd0e6a86430bf060c7eb391c1378394c4a2c574", "tree": "ea513f925b6130fca92872c54e938d93338443b2", "parents": [ "743e9625bd4b9bddc8752170e647660986c53f08" ], "author": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Mon Aug 03 20:14:29 2015 -0700" }, "committer": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Mon Aug 03 20:14:29 2015 -0700" }, "message": "Added repe_cmpsq instruction to x86_64 assembler\n\nChange-Id: I9085694fd3313581b2775a8267ccda58fec19a1a\n" }, { "commit": "743e9625bd4b9bddc8752170e647660986c53f08", "tree": "afd02ad71706cef14ec9ff0235f8e3f85ec6342d", "parents": [ "e238414eee3ec933a4ceb1894666c9ef331ace0c", "7a08fb53bd13c74dec92256bef22a37250db1373" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Aug 03 17:48:11 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 03 17:48:11 2015 +0000" }, "message": "Merge \"Optimizing: Add Non Temporal Move support for x86\"" }, { "commit": "e238414eee3ec933a4ceb1894666c9ef331ace0c", "tree": "6a971c3a336c4c76bd622685a355e01da3ce4919", "parents": [ "bc576cfd9c85a285f15b8c33a2cc7f947d999f49", "4a2aa4af61e653a89f88d776dcdc55f6c7ca05f2" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 03 14:57:38 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 03 14:57:38 2015 +0000" }, "message": "Merge \"Optimizing: Use more X86 3 operand multiplies\"" }, { "commit": "970abfb65530b700f3a0cc8b90b131df5420cec3", "tree": "674f52f6f573bab2e1529590facb64ab61af30af", "parents": [ "8433bb8a3120d064de97a692d98341d9bc29a985" ], "author": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Fri Jul 31 10:31:14 2015 -0700" }, "committer": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Fri Jul 31 10:31:14 2015 -0700" }, "message": "Added repe_cmpsl instruction to x86, x86_64 assemblers\n\nSupport for this instruction has already been added to the disassembler\nin commit 124b392d.\n\nChange-Id: I6e8401a7b814618758427f5cc6b4992e265f937c\n" }, { "commit": "c60e1b755c5632dfeb04c333489ede52ee5c945f", "tree": "9582a0ffc99e4ad11dcd5d95dd97b09bc6acc5bf", "parents": [ "7b926cdacc2b67241bc9cb5f2d4b04b13ca79d0e" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 30 08:57:50 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 30 08:57:50 2015 -0700" }, "message": "ART: Use __ANDROID__ instead of HAVE_ANDROID_OS\n\nUse the proper define.\n\nChange-Id: I71e291ac25f5d5f0187ac9b6ef2d6872f19e6085\n" }, { "commit": "7a08fb53bd13c74dec92256bef22a37250db1373", "tree": "4a875755b0a768eb7f478c59e477bcc78ce62d49", "parents": [ "595335100a947693b9af5fb6c0b5b3c1f0b91788" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jul 15 14:09:35 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jul 30 09:48:54 2015 -0400" }, "message": "Optimizing: Add Non Temporal Move support for x86\n\nAdd moves that don\u0027t pollute the data cache. These can be used for\nassigning large data structures.\n\nChange-Id: I14d91ba6264f5ce2f128033d65d59b2536426643\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "4a2aa4af61e653a89f88d776dcdc55f6c7ca05f2", "tree": "c2821abad2247064094e9b2116c7ea727b63384c", "parents": [ "595335100a947693b9af5fb6c0b5b3c1f0b91788" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Jul 27 16:13:10 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jul 28 15:54:05 2015 -0400" }, "message": "Optimizing: Use more X86 3 operand multiplies\n\nThe X86_64 code generator generated 3 operand multiplies for long\nmultiplication only. Add support for 3 operand multiplication for\nint as well for both X86 and X86_64.\n\nNote that the RHS operand must be a 32 bit constant, and that it is\npossible for the constant to end up in a register (!) due to a previous\nuse by another instruction. Handle this case by checking the operand,\notherwise the first input might not be the same as the output, due to\nthe use of Any().\n\nAlso allow stack operands for multiplication.\n\nChange-Id: I8f3d14cc01e9a91210f418258aa18065ee87979d\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "71311f868e2579fa5d40b24e620198734119d1a0", "tree": "e206f2b7580ce1a3ddd354a5e2d4ea6caf670d49", "parents": [ "8ae3588989ea99d8c60f885e3d830e6e0c87ff5f" ], "author": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Mon Jul 27 11:34:13 2015 -0700" }, "committer": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Mon Jul 27 13:48:44 2015 -0700" }, "message": "Added repe_cmpsw instruction to x86, x86_64 assemblers\n\nChange-Id: I7634959eebb64d607f47497db320d5c2afdef16b\n" }, { "commit": "c470193cfc522fc818eb2eaab896aef9caf0c75a", "tree": "9887d434f8d9e33c41b98ca406e7c060c68c9016", "parents": [ "c87c8939ea1bcfbddb954478d527cf1138f4f343" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 10 13:18:51 2015 -0400" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 07 16:49:53 2015 +0100" }, "message": "Fuse long and FP compare \u0026 condition on x86/x86-64 in Optimizing.\n\nThis is a preliminary implementation of fusing long/float/double\ncompares with conditions to avoid materializing the result from the\ncompare and condition.\n\nThe information from a HCompare is transferred to the HCondition if it\nis legal. There must be only a single use of the HCompare, the HCompare\nand HCondition must be in the same block, the HCondition must not need\nmaterialization.\n\nAdded GetOppositeCondition() to HCondition to return the flipped\ncondition.\n\nBug: 21120453\nChange-Id: I1f1db206e6dc336270cd71070ed3232dedc754d6\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "4d02711ea578dbb789abb30cbaf12f9926e13d81", "tree": "29c802afff6e73c06021c44e6b2ec9d8340c75e9", "parents": [ "312f1bfcfd8f655e635c941dda147377d8bff814" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 01 15:41:14 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 01 16:31:41 2015 +0100" }, "message": "Implement heap poisoning in ART\u0027s Optimizing compiler.\n\n- Instrument ARM, ARM64, x86 and x86-64 code generators.\n- Note: To turn heap poisoning on in Optimizing, set the\n environment variable `ART_HEAP_POISONING\u0027 to \"true\"\n before compiling ART.\n\nBug: 12687968\nChange-Id: Ib3120b38cf805a8a50207a314b9ccc90c8d93740\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "80afd02024d20e60b197d3adfbb43cc303cf29e0", "tree": "ef054c7b4f2a739f7cf063e0bc4c501c2c7e41b5", "parents": [ "559b178e34c5d92e7932f92e5d8a981ac334606f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 19 18:08:00 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 26 15:59:02 2015 +0100" }, "message": "ART: Clean up arm64 kNumberOfXRegisters usage.\n\nAvoid undefined behavior for arm64 stemming from 1u \u003c\u003c 32 in\nloops with upper bound kNumberOfXRegisters.\n\nCreate iterators for enumerating bits in an integer either\nfrom high to low or from low to high and use them for\n\u003carch\u003eContext::FillCalleeSaves() on all architectures.\n\nRefactor runtime/utils.{h,cc} by moving all bit-fiddling\nfunctions to runtime/base/bit_utils.{h,cc} (together with\nthe new bit iterators) and all time-related functions to\nruntime/base/time_utils.{h,cc}. Improve test coverage and\nfix some corner cases for the bit-fiddling functions.\n\nBug: 13925192\nChange-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7\n" }, { "commit": "21030dd59b1e350f6f43de39e3c4ce0886ff539c", "tree": "b2123ddf1fb1535f750560507e3a186df99dac62", "parents": [ "775b7b888a13315b8b7722564c2824baabb98221" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu May 07 14:46:15 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 11 10:40:05 2015 -0700" }, "message": "ART: x86 indexOf intrinsics for the optimizing compiler\n\nAdd intrinsics implementations for indexOf in the optimizing\ncompiler. These are mostly ported from Quick. Add instruction\nsupport to assemblers where necessary.\n\nChange-Id: Ife90ed0245532a5c436a26fe84715dc357f353c8\n" }, { "commit": "2cebb24bfc3247d3e9be138a3350106737455918", "tree": "d04d27d21b3c7733d784e303f01f873bb99e7770", "parents": [ "1f02f1a7b3073b8fef07770a67fbf94afad317f0" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Apr 21 16:50:40 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 12:44:27 2015 -0700" }, "message": "Replace NULL with nullptr\n\nAlso fixed some lines that were too long, and a few other minor\ndetails.\n\nChange-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb\n" }, { "commit": "7fd8b59ab9fcd896a95883ce7be781d74e849d60", "tree": "80b8d9f3b56159e75100dcf570b19246d8d548a7", "parents": [ "f456ce1d602044e96deef30297b16bfb44f6663a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 22 10:46:07 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 22 11:16:51 2015 -0400" }, "message": "Fix X86_64 assembler REX instructions\n\nA couple of instructions don\u0027t pass the \u0027Address\u0027 to EmitRex64. This\nwill cause the incorrect register number to be assembled if the register\nis \u003e\u003d 8.\n\nThis may cause bad code to be generated in some cases.\n\nChange-Id: I2907ae8b7629ee95d542e3fab429318994a78938\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "40741f394b2737e503f2c08be0ae9dd490fb106b", "tree": "d5d9e6d51168e36154de408e2b5d77371bd8c86d", "parents": [ "dac1a694e4fd79fd5d5ba95319197a1e42f9f054" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Apr 20 22:10:34 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Apr 21 16:23:15 2015 -0400" }, "message": "[optimizing] Use more X86_64 addressing modes\n\nAllow constant and memory addresses to more X86_64 instructions.\n\nAdd memory formats to X86_64 instructions to match.\n\nFix a bug in cmpq(CpuRegister, const Address\u0026).\n\nAllow mov \u003caddr\u003e,immediate (instruction 0xC7) to be a valid faulting\ninstruction.\n\nChange-Id: I5b8a409444426633920cd08e09f687a7afc88a39\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "0a18601f141d864a26d4b74ff5613e69ae411483", "tree": "f8f716fe135199e620c552244a867a8c2a6f7be9", "parents": [ "9134a1a405d471b0dfbf299ab0d4c2d629778632" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 13 17:00:20 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 13 17:00:20 2015 +0100" }, "message": "Exercise the x86 and x86-64 FILD and FISTP instructions.\n\n- Ensure the double- and quadword x87 (FPU) instructions for\n integer loading (resp. fildl and fildll) are properly\n generated by the x86 and x86-64 generators (resp.\n X86Assembler::filds/X86_64Assembler::filds and\n X86Assembler::fildl/X86_64Assembler::fildl).\n- Ensure the double- and quadword x87 (FPU) instructions for\n integer storing \u0026 popping (resp. filstpl and fistpll) are\n properly generated by the x86 and x86-64 generators (resp.\n X86Assembler::fistps/X86_64Assembler::fistps and\n X86Assembler::fistpl/X86_64Assembler::fistpl).\n\nThese instructions can be used in the implementation of the\nlong-to-float and long-to-double Dex type conversions.\n\nChange-Id: Iade52a9aee326d189d77d3dbd352a2b5dab52e46\n" }, { "commit": "e4e88d7b37c977b4c755485174a54c04aa3de951", "tree": "b25d5be5b8e7320d05f42da549c11cc82d7dbc51", "parents": [ "6cfece6336c86017694758bbc0dc68b62c02de86", "386ce406f150645158d6067c4e0a36565aefc44f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 13 12:53:56 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 13 12:53:57 2015 +0000" }, "message": "Merge \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"" }, { "commit": "386ce406f150645158d6067c4e0a36565aefc44f", "tree": "e350441be38017d6e7555d9e13ca8b975d61451d", "parents": [ "2d45b4df3838d9c0e5a213305ccd1d7009e01437" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 13 12:53:37 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 13 12:53:37 2015 +0000" }, "message": "Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\n\nTest fails on arm.\n\nThis reverts commit 2d45b4df3838d9c0e5a213305ccd1d7009e01437.\n\nChange-Id: Id2864917b52f7ffba459680303a2d15b34f16a4e\n" }, { "commit": "6cfece6336c86017694758bbc0dc68b62c02de86", "tree": "c0cc90f4167aed365c0ebfddd99fec31c473efc2", "parents": [ "095d209342420563becfec6676b46a6c6b839107", "2d45b4df3838d9c0e5a213305ccd1d7009e01437" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 13 11:33:08 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 13 11:33:09 2015 +0000" }, "message": "Merge \"Optimizing: Fix long-to-fp conversion on x86.\"" }, { "commit": "2d45b4df3838d9c0e5a213305ccd1d7009e01437", "tree": "b3893899a540ba9f4c8cd70e69536d0239a9d3ef", "parents": [ "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Tue Apr 07 17:04:50 2015 +0600" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 13 11:30:02 2015 +0000" }, "message": "Optimizing: Fix long-to-fp conversion on x86.\n\nlong-to-fp conversion implemented using SSE loses the precision.\nThe test is included. CL uses FPU to provide the correct result.\n\nChange-Id: I8eaf3c46819a8cb52642a7e7d7c4e3e0edbc88db\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "39dcf55a56da746e04f477f89e7b00ba1de03880", "tree": "97bbd68fa538cf76ac26cfeb7a101b5ceb330028", "parents": [ "fcfea6324b2913621d5cb642d4315f22c4901368" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Apr 09 20:42:42 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 10 08:50:40 2015 -0400" }, "message": "[optimizing] Address x86_64 RIP patch comments\n\nNicolas had some comments after the patch\nhttps://android-review.googlesource.com/#/c/144100 had merged. Fix the\nproblems that he found.\n\nChange-Id: I40e8a4273997860db7511dc8f1986281b72bead2\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "467e33616472fe92051c75b65327aad87a639f3f", "tree": "0dbd7a486916b929592cc8f5b3b696fe8aafedcf", "parents": [ "4ab74e8b26b8f860f6c39f04ed0a5830bf9823d4", "f55c3e0825cdfc4c5a27730031177d1a0198ec5a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Apr 09 17:25:02 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 17:25:03 2015 +0000" }, "message": "Merge \"[optimizing] Add RIP support for x86_64\"" }, { "commit": "b33b6502523d67180ce7e8044714d1e85dcabfa9", "tree": "b8196576d7be1bb82efa72aec71e1b5fc2cdb38f", "parents": [ "c2981e84b1a0292cc910a22a8b11f52226987d2a", "dd97393aca1a3ff2abec4dc4f78d7724300971bc" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 16:47:14 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 16:47:16 2015 +0000" }, "message": "Merge \"Implement CFI for JNI.\"" }, { "commit": "c2981e84b1a0292cc910a22a8b11f52226987d2a", "tree": "25d33842eb0ff378c9537d318abf10f5976ecd95", "parents": [ "03fe9c80f514de61d52b65f6972d66b464a3d2fd", "d23840d3ed900c6072d71e6599b3568b68de6b7c" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Apr 09 16:41:55 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 16:41:55 2015 +0000" }, "message": "Merge \"x86_64: Fix the rex prefix for movzxb, movsxb, movb\"" }, { "commit": "f55c3e0825cdfc4c5a27730031177d1a0198ec5a", "tree": "500a596838d0ec2bfb3f84ea3c4d87b35d5ca22f", "parents": [ "96159860fc6c4bf68a51a8a57941971f122685d6" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Mar 26 21:07:46 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Apr 09 10:47:11 2015 -0400" }, "message": "[optimizing] Add RIP support for x86_64\n\nSupport a constant area addressed using RIP on x86_64. Use it for FP\noperations to avoid loading constants into a CPU register and moving\nto a XMM register.\n\nChange-Id: I58421759ef2a8475538876c20e696ec787015a72\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "96159860fc6c4bf68a51a8a57941971f122685d6", "tree": "ef2465ab2d84b9076ab57ad239333910f68abd2b", "parents": [ "0c51da5db821493bcef4617ccab04ea367ecc444", "0f88e87085b7cf6544dadff3f555773966a6853e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 09 12:46:58 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 12:46:59 2015 +0000" }, "message": "Merge \"Speedup div/rem by constants on x86 and x86_64\"" }, { "commit": "0f88e87085b7cf6544dadff3f555773966a6853e", "tree": "ea0ae17c712b995e258f1f749a1b8cd98b1fa34b", "parents": [ "c4bd0e6a7f4839ea99222f06979cc2369cb9bf10" ], "author": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Mon Mar 30 17:55:45 2015 +0100" }, "committer": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Thu Apr 09 12:24:10 2015 +0100" }, "message": "Speedup div/rem by constants on x86 and x86_64\n\nThis is done using the algorithms in Hacker\u0027s Delight chapter 10.\n\nChange-Id: I7bacefe10067569769ed31a1f7834f796fb41119\n" }, { "commit": "d23840d3ed900c6072d71e6599b3568b68de6b7c", "tree": "c21634a4f0150913ab7b18017a1848ad7ca0224c", "parents": [ "fa09d442dc74ade81806fce5f1c256f4ddc13004" ], "author": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Tue Apr 07 16:03:04 2015 -0700" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Wed Apr 08 18:10:26 2015 -0700" }, "message": "x86_64: Fix the rex prefix for movzxb, movsxb, movb\n\nThis patch sets the rex prefix for the source byte register of\nmovzxb, movsxb, and movb that has the destination memory operand,\nwhen the register is SPL, BPL, SIL, DIL.\n\nThis patch adds tests for movzxb and movsxb via Repeatrb(),\nand adds the tertiary and quaternary register views for word and\nbyte registers on x86_64.\nTODO: Support tests with memory operands.\n\nChange-Id: I0c5c727f3dd4a75af039b87f7e57d0741e689038\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "9d0ab6f0a2f08c3fa9a59e0b8742cf366d7d0feb", "tree": "5b05ed14a1aa514a1887dd4268f61209087716e1", "parents": [ "cde8e5da3e774a2494b051043130c0495eca09ef", "58d25fd052e999a24734b0cf856a1563e3d1b2d0" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Apr 08 16:07:41 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 08 16:07:41 2015 +0000" }, "message": "Merge \"[optimizing] Implement more x86/x86_64 intrinsics\"" }, { "commit": "dd97393aca1a3ff2abec4dc4f78d7724300971bc", "tree": "eed7360a80b7543ec7962b47feb7df0d1a8d438e", "parents": [ "1109fb3cacc8bb667979780c2b4b12ce5bb64549" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:29:48 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Apr 08 16:36:27 2015 +0100" }, "message": "Implement CFI for JNI.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I37eb7973f99a6975034cf0e699e138c3a9aba10f\n" }, { "commit": "8c57831b2b07185ee1986b9af68a351e1ca584c3", "tree": "862c57e602dff367ca141d3a86235b48bf47bf17", "parents": [ "caff30245889729f102af87e79705893401251ef" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 19:46:22 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:07:58 2015 +0100" }, "message": "Remove the old CFI infrastructure.\n\nChange-Id: I12a17a8a1c39ffccaa499c328ebac36e4d74dc4e\n" }, { "commit": "58d25fd052e999a24734b0cf856a1563e3d1b2d0", "tree": "b1dbeae13a24e3f7ec325698a3724b5d90df2ef9", "parents": [ "1b8e8cac2c96f6d2af8e7217f997a30e11c098b5" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 03 14:52:31 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Apr 06 23:05:13 2015 -0400" }, "message": "[optimizing] Implement more x86/x86_64 intrinsics\n\nImplement CAS and bit reverse and byte reverse intrinsics that were\nmissing from x86 and x86_64 implementations.\n\nAdd assembler tests and compareAndSwapLong test.\n\nChange-Id: Iabb2ff46036645df0a91f640288ef06090a64ee3\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c", "tree": "01b21964ce0516bda835faa15b260ac290714fe0", "parents": [ "dcff612c3a6e1427749771c4559f198fa480f709" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 22:16:59 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 08:45:38 2015 -0400" }, "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures. Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "3f6c7f61855172d3d9b7a9221baba76136088e7c", "tree": "b61ab89a880ae74f44956425f5c9794d73ef029d", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Mar 13 13:47:53 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Mar 13 14:01:43 2015 -0400" }, "message": "[optimizing] Improve x86, x86_64 code\n\nTweak the generated code to allow more use of constants and other small\nchanges\n- Use test vs. compare to 0\n- EmitMove of 0.0 should use xorps\n- VisitCompare kPrimLong can use constants\n- cmp/add/sub/mul on x86_64 can use constants if in int32_t range\n- long bit operations on x86 examine long constant high/low to optimize\n- Use 3 operand imulq if constant is in int32_t range\n\nChange-Id: I2dd4010fdffa129fe00905b0020590fe95f3f926\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "ab1eb0d1d047e3478ebb891e5259d2f1d1dd78bd", "tree": "a2d211ec81294adab2981d0179c8f04be3e8c8c4", "parents": [ "6e27f82193a8f54cd8ecdc8fb2c4c1adadafbaf4" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Feb 13 19:23:55 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Feb 18 16:50:22 2015 -0800" }, "message": "ART: Templatize IsInt \u0026 IsUint\n\nEnsure that things are used correctly.\n\nChange-Id: I76f082b32dcee28bbfb4c519daa401ac595873b3\n" }, { "commit": "748f140d5f0631780dbeecb033c1416faf78930d", "tree": "aa46aea42df4e02614f2565965cd32ef8a9dfafd", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 27 08:17:54 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 17:40:48 2015 +0000" }, "message": "x64 goodness.\n\n- Use test instead of cmp when comparing against 0.\n- Make it possible to use lea for add.\n- Use xor instead of mov when loading 0.\n\nChange-Id: Ide95c4e2d9b773e952412892f2df6869600c324e\n" }, { "commit": "1cf95287364948689f6a1a320567acd7728e94a3", "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed", "parents": [ "4a50662eeaa0b1a26be66e7584fb765151dabc59" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 10:52:14 2015 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "24f2dfae084b2382c053f5d688fd6bb26cb8a328", "tree": "74cfabf632f13c04729081051e34f68d002c91d4", "parents": [ "93edf73a5fecd526920fbd870068fa592376ac8a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 14 19:51:45 2015 -0500" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 11:00:55 2015 +0000" }, "message": "[optimizing compiler] Implement inline x86 FP \u0027%\u0027\n\nReplace the calls to fmod/fmodf by inline code as is done in the Quick\ncompiler.\n\nRemove the quick fmod/fmodf runtime entries, as they are no longer in\nuse.\n\n64 bit code generator Move() routine needed to be enhanced to handle\nconstants, as Location::Any() allows them to be generated.\n\nChange-Id: I6b6a42f6faeed4b0b3c940453e487daf5b25d184\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f", "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f", "parents": [ "12c03ac7575db242a6f35739bb459e8277115da4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Jan 08 17:35:35 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Jan 16 17:27:03 2015 +0000" }, "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n" }, { "commit": "71fb52fee246b7d511f520febbd73dc7a9bbca79", "tree": "444d91e910433aaf887bbdada28dfaa3160bebc2", "parents": [ "420457e6040184a6e1639a4c84fcc8e237bd8a3d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 29 17:43:08 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 10:21:11 2015 -0800" }, "message": "ART: Optimizing compiler intrinsics\n\nAdd intrinsics infrastructure to the optimizing compiler.\n\nAdd almost all intrinsics supported by Quick to the x86-64 backend.\nFurther intrinsics require more assembler support.\n\nChange-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807\n" }, { "commit": "369810a98e6394b6dd162f5349e38a1f597b3bc7", "tree": "ec703b9fdfe57f039f833208f879d8c95b813137", "parents": [ "1c1d40ab7fd856eac52e1a3be7ce60da3fc21fb5" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 14 19:53:31 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 07:51:55 2015 -0800" }, "message": "ART: Allow scoped adjustments to log verbosity\n\nAdd ScopedLogSeverity to adjust the logging level.\n\nSuppress warnings by default in gtests. Suppress errors in instances\nwhere errors are expected.\n\nChange-Id: If3ef865813e9505ab60bc90baed63ff11d90afbb\n" }, { "commit": "140c2c7ca3794210a5376f1b942e12d8b7795faf", "tree": "04c3ca15a0acdc62cf71fb76d9802a868be81ac7", "parents": [ "1e862370ff2c3207afd1b2fc6f77f7ca345643b2" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 06 07:47:10 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 06 07:47:10 2015 -0800" }, "message": "ART: Remove unused parts of x86 assemblers\n\nThese functions are neither used nor functional.\n\nChange-Id: Ib6d0761388a45662ad9448ceb2c539c6f0b77f23\n" }, { "commit": "8558375377946aabbbda6ab584e13f754590bd89", "tree": "589087305c44e6378fa7a38838d7be48ab591506", "parents": [ "43a725cde37740f0384f3f73227c54249ba4fe4f", "784cc5c37f382838f89e281758040c6620ccfd01" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 05 09:16:00 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 05 09:16:01 2015 +0000" }, "message": "Merge \"Fix braino in x64 assembler.\"" }, { "commit": "784cc5c37f382838f89e281758040c6620ccfd01", "tree": "d5804e56b8dba7f55f13eda4f63db3b8f9947163", "parents": [ "ca747ea9951188dbc6f5217d49aca34aeadcc2a6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 20:25:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 20:57:37 2014 +0000" }, "message": "Fix braino in x64 assembler.\n\nWe need to compare the low bits, not the register directly.\n\nChange-Id: I0a8f3901bacbc6002f904543bac9a2fbd7972305\n" }, { "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8", "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519", "parents": [ "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n" }, { "commit": "6004796d6c630696127df2494dcd4f30d1367a34", "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97", "parents": [ "407d77f344cfbdbbfb50531c5f0766bc0892e2fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 00:01:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 14:59:50 2014 +0000" }, "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n" }, { "commit": "4c0b61f506644bb6b647be05d02c5fb45b9ceb48", "tree": "26ff4e14af3cae5f9b30f65177be258d8259ecee", "parents": [ "7c8ce29e97fb7873160ab8895d847e9643a1f8f6" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Dec 05 12:06:01 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Dec 05 12:06:01 2014 +0000" }, "message": "Add support for double-to-int \u0026 double-to-long in optimizing.\n\n- Add support for the double-to-int and double-to-long Dex\n instructions in the optimizing compiler.\n- Add S1 to the list of ARM FPU parameter registers so that\n a double value can be passed as parameter during a call\n to the runtime through D0.\n- Have art::x86_64::X86_64Assembler::cvttsd2si work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n double to int and double to long HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ic93b9ec6630c26e940f7966a3346ad3fd5a2ab3a\n" }, { "commit": "624279f3c70f9904cbaf428078981b05d3b324c0", "tree": "a81f8d8facfc28cac479a68a1042edc74c36d25b", "parents": [ "9a64a46e8edfa89402598d8650b8ebb337ba3d52" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "message": "Add support for float-to-long in the optimizing compiler.\n\n- Add support for the float-to-long Dex instruction in the\n optimizing compiler.\n- Add a Dex PC field to art::HTypeConversion to allow the\n x86 and ARM code generators to produce runtime calls.\n- Instruct art::CodeGenerator::RecordPcInfo not to record\n PC information for HTypeConversion instructions.\n- Add S0 to the list of ARM FPU parameter registers.\n- Have art::x86_64::X86_64Assembler::cvttss2si work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n float to long HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I954214f0d537187883f83f7a83a1bb2dd8a21fd4\n" }, { "commit": "6d0e483dd2e0b63e952de060738c10e2abd12ff7", "tree": "b396377926d2645f0df982f0b03c41149632a3de", "parents": [ "7c97e855ceb9b45a1cc738fb144bd3312c4e09a8" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 18:31:21 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 18:36:14 2014 +0000" }, "message": "Add support for long-to-float in the optimizing compiler.\n\n- Add support for the long-to-float Dex instruction in the\n optimizing compiler.\n- Have art::x86_64::X86_64Assembler::cvtsi2ss work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n long to float HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ic983cbeb1ae2051add40bc519a8f00a6196166c9\n" }, { "commit": "d7fa3a7d26105dd112acf955a0c7a880a6027180", "tree": "2230bd8ef1ab17e79b786c906f571222a76e9d67", "parents": [ "a9159b2e6b11ec92a1c20a6f3cfe0072f12bd389", "ddb7df25af45d7cd19ed1138e537973735cc78a5" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Nov 27 13:13:34 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Nov 27 13:13:35 2014 +0000" }, "message": "Merge \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"" }, { "commit": "ddb7df25af45d7cd19ed1138e537973735cc78a5", "tree": "c428e9482c7d9137c0965eed586969ae108b173f", "parents": [ "35ecc8ca8fba713728b8fc60e9e2a275da2028aa" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 25 20:56:51 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Nov 27 12:30:27 2014 +0000" }, "message": "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\n\nAdds:\n- float comparison for arm, x86, x86_64 backends.\n- ucomis{s,d} assembly to x86 and x86_64.\n- vmstat assebmly for thumb2\n- new assembly tests\n\nChange-Id: Ie3e19d0c08b3b875cd0a4be4ee4e9c8a4a076290\n" }, { "commit": "647b9ed41cdb7cf302fd356627a3ba372419b78c", "tree": "f1ca054aa20ae4c489f208982e7a6cba5d5ee21e", "parents": [ "35ecc8ca8fba713728b8fc60e9e2a275da2028aa" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 12:06:00 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 12:06:00 2014 +0000" }, "message": "Add support for long-to-double in the optimizing compiler.\n\n- Add support for the long-to-double Dex instruction in the\n optimizing compiler.\n- Enable requests of temporary FPU (double) registers during\n code generation.\n- Fix art::x86::X86Assembler::LoadLongConstant and extend\n it to int64_t values.\n- Have art::x86_64::X86_64Assembler::cvtsi2sd work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n long to double HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ie73d9e5e25bd2e15f585c371e8fc2dcb83438ccd\n" }, { "commit": "91debbc3da3e3376416e4394155d9f9e355255cb", "tree": "fd2181a2d4b8e7e8d26101a9a87b4f0c34fa990f", "parents": [ "fd861249f31ab360c12dd1ffb131d50f02b0bfc6" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 19:01:09 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 19:01:09 2014 +0000" }, "message": "Revert \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"\n\nFails on arm due to missing vmrs op after vcmp. I revert this instead of pushing the fix because I don\u0027t understand yet why it compiles with run-test but not with dex2oat.\n\nThis reverts commit fd861249f31ab360c12dd1ffb131d50f02b0bfc6.\n\nChange-Id: Idc2d30f6a0f39ddd3596aa18a532ae90f8aaf62f\n" }, { "commit": "fd861249f31ab360c12dd1ffb131d50f02b0bfc6", "tree": "1765db2b26337f8e96616ebfb769c95d7b421ad2", "parents": [ "fef1680241e85532919ecfaf42855d31ddb69361" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 25 20:56:51 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 16:49:23 2014 +0000" }, "message": "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\n\n- adds float comparison for arm, x86, x86_64 backends.\n- adds ucomis{s,d} assembly to x86 and x86_64.\n\nChange-Id: I232d2b6e9ecf373beb5cc63698dd97a658ff9c83\n" }, { "commit": "799f506b8d48bcceef5e6cf50f3f5eb6bcea05e1", "tree": "078cd0518627673566727494b003fa671c027dc8", "parents": [ "cea28ec4b9e94ec942899acf1dbf20f8999b36b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 26 14:45:52 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 26 14:45:52 2014 +0000" }, "message": "Revert \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"\n\nFails on x86_64 and target.\n\nThis reverts commit cea28ec4b9e94ec942899acf1dbf20f8999b36b4.\n\nChange-Id: I30c1d188c7ecfe765f137a307022ede84f15482c\n" }, { "commit": "cea28ec4b9e94ec942899acf1dbf20f8999b36b4", "tree": "893c062f6792688671519989a78065ecc7e79de9", "parents": [ "f0c001465371279355eeb7633b67ffcc6f6738e5" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 25 20:56:51 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 10:59:15 2014 +0000" }, "message": "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\n\n- adds float comparison for arm, x86, x86_64 backends.\n- adds ucomis{s,d} assembly to x86 and x86_64.\n\nChange-Id: Ie91e04bfb402025073054f3803a3a569e4705caa\n" }, { "commit": "9aec02fc5df5518c16f1e5a9b6cb198a192db973", "tree": "fe924b37f395af1bb50f55ee6c87c66b727f00af", "parents": [ "20032e512c003a8f42735c4e1eca19c1472bb95e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 18 23:06:35 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 24 16:06:55 2014 +0000" }, "message": "[optimizing compiler] Add shifts\n\nAdded SHL, SHR, USHR for arm, x86, x86_64.\n\nChange-Id: I971f594e270179457e6958acf1401ff7630df07e\n" }, { "commit": "8366ca0d7ba3b80a2d5be65ba436446cc32440bd", "tree": "b21c1656af3ec5c9f775373c9d78cb832bee2ca9", "parents": [ "8542ff31bfa778a06316511672dc113a3f19ae5b" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Nov 17 12:02:05 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Nov 19 11:53:07 2014 -0800" }, "message": "Fix the last users of TARGET_CPU_SMP.\n\nEveryone else assumes SMP.\n\nChange-Id: I7ff7faef46fbec6c67d6e446812d599e473cba39\n" }, { "commit": "851df20225593b10e698a760ac3cd5243620700b", "tree": "e4414bc2fbad4e73785e3ef336ab2278d85aa496", "parents": [ "3225b83903329ba7745f6785127e09ff040492cf" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Nov 12 14:05:46 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Nov 13 16:31:59 2014 -0800" }, "message": "ART: Multiview assembler_test, fix x86-64 assembler\n\nExpose \"secondary\" names for registers so it is possible to test\n32b views for 64b architectures.\n\nAdd floating-point register testing.\n\nRefactor assembler_test for better code reuse (and simpler adding\nof combination drivers).\n\nFix movss, movsd (MR instead of RM encoding), xchgl, xchgq,\nboth versions of EmitGenericShift.\n\nTighten imull(Reg,Imm), imulq(Reg,Imm), xchgl and xchgq encoding.\n\nClarify cv*** variants with a comment.\n\nAdd tests for movl, addl, imull, imuli, mull, subl, cmpqi, cmpl,\nxorq (regs), xorl, movss, movsd, addss, addsd, subss, subsd, mulss,\nmulsd, divss, divsd, cvtsi2ss, cvtsi2sd, cvtss2si, cvtss2sd, cvtsd2si,\ncvttss2si, cvttsd2si, cvtsd2ss, cvtdq2pd, comiss, comisd, sqrtss,\nsqrtsd, xorps, xorpd, fincstp, fsin, fcos, fptan, xchgl (disabled,\nsee code comment), xchgq, testl, andl, andq, orl, orq, shll, shrl,\nsarl, negq, negl, notq, notl, enter and leave, call, ret, and jmp,\nand make some older ones more exhaustive.\n\nFollow-up TODOs:\n1) Support memory (Address).\n2) Support tertiary and quaternary register views.\n\nBug: 18117217\nChange-Id: I1d583a3bec552e3cc7c315925e1e006f393ab687\n" }, { "commit": "d6fb6cfb6f2d0d9595f55e8cc18d2753be5d9a13", "tree": "2f8192e49c9debeba18e73e28b9c789adf8d2eef", "parents": [ "f97f9fbfdf7f2e23c662f21081fadee6af37809d" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 11 19:07:44 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 12 19:43:32 2014 +0000" }, "message": "[optimizing compiler] Add DIV_LONG\n\n- for backends: arm, x86, x86_64\n- added cqo, idivq, testq assembly for x64_64\n- small cleanups\n\nChange-Id: I762ef37880749038ed25d6014370be9a61795200\n" }, { "commit": "9574c4b5f5ef039d694ac12c97e25ca02eca83c0", "tree": "2ad3cb7ffaf3579b9ca2a7bb0d7d7e99b3c758b6", "parents": [ "59321e0e10ea09694efecf6154704e2743b9bffd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 13:19:37 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 13:55:36 2014 +0000" }, "message": "Implement and/or/xor in optimizing.\n\nChange-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec\n" }, { "commit": "15136cb06f0a0fd5f60a832c33870de53c74696a", "tree": "ce01322ba56b4678f2a0320a3a5a45115511d89e", "parents": [ "9ffeab50f7675ba69c98efdf3815540eafe79a0e", "946e143941d456a4ec666f7f54719c65c5aa3f5d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Nov 12 11:33:41 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 12 11:33:42 2014 +0000" }, "message": "Merge \"Revert \"Revert \"Add support for long-to-int in the optimizing compiler.\"\"\"" }, { "commit": "57a88d4ac205874dc85d22f9f6a9ca3c4c373eeb", "tree": "af321a2f2d4555f56e0ffcbe31cb4e313b8d35c7", "parents": [ "401da919c67ceb8fbcac81596327ecc10b73389b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 10 15:09:21 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 09:18:41 2014 +0000" }, "message": "Implement checkcast for optimizing.\n\n- Ended up not using HTypeCheck because of how\n instanceof and checkcast end up having different logic\n for code generation.\n\n- Fix a x86_64 assembler bug triggered by now enabling\n more methods to be compiled. Difficult to test today\n without b/18117217.\n\nChange-Id: I3022e7ae03befb1d10bea9637ad21fadc430abe0\n" }, { "commit": "946e143941d456a4ec666f7f54719c65c5aa3f5d", "tree": "4535eb320a60043b18735a8496a288f6f8377cb7", "parents": [ "d6425d7bb909b668341d9781c567f35f6d10ea16" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Nov 11 17:35:19 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Nov 11 17:35:19 2014 +0000" }, "message": "Revert \"Revert \"Add support for long-to-int in the optimizing compiler.\"\"\n\nThis reverts commit 3adfd1b4fb20ac2b0217b5d2737bfe30ad90257a.\n\nChange-Id: Iacf0c6492d49267e24f1b727dbf6379b21fd02db\n" }, { "commit": "55dcfb5e0dd626993bb2b7b9f692c1b02b5d955f", "tree": "ee7bce7035220b6a1b630b54dfe743bbfc8941d8", "parents": [ "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Oct 24 18:09:09 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 06 16:40:59 2014 +0000" }, "message": "Add support for not-long on ARM64 in the optimizing compiler.\n\nChange-Id: I3e98ff411ba358d92774def18a12daccdc4f558f\n" }, { "commit": "dff1f2812ecdaea89978c5351f0c70cdabbc0821", "tree": "5305173d341263ad32deb98c0299ee8bad03baa9", "parents": [ "5e5632ff1651adbf95faaf8fb3239a36f9f61124" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Nov 05 14:15:05 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Nov 05 16:51:59 2014 +0000" }, "message": "Support int-to-long conversions in the optimizing compiler.\n\n- Add support for the int-to-float Dex instruction in the\n optimizing compiler.\n- Add a HTypeConversion node type for control-flow graphs.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n int-to-float HTypeConversion nodes.\n- Add a 64-bit \"Move doubleword to quadword with\n sign-extension\" (MOVSXD) instruction to the x86-64\n assembler.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ieb8ec5380f9c411857119c79aa8d0728fd10f780\n" }, { "commit": "277ccbd200ea43590dfc06a93ae184a765327ad0", "tree": "d89712e93da5fb2748989353c9ee071102cf3f33", "parents": [ "ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Nov 03 21:36:10 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Nov 04 18:40:08 2014 -0800" }, "message": "ART: More warnings\n\nEnable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,\nand -Wunused-but-set-parameter for GCC builds.\n\nChange-Id: I81bbdd762213444673c65d85edae594a523836e5\n" }, { "commit": "705664321a5cc1418255172f92d7d7195cf60a7b", "tree": "bdb7a60edff3e13c9bb6658d9ba20d3541a9c50d", "parents": [ "2deace28b16d3161ccd6a85a2c577e83f4b25364" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Oct 24 16:20:17 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 27 17:33:47 2014 +0000" }, "message": "Add long bitwise not instruction in the optimizing compiler.\n\n- Add support for the not-long (long integer one\u0027s\n complement negation) instruction in the optimizing\n compiler.\n- Add a 64-bit NOT instruction (notq) to the x86-64\n assembler.\n- Generate ARM, x86 and x86-64 code for long HNot nodes.\n- Gather not-related tests in test/416-optimizing-arith-not.\n\nChange-Id: I2d5b75e9875664d6032d04f8401b2bbb84506948\n" } ], "next": "b5de00f1c8f53e6552f1778702673c6274a98bb3" }