)]}' { "log": [ { "commit": "82e52ce8364e3e1c644d0d3b3b4f61364bf7089a", "tree": "d26020cbee67645a46838c57747d2ba1533ba5d1", "parents": [ "ebbb1e322d8c89e69424a543faa03402e5b63673" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Mar 26 16:50:57 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Mar 31 15:53:57 2015 +0100" }, "message": "ARM64: Update to VIXL 1.9.\n\nUpdate VIXL\u0027s interface to VIXL 1.9.\n\nChange-Id: Iebae947539cbad65488b7195aaf01de284b71cbb\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "027f0ff64c2512b9a5f1f54f3fea1bec481eb0f5", "tree": "9202535f219d7343b4c26d5c43f0bcb7c31650df", "parents": [ "6cc763c8b8157fb42dd44e1dfb84812546500dc1" ], "author": { "name": "Douglas Leung", "email": "douglas.leung@imgtec.com", "time": "Fri Feb 27 19:05:03 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Mar 20 16:51:56 2015 -0700" }, "message": "ART: Add Mips32r6 backend support\n\nAdd Mips32r6 compiler support.\n\nDon\u0027t use deprecated Mips32r2 instructions if running in Mips32r6\nmode.\n\nChange-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67\n" }, { "commit": "6ea651f0f4c7de4580beb2e887d86802c1ae0738", "tree": "fd97dcbd7301892cb785ca34aee21ad86437c3b3", "parents": [ "0e242b5cad3c0b68b72f28c1e5fd3fdd4c05bfd8" ], "author": { "name": "Maja Gagic", "email": "maja.gagic@imgtec.com", "time": "Tue Feb 24 16:55:04 2015 +0100" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Mar 06 13:05:47 2015 -0800" }, "message": "Initial support for quick compiler on MIPS64r6.\n\nChange-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8\n" }, { "commit": "d737ab33a458537fca6207e9e4e25198a1511113", "tree": "5d365b8def0e9a8a87ff86c5b12559ff74e8f831", "parents": [ "65405378f4fd207dcd7d99916c2397a0da08438f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Mar 06 09:11:12 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Mar 06 10:45:10 2015 +0000" }, "message": "ART: Enable the use of relative addresses in the arm64 disassembler.\n\nAlso, only keep register aliases for the link register \u0027lr\u0027 and the\nthread register \u0027tr\u0027 in the arm64 disassembler. Other aliases are not\nvery important, and this way we don\u0027t have to provide aliases\nspecialised for Quick or Optimizing.\n\nChange-Id: Ie7a04910f0c587710a0cf2648203d7e89eab5d1f\n" }, { "commit": "1cd27903529ee10229fa639dc8438a75517de492", "tree": "c3689e5286876ea6deb967a79869bac5d270551f", "parents": [ "f5c224cca603ef1dba9bb80952613facc22598fa" ], "author": { "name": "Douglas Leung", "email": "douglas.leung@imgtec.com", "time": "Fri Feb 13 16:55:57 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Sat Feb 28 00:11:26 2015 +0000" }, "message": "ART: Fix Mips disassembler for some floating point instructions.\n\nChange-Id: I2b661a8dae4cd924c081df85f570007cf645769c\n" }, { "commit": "a34e760fa5cc3102ce1998f10816d380c37f43aa", "tree": "887177774ce2875a2938acc9be1cac18f74ba6be", "parents": [ "5a7c634406b2acc4917009b43dcc7def2178a79b" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Tue Feb 03 12:03:15 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Tue Feb 03 18:39:12 2015 +0800" }, "message": "ARM/ARM64: Dump thread offset.\n\nDump thread offset in compiler verbose log for arm32/arm64 and\noatdump for arm64.\n\nBefore patch :\n0x4e: ldr lr, [rSELF, #604]\nAfter patch :\n0x4e: ldr lr, [rSELF, #604] ; pTestSuspend\n\nChange-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91\n" }, { "commit": "5d718dcd46a0a3c65b3635449d80947f342b1d2f", "tree": "cd7ab915520775c8ab7ea2563c0b6badc066c494", "parents": [ "e5deafe9cdd81238c3916b04301ea884c93f46b5", "031b00dc87cca699f02ce4206a9ecd99d59090dd" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Feb 02 15:57:09 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Feb 02 15:57:10 2015 +0000" }, "message": "Merge \"ART: Fix x86 disassembler\"" }, { "commit": "31fb26054349db03b3f1627fe975ed099ade69dd", "tree": "1584fbca9d5099a25ca857531b846f5b05b61de9", "parents": [ "28acb6feb50951645c37c077bd3897ea760ca322" ], "author": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Tue Sep 30 22:10:10 2014 -0700" }, "committer": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Fri Jan 30 08:57:51 2015 -0800" }, "message": "Add options for building/testing with coverage.\n\n acov --clean\n mm -B NATIVE_COVERAGE\u003dtrue ART_COVERAGE\u003dtrue test-art-host\n acov --host\n\n-B is needed because you need to be sure you rebuild *all* of ART with\ncoverage.\n\nChange-Id: Ib94ef610bd1b44dc45624877710ed733051b7a50\n" }, { "commit": "f36df544d421aa60fc4cf8a5db6356b45f97953b", "tree": "85c2a17e6ccdee567c0aee669a6b949a9eead1a8", "parents": [ "ab7f56d9b9838811cb01773e45999e2cda4aa03a" ], "author": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Thu Jan 29 13:28:13 2015 -0800" }, "committer": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Thu Jan 29 13:28:13 2015 -0800" }, "message": "Remove libcxx.mk cruft.\n\nThis is on by default now. No need to leave it in the makefiles.\n\nChange-Id: I20eab7426da4bbbf8b70ffc5b9af7b97487d885d\n" }, { "commit": "031b00dc87cca699f02ce4206a9ecd99d59090dd", "tree": "931769ccc85050469f5e5cb502021d8d35d5ae30", "parents": [ "94fc0e7be35ab1dd42c6336071ea53dfc565faee" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jan 26 19:30:23 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 27 08:44:15 2015 -0800" }, "message": "ART: Fix x86 disassembler\n\nIndex 4 in SIB is valid when given Rex.x, where it denotes r12 and\nnot the invalid rsp.\n\nBug: 19149560\nChange-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850\n" }, { "commit": "57b34294758e9c00993913ebe43c7ee4698a5cc6", "tree": "981821619027686f83fbe00445299b0522f1df05", "parents": [ "4945bfef00ac446d9c5458e55500229d463ab4c3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 14 15:45:59 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 11:32:48 2015 -0800" }, "message": "ART: Allow to compile interpret-only mips64 files\n\nInclude enough infrastructure to allow cross-compiling for mips64,\ninterpret-only. This includes the instruction-set-features, frame\nsize info and utils assembler.\n\nAlso add a disassembler for oatdump, and support in patchoat.\n\nNote: the runtime cannot run mips64, yet.\n\nChange-Id: Id106581fa76b478984741c62a8a03be0f370d992\n" }, { "commit": "8d36591d93920e7b7830c3ffee3759b561f5339e", "tree": "3217249ce513848ed93dcec981d6ed4c13c2fc60", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 13 11:32:32 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 13 11:32:32 2015 -0800" }, "message": "ART: Use jalr instead of jr for Mips\n\nUse the jalr instruction instead of jr in stubs and compiled code.\n\nChange-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b\n" }, { "commit": "55d7c18a1d76eea6d038205ccb9f2d385247f6ac", "tree": "58d55810040aaadad98717c12cae6505cf92dede", "parents": [ "3d5872eb090a04a9444b5621d381eec3846f47a3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 05 15:17:01 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 06 10:59:56 2015 +0000" }, "message": "Improve Thumb disassembler for LDR/STR/PUSH/POP/BKPT.\n\nDisassemble 16-bit Thumb PUSH, POP, BKPT.\n\nClean up 32-bit load/store to handle all cases (including\npreviously unrecognized indexed load/store) in one place;\nthis also fixes LDRSH erroneously disassembled as LDRSB.\n\nRecognize more UNDEFINED instructions and other minor\ncleanup.\n\nChange-Id: Ifdd177745b70e3f774cc0469deb81191b035f51b\n" }, { "commit": "6a0b920512b72542b3f1a3d232fba7ded45ea455", "tree": "9fb25c9217e0a0c671faf507e4990b3205bbeade", "parents": [ "f610c0597e001cb1043aa4074afe25ae79a800e3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 16 14:54:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 16 14:54:18 2014 +0000" }, "message": "Fix crash in x86 disassembler.\n\nProbably a typo from last refactoring.\n\nChange-Id: I086a87120ca0f0dfddbe803573b0e0f79cc6d945\n" }, { "commit": "8683038c1f59bea790d8c7691e40eed7f6250e4a", "tree": "63f168876ecb6b8416082cbc141da1d478a66988", "parents": [ "29045735a55726235e5c2c5156809cdcac61d4d7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Dec 12 21:41:29 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 15 10:27:32 2014 -0800" }, "message": "ART: Do not inline elf writer debug symbols\n\nUsing Clang, this pushes the frame size of the caller across our\nlimit. Thus forbid inlining. The function is only called once per\ncompile, impact is insignificant.\n\nBug: 18738594\nChange-Id: I19c3f1168a5104ab508a8dbf9f2a8c035cb97e3c\n" }, { "commit": "e5eb7060dbacfd7c768692a8fcc4a6017d0bd1cc", "tree": "059f7f8b927e4e5fdbef2ed1f78c2a31c36699ab", "parents": [ "d1512fed4e43bba77fb21fd1b6322c22ef7c5881" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Dec 12 18:44:19 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 15 08:15:57 2014 -0800" }, "message": "ART: Break up x86 disassembler main function\n\nThe function leads to large stack frames with Clang. Break out\nsome parts and use four char* variables for opcode.\n\nBug: 18733806\nChange-Id: I8bf6da6c763175d7081c4231fa5d3b6809316220\n" }, { "commit": "a262f7707330dccfb50af6345813083182b61043", "tree": "a8ab4e42654f47c9deea517f6c4e2020c62d5724", "parents": [ "3e465bec65067ebfdf662469cf85dd82cd077bdd" ], "author": { "name": "Ningsheng Jian", "email": "ningsheng.jian@arm.com", "time": "Tue Nov 25 16:48:07 2014 +0800" }, "committer": { "name": "Ningsheng Jian", "email": "ningsheng.jian@arm.com", "time": "Thu Dec 11 09:08:22 2014 +0800" }, "message": "ARM: Combine multiply accumulate operations.\n\nTry to combine integer multiply and add(sub) into a MAC operation.\nFor AArch64, also try to combine long type multiply and add(sub).\n\nChange-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e\n" }, { "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa", "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Nov 25 20:05:46 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 12:02:58 2014 +0000" }, "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "834896de1c955c04d781d2bf8c53573f94ce8c3e", "tree": "7152aa7bebe9a82f7b35b3f233aacaf6e3e72ea7", "parents": [ "7b5f98e0c17785ec64eb291856cd08dcd3d19ce1", "a37d925d405be9f589ac282869a997e73414d859" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Nov 19 21:09:12 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 19 21:09:15 2014 +0000" }, "message": "Merge \"Improvements to the ARM64 disassembler.\"" }, { "commit": "847c8db052fcb3c1a945a8206547c409d3eb06fc", "tree": "013b7081bf3805b25970dcd71ee18b79944fcab5", "parents": [ "195c576fbff290d4c313b67ed24ca36f2531acc4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 17 10:22:02 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 17 10:22:02 2014 +0000" }, "message": "Revert \"Arm64: Use the debug version of VIXL for debug builds.\"\n\nThis reverts commit 195c576fbff290d4c313b67ed24ca36f2531acc4.\n\nChange-Id: Id992a43ae346bb4c38a6c47639b02aea838d974a\n" }, { "commit": "195c576fbff290d4c313b67ed24ca36f2531acc4", "tree": "0565c97102cc73fa989b6df822b9f2b3f1022a6c", "parents": [ "ff5298ff1640b730ee62c90ca78fc96b7ee82ec4" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Nov 13 11:14:25 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 14 19:02:47 2014 +0000" }, "message": "Arm64: Use the debug version of VIXL for debug builds.\n\nThis patch builds the debug version of ART against VIXL debug. In this\nway VIXL will assert misuses of the assembler and disassembler.\n\nChange-Id: Ic4654eb20e420f23b40e96a69be452dc50770c1c\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "d582fa4ea62083a7598dded5b82dc2198b3daac7", "tree": "c76704c266ef4687eab425612ddf3fd24f93fe8d", "parents": [ "f20076ff813b8012096ff31af236d59db3c0f4e1" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Nov 05 23:46:43 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Nov 13 16:17:46 2014 -0800" }, "message": "Instruction set features for ARM64, MIPS and X86.\n\nAlso, refactor how feature strings are handled so they are additive or\nsubtractive.\nMake MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler\nrather than #ifdefs that wouldn\u0027t have worked in cross-compilation.\nAdd SIMD features for x86/x86-64 proposed in:\n https://android-review.googlesource.com/#/c/112370/\n\nBug: 18056890\n\nChange-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666\n" }, { "commit": "677c12fe1939cad5795e7c9f4738941508c4d56f", "tree": "362b74f16c2d73d5dd66268a206ee3b4fcbe22b6", "parents": [ "abe07109e4128ea2adc26c0cb4312539bbe2913d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 07 16:58:38 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 07 16:58:38 2014 -0800" }, "message": "Tidy x86 disassembler\n\nChange-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e\n" }, { "commit": "277ccbd200ea43590dfc06a93ae184a765327ad0", "tree": "d89712e93da5fb2748989353c9ee071102cf3f33", "parents": [ "ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Nov 03 21:36:10 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Nov 04 18:40:08 2014 -0800" }, "message": "ART: More warnings\n\nEnable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,\nand -Wunused-but-set-parameter for GCC builds.\n\nChange-Id: I81bbdd762213444673c65d85edae594a523836e5\n" }, { "commit": "872dd8208f00c667af8d9e0fd07fdd0ada56d437", "tree": "2f69282f19c72ef157dad9fdc7b6c6daf8a1bf38", "parents": [ "af62cf99a1a4320157e1074c1e65c5fbb0320349" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 30 11:19:14 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 30 11:19:14 2014 -0700" }, "message": "Tidy and reduce ART library dependencies on the host.\n\nMove to shared rather than static libraries. Avoids capture of all static\nlibraries library dependencies.\n\nChange-Id: I2be96e92dad4ed1842d76b044745f2a2e15372eb\n" }, { "commit": "a37d925d405be9f589ac282869a997e73414d859", "tree": "f48473337f07df6fb9f505651d653ed01b9d2eda", "parents": [ "be29639a910daaa5bdb0c32be1e03477cf12babb" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Oct 27 11:28:14 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Oct 29 09:01:14 2014 +0000" }, "message": "Improvements to the ARM64 disassembler.\n\nThis contains three changes:\n- Use register aliases in the disassembly.\n- When loading from a literal pool, show what is being loaded.\n- Disassemble using absolute addresses on ARM64.\n This ensures that addresses disassembled are coherent with instruction\n location addresses shown.\n\nExamples of disassembled instructions before and after the changes:\n\nBefore:\n movz w17, #0x471f\n ldr d9, pc+736 (addr 0x72690d50)\n\nAfter:\n movz wip1, #0x471f\n ldr d9, pc+736 (addr 0x72690d50) (-745.133)\n\nChange-Id: I72fdc160fac26f74126921834f17a581c26fd5d8" }, { "commit": "2c4257be8191c5eefde744e8965fcefc80a0a97d", "tree": "9db3e1f1c60f2df29638ba3ce9d5d5bb8b26ca2c", "parents": [ "98c271d517bc4d25fc6879b4b8e35ea93885d9e2" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 24 14:20:06 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 24 14:23:42 2014 -0700" }, "message": "Tidy logging code not using UNIMPLEMENTED.\n\nChange-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe\n" }, { "commit": "cf7f19135f0e273f7b0136315633c2abfc715343", "tree": "ffa4d9efd9c45f4b6789acc1f534bb9327052b7e", "parents": [ "aea6888b056be21adf762e066c7f33b8939b8a06" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:06:39 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:21:57 2014 -0700" }, "message": "C++11 related clean-up of DISALLOW_..\n\nMove DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations\nwith no definitions this prompts better warning messages so deal with these\nby correcting the code.\nAdd a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object.\nMake X86 assembly operand types ValueObjects to fix compilation errors.\nTidy the use of iostream and ostream.\nAvoid making cutils a dependency via mutex-inl.h for tests that link against\nlibart. Push tracing dependencies into appropriate files and mutex.cc.\nx86 32-bit host symbols size is increased for libarttest, avoid copying this\nin run-test 115 by using symlinks and remove this test\u0027s higher than normal\nulimit.\nFix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it\nreturns NULL when the heap is under construction by Runtime.\n\nChange-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b\n" }, { "commit": "c7dd295a4e0cc1d15c0c96088e55a85389bade74", "tree": "0c08a2236bc9ba5d9a4dc75d4dd0ed2d76f8f1c6", "parents": [ "94e5af8602150efa95bde35cc9be9891ddf30135" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 21 23:31:19 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 12:06:23 2014 -0700" }, "message": "Tidy up logging.\n\nMove gVerboseMethods to CompilerOptions. Now \"--verbose-methods\u003d\" option to\ndex2oat rather than runtime argument \"-verbose-methods:\".\nMove ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc\nexcept for a forward declaration.\nRemove ConstDumpable as Dump methods are all const (and make this so if not\ncurrently true).\nMake LogSeverity an enum and improve compile time assertions and type checking.\nRemove log_severity.h that\u0027s only used in logging.h.\nWith system headers gone from logging.h, go add to .cc files missing system\nheader includes.\nAlso, make operator new in ValueObject private for compile time instantiation\nchecking.\n\nChange-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641\n" }, { "commit": "6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3", "tree": "f7a20779e4d665f948c5fbcd26dac0071dafb8d4", "parents": [ "2df6840f68dd18d7dd8dbf53f8b6181bbfdc4fc4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 14 17:41:57 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 16 19:27:28 2014 -0700" }, "message": "Make ART compile with GCC -O0 again.\n\nTidy up InstructionSetFeatures so that it has a type hierarchy dependent on\narchitecture.\nAdd to instruction_set_test to warn when InstructionSetFeatures don\u0027t agree\nwith ones from system properties, AT_HWCAP and /proc/cpuinfo.\nClean-up class linker entry point logic to not return entry points but to\ntest whether the passed code is the particular entrypoint. This works around\nimage trampolines that replicate entrypoints.\nBug: 17993736\n\nChange-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23\n" }, { "commit": "fef019c52ed7b131990d51a1e0d4444a3adf9b7b", "tree": "662ba622c502a487f49ab1658567fccf2ca2eb0f", "parents": [ "f8e28f575b1382e984edb2e8c9846a27a1bdea10" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Oct 10 17:14:18 2014 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Oct 13 14:12:33 2014 +0100" }, "message": "ART: ARM64: Fix instruction addresses in the disassembly.\n\nChange-Id: Ic8b6e0d5cd15e029de9bc82e0a4fc2e33d07936c\n" }, { "commit": "fc787ecd91127b2c8458afd94e5148e2ae51a1f5", "tree": "ef48c0f511ee9bf4ed85607cc4d530bace7e6cae", "parents": [ "8fa8c904f7c783204a1dc9438429391d256658da" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 21:56:44 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 22:22:46 2014 -0700" }, "message": "Enable -Wimplicit-fallthrough.\n\nFalling through switch cases on a clang build must now annotate the fallthrough\nwith the FALLTHROUGH_INTENDED macro.\nBug: 17731372\n\nChange-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324\n" }, { "commit": "c8ccf68b805c92674545f63e0341ba47e8d9701c", "tree": "fb360323538cb242ebf7c5c0aca27d3a0bce0abb", "parents": [ "fcabfbe577c0fd40910b565beb681bd4b66f6c5d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 29 20:07:43 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 29 20:13:48 2014 -0700" }, "message": "ART: Fix some -Wpedantic errors\n\nRemove extra semicolons.\n\nDollar signs in C++ identifiers are an extension.\n\nNamed variadic macros are an extension.\n\nBinary literals are a C++14 feature.\n\nEnum re-declarations are not allowed.\n\nOverflow.\n\nChange-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a\n" }, { "commit": "2cbaccb67e22c0b313a9785bfc65bcb4b25d0676", "tree": "daeb766e19880b651fd9c4a719c9a07dd7d4bd0e", "parents": [ "bace0378d720a1d2938ec7f6be17e2814671d20a" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Sun Sep 14 20:34:17 2014 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Tue Sep 16 12:50:08 2014 -0700" }, "message": "Avoid printing absolute addresses in oatdump\n\n- Added printing of OatClass offsets.\n- Added printing of OatMethod offsets.\n- Added bounds checks for code size size, code size, mapping table, gc map, vmap table.\n- Added sanity check of 100k for code size.\n- Added partial disassembly of questionable code.\n- Added --no-disassemble to disable disassembly.\n- Added --no-dump:vmap to disable vmap dumping.\n- Reordered OatMethod info to be in file order.\n\nBug: 15567083\n\n(cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f)\n\nChange-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8\n" }, { "commit": "b3a84e2f308b3ed7d17b8e96fc7adfcac36ebe77", "tree": "381fb72a42defc934f01cddab40a63299c0ba592", "parents": [ "2a09504334a3a3b4c47100197df0827cc6740433" ], "author": { "name": "Lupusoru, Razvan A", "email": "razvan.a.lupusoru@intel.com", "time": "Mon Jul 28 14:11:01 2014 -0700" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Sep 03 10:05:40 2014 -0700" }, "message": "ART: Vectorization opcode implementation fixes\n\nThis patch fixes the implementation of the x86 vectorization opcodes.\n\nChange-Id: I0028d54a9fa6edce791b7e3a053002d076798748\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\nSigned-off-by: Philbert Lin \u003cphilbert.lin@intel.com\u003e\n" }, { "commit": "b5bce7cc9f1130ab4932ba8e6917c362bf871f24", "tree": "45d3b064227213da49d047c3c718e23f33b47cad", "parents": [ "3b6711faf7b0b10eaa6c48ba854160bcecd00166" ], "author": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Fri Jul 25 12:32:18 2014 -0700" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Tue Aug 26 11:38:04 2014 -0700" }, "message": "ART: Add non-temporal store support\n\nAdded non-temporal store support as a hint from the ME.\nAdded the implementation of the memory barrier\nextended instruction that supports non-temporal stores\nby explicitly serializing all previous store-to-memory instructions.\n\nChange-Id: I8205a92083f9725253d8ce893671a133a0b6849d\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "f40f890ae3acd7b3275355ec90e2814bba8d4fd6", "tree": "2c25813aefc9fd579a6527ccb8145fba10f5d768", "parents": [ "6324ca4706de44b75e5b8ba55473766809c4f132" ], "author": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Thu Aug 14 14:10:32 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Aug 14 15:21:12 2014 -0700" }, "message": "Implement inlined shift long for 32bit\n\nAdded support for x86 inlined shift long for 32bit\n\nChange-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\n" }, { "commit": "76ab347dc9b89970da1451568965ee208c728c43", "tree": "9581645023d8ebceb1d9385145648f37a83cebe2", "parents": [ "99c251bbd225dd97d0deece29559a430b12a0b66" ], "author": { "name": "Junmo Park", "email": "junmoz.park@samsung.com", "time": "Mon Aug 11 21:28:16 2014 +0900" }, "committer": { "name": "Junmo Park", "email": "junmoz.park@samsung.com", "time": "Wed Aug 13 08:21:05 2014 +0900" }, "message": "Fix art build script\n\nUse ART_BUILD_HOST_NDEBUG instead of ART_BUILD_NDEBUG.\n\nChange-Id: I0ff590552f47d3354287a155b51936a7aef82f1f\nSigned-off-by: Junmo Park \u003cjunmoz.park@samsung.com\u003e\n" }, { "commit": "ec95f72490de0a7f86c35de3d00b50bb80d036a1", "tree": "d6576fb0ada8810d721f3e989e03e861e4dac03f", "parents": [ "f90283f61d6ca37abf3a9fb8447d05e79caf0160" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 23 12:10:07 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 30 07:41:43 2014 +0000" }, "message": "ART: Correct disassembling of 64bit immediates on x86_64\n\nThe patch fixes an issue with disassembling \u0027movsxd\u0027 and \u0027movabsq\u0027\ninstructions altered with 64bit immediates: not only a REX.W prefix\nmay be prepended to these instructions.\n\nChange-Id: Ida7c7b368327a6b5cae1ff12ec00ceb0769c0a3d\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "3c7bb98698f77af10372cf31824d3bb115d9bf0f", "tree": "1cd4cc18babfbb16ab908f23929fa88d7678f06b", "parents": [ "98cc1e552c2ccbe5d51bc81d49e79119280f5416" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 23 16:04:16 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 28 15:44:28 2014 +0100" }, "message": "Implement array get and array put in optimizing.\n\nAlso fix a couple of assembler/disassembler issues.\n\nChange-Id: I705c8572988c1a9c4df3172b304678529636d5f6\n" }, { "commit": "79bb184ec0a661bf1276eef555dd5e20828bc528", "tree": "ccac7bc93ddca873940467ce8be7472a8b8915f5", "parents": [ "62f28f943e2da2873c7a09096c292f01a21c6478" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Jul 01 18:28:43 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 09 10:59:33 2014 +0000" }, "message": "ART: Correct disassembling of regs from opcodes\n\nRegisters, which are part of opcode might have 1-byte size\nor 2-byte size depending on the instruction and 66h prefix.\nThis patch makes the decoding of such instruction correct.\n\nExamples:\n - \u0027664155\u0027 should be decoded as \u0027push r13w\u0027\n (66h + REX.B)\n\n - \u002741B320\u0027 should be decoded as \u0027mov r11l, 0x20\u0027\n (byte-operand + REX.B)\n\nChange-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "2cfe30bd592cb6ae63bb4c28ccaf4b069d6ab565", "tree": "3eb01d4c9f9a36985f70450822c0bb3f4065db02", "parents": [ "7b68fb3b9b421d4b20c1993704986d637f1cab91", "60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jul 09 07:44:21 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 08 22:56:31 2014 +0000" }, "message": "Merge \"X86 Backend support for vectorized float and byte 16x16 operations\"" }, { "commit": "60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43", "tree": "496acee66205218843ed6bddc300ae3653794e75", "parents": [ "cecec712e1e05aab1fe3469077016320b7bf9583" ], "author": { "name": "Udayan Banerji", "email": "udayan.banerji@intel.com", "time": "Tue Jul 08 19:59:43 2014 -0700" }, "committer": { "name": "Udayan Banerji", "email": "udayan.banerji@intel.com", "time": "Tue Jul 08 19:59:43 2014 -0700" }, "message": "X86 Backend support for vectorized float and byte 16x16 operations\n\nAdd support for reserving vector registers for the duration of vector loop.\nAdd support for 16x16 multiplication, shifts, and add reduce.\n\nChanged the vectorization implementation to be able to use the dataflow\nelements for SSA recreation and fixed a few implementation details.\n\nChange-Id: I2f358f05f574fc4ab299d9497517b9906f234b98\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Olivier Come \u003colivier.come@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\n" }, { "commit": "94f3eb0c757d0a6a145e24ef95ef7d35c091bb01", "tree": "9f9c49f151d8065633d916921071adcb1bb1f087", "parents": [ "6e524ddc060f10a493dc63fa5b6dde0deef22219" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Tue Jun 24 13:23:17 2014 +0700" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Wed Jul 09 12:10:52 2014 +0700" }, "message": "x86_64: Clean-up after cmp-long fix\n\nThe patch adresses the coments from review done by Ian Rogers.\nClean-up of assembler.\n\nChange-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "ae2efea4582df773f80be274bdc754f732b07df3", "tree": "dab448db22bc5c01e0010cd6f78fc8017ff8f89c", "parents": [ "0da09a026fb6c612e659dc782312987b4515f472", "fb0fecffb31398adb6f74f58482f2c4aac95b9bf" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Jul 07 18:18:03 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 07 17:50:18 2014 +0000" }, "message": "Merge \"ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation\"" }, { "commit": "e443a8063518fb1c5229afa3081b9fd1f6d33b16", "tree": "a4e64dea6743e787e77369241ec14f3969c43c0d", "parents": [ "ca8ff32bbb1f034b3b1f25de1fe20a9015bc87ec" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Mon Jun 30 15:44:12 2014 +0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 03 16:23:28 2014 -0700" }, "message": "ART: FF-opcodes are target-specific\n\nSome of the FF-opcodes\u0027 (i.e., push, call, jmp) register names\ndepend on the the target (32-bit vs 64-bit). This patch makes\nsuch opcodes target-specific.\n\nChange-Id: I4fa0b7ee5310e14f4022850ac2160c21be5d1c99\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "5192cbb12856b12620dc346758605baaa1469ced", "tree": "46f8727c0009978e1c15f94ea353a9fc92d2fe42", "parents": [ "7a59a24987beb52877b72b4e3f841e406413bb6d" ], "author": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Tue Jul 01 13:48:17 2014 -0400" }, "committer": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Wed Jul 02 06:40:12 2014 -0400" }, "message": "Load 64 bit constant into GPR by single instruction for 64bit mode\n\nThis patch load 64 bit constant into a register by a single movabsq\ninstruction on 64 bit bit instead of previous mov, shift, add\ninstruction sequences.\n\nChange-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\n" }, { "commit": "d48b8a2bc111d30ebafdd2c661e9c0789f5c66a7", "tree": "86c281284fa1a594e9ed6ee9da349cee8c8a84fb", "parents": [ "6f9dbb8d4aa72c9b24ea45358751123b6e4c7488" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Jun 24 16:40:19 2014 +0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 01 16:15:05 2014 -0700" }, "message": "ART: FPU instructions support in disassembler\n\nThis patch extends the disassembler with new FPU instructions:\n - fstsw\n - fucompp\n - fprem\n\nChange-Id: I9458510bc17f2b3b286edec102552f64be05147e\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "fb0fecffb31398adb6f74f58482f2c4aac95b9bf", "tree": "10ce833ce3912adbfbbb7b2514d483a1ae2b14bb", "parents": [ "e7248f2f1835ed194296d4f989c56251d03b834b" ], "author": { "name": "Olivier Come", "email": "olivier.come@intel.com", "time": "Fri Jun 20 11:46:16 2014 +0200" }, "committer": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Wed Jun 25 11:58:01 2014 -0700" }, "message": "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation\n\nThe patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation\n for X86.\n\nChange-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6\nSigned-off-by: Olivier Come \u003colivier.come@intel.com\u003e\n" }, { "commit": "afd9acc30bdd11cdd12d8209eb994cb371c65e33", "tree": "10ebfa28d992a96422fcf81eb28c98393719e9a6", "parents": [ "ba778fae99ec3b38d4f98262e6b7072bab0e9de4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 17 08:21:54 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 24 16:47:31 2014 -0700" }, "message": "Multilib ART host.\n\nBuild ART for the host as a multilib project with dalvikvm32 and dalvikvm64\nrunning as 32 or 64-bit repsectfully. Note, currently multilib host builds\nare not the default, you make the so by setting BUILD_HOST_64bit\u003d1.\nExtend tests to execute in both 32 and 64-bit modes. By default both 32 and\n64-bit tests are run, add 32 or 64 to the end of a test name to run it in\npurely that flavor.\nGiven the extra spam, modify oat tests to only generate console output when\nthe test fails.\nChange the test harness so that common commands are run when a test should be\nskipped, when it passes or when it fails. Use these commands to generate a\nsummary of passing, skipped and failing tests. Tests will be skipped if they\nare known to be broken or if a test has already failed. Setting the variable\nTEST_ART_KEEP_GOING\u003dtrue will force working tests not to be skipped.\nIn this change all tests running on the optimizing compiler are marked broken\ndue to breakages running them in a multilib environment.\nBreak apart Android.common.mk into its constituent parts, along with other\npieces of reorganization.\n\nStylistic nit, we refer to make rule targets as targets thereby overloading\nthe term target. While consistent with make\u0027s terminology, its confusing with\nthe Android notion of target. I\u0027ve switched to just calling targets rules to\navoid confusion in host tests.\n\nChange-Id: I5190fc3de46800a949fbb06b3f4c258ca89ccde9\n" }, { "commit": "20dfc797dc631bf8d655dcf123f46f13332d3074", "tree": "c1d4e4f919d54f39a6d39d9d769ed5a844afb22b", "parents": [ "cbb0e809c0a4e8a4e8b7f5d3768a1864cfb381bb" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon Jun 16 20:44:29 2014 -0700" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Tue Jun 24 09:05:27 2014 -0700" }, "message": "Add some more instruction support to optimizing compiler.\n\nThis adds a few more DEX instructions to the optimizing compiler\u0027s\nbuilder (constants, moves, if_xx, etc).\n\nAlso:\n* Changes the codegen for IF_XX instructions to use a condition\n rather than comparing a value against 0.\n* Fixes some instructions in the ARM disassembler.\n* Fixes PushList and PopList in the thumb2 assembler.\n* Switches the assembler for the optimizing compiler to thumb2\n rather than ARM.\n\nChange-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f\n" }, { "commit": "a33720c7370d1c9e0d6569d7126bb06f2083c614", "tree": "925f6b2e03efb37148b3d52f24653656f2f84f4f", "parents": [ "b493c2983016a78de498c3a3aef302b1353dca99" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 18 21:02:29 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sat Jun 21 22:28:48 2014 -0700" }, "message": "X86 Dis: Add missing mov byte; Add size suffixes\n\nYet another instruction not disassembled properly.\nAdd \u0027b\u0027, \u0027w\u0027, \u0027q\u0027 to opcodes to diffferentiate between various versions\nand make it more understandable.\n\nChange-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "c5f17732d8144491c642776b6b48c85dfadf4b52", "tree": "811daa488ae5ee5dfd9b3b73bd210bc1506e5ca1", "parents": [ "08654d40cdd256f6a6c8619bf06d04d4c819714a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Jun 05 20:48:42 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 10 23:19:29 2014 -0700" }, "message": "Remove deprecated WITH_HOST_DALVIK.\n\nBug: 13751317\nFix the Mac build:\n - disable x86 selector removal that causes OS/X 10.9 kernel panics,\n - madvise don\u0027t need does zero memory on the Mac, factor into MemMap\n routine,\n - switch to the elf.h in elfutils to avoid Linux kernel dependencies,\n - we can\u0027t rely on exclusive_owner_ being available from other pthread\n libraries so maintain our own when futexes aren\u0027t available (we\n can\u0027t rely on the OS/X 10.8 hack any more),\n - fix symbol naming in assembly code,\n - work around C library differences,\n - disable backtrace in DumpNativeStack to avoid a broken libbacktrace\n dependency,\n - disable main thread signal handling logic,\n - align the stack in stub_test,\n - use $(HOST_SHLIB_SUFFIX) rather than .so in host make file variables.\n\nNot all host tests are passing on the Mac with this change. dex2oat\nworks as does running HelloWorld.\nChange-Id: I5a232aedfb2028524d49daa6397a8e60f3ee40d3\n" }, { "commit": "33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e", "tree": "bf29fe047b99ff3e387c1eff5c2ea2215bdfda16", "parents": [ "6473c0ab5fe81761c34515c5049d8baf8ee1d35e" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jun 06 15:19:45 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sun Jun 08 22:27:11 2014 -0700" }, "message": "Add Move with Sign Extend Double to disassembler\n\nI noticed another missing instruction.\n\nChange-Id: I71170496b014ac2609116eff2aeb13a13e71e263\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "88649c790cb437c130dcb6e428cddeb1ae62601c", "tree": "4952aa31790fd3016bba3c53808a2a38245aab3b", "parents": [ "32640daf36acda331719766956b25661647e2461" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 04 21:20:00 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jun 05 08:29:31 2014 -0400" }, "message": "Fix X86 disassambler printing of XMM, MM registers\n\nPrinting of uint8_t is done as a char, rather than an integer.\n\nChange-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "f3639b2653fe4e55ce6f753b991eeb015116541d", "tree": "724905b5ebee5d32c6079c29e5e4a97a4e6c558c", "parents": [ "fd51b9fa42af1f3024d93b53ac589c52c095d7db", "122113a8a233f824c014a8fe9d90626218c4dcca" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jun 04 15:12:40 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 04 15:12:40 2014 +0000" }, "message": "Merge \"ART: x86_64 disassembler improvements\"" }, { "commit": "5ca4eaace8ba513f97309bbdc2e156de4b1d648a", "tree": "3a392eb39fda9b6f6e46e05e529c85e18296bc49", "parents": [ "fa5fda3ca52678b6fa739aad46e5c6ea08ae301e" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu May 29 02:09:33 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jun 04 08:00:30 2014 -0700" }, "message": "ART: Make LOCAL_CLANG architecture dependent for the target\n\nBe selective for which target we compile with Clang. Currently we\nonly want to compile with Clang for ARM64, which means we need to\nbe careful about ARM, which is the second architecture for that.\n\nBug: 15014252\n\n(cherry picked from commit 9689e3768621130b2536564f4e00fcb6b3d25df4)\n\nChange-Id: I312e1caea08f2f3a20304b27f979d3c7b72b0a04\n" }, { "commit": "122113a8a233f824c014a8fe9d90626218c4dcca", "tree": "ba2b357fe6b2334b83f0da97118ba91fcaee1af6", "parents": [ "57795db7d44bcd6d106481fa192691400b2358c8" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Fri May 30 17:56:23 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jun 04 12:21:28 2014 +0700" }, "message": "ART: x86_64 disassembler improvements\n\nThis patch\n (a) enables full support of 64bit extended regs r8-r15,\n including 8bit r8l-r15l, 16bit r8w-r15w and also\n 32bit r8d-r15d\n (b) fixes an issue with decoding reg from ModRM byte\n (REX.B should be used)\n (c) fixes an issue with decoding regs from SIB byte\n (regs that contain addr are target-specific)\n\nChange-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "67d18be2a5bddbd8ee9ef144b34ccaeba08a1db2", "tree": "77a7d6e731f63ec95005e52261585d1b93324929", "parents": [ "b413cd79c46b7c48ac763cb8152a55a4ed60fe9f" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri May 30 15:05:09 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri May 30 13:04:11 2014 -0700" }, "message": "Support disassembly of 16-bit immediates\n\nChange-Id: I66f5ce93077241204311e52c547599f5287bae04\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "fe94578b63380f464c3abd5c156b7b31d068db6c", "tree": "d5b400472581859591e9f6794fb07b3ba9cb47c0", "parents": [ "8c895b3385ed96a0b040c35222c0338058895d49" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu May 22 09:52:36 2014 -0400" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat May 24 07:33:52 2014 -0700" }, "message": "Implement all vector instructions for X86\n\nAdd X86 code generation for the vector operations. Added support for\nX86 disassembler for the new instructions.\n\nChange-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2a0e954ecf7c60e6ec62d64b9382cc4ee447e224", "tree": "37d22f5d9e221ecd8a68c41d430e7b21fa3f54d1", "parents": [ "299d2a2b200a94daa49c4727fd679f4461c083c7" ], "author": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Wed May 21 14:55:02 2014 -0700" }, "committer": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Wed May 21 19:47:17 2014 -0700" }, "message": "Move art host to libc++\n\nChange-Id: Ia51a4fdfdbae7377130a43c401c2d8d241671d1e\n" }, { "commit": "700a402244a1a423da4f3ba8032459f4b65fa18f", "tree": "4c22fcda04d271bd55a37aff30650214af17a90c", "parents": [ "047c11adcbcbc0bcf210defdfcbada763961ffee" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 16:49:03 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 22:27:39 2014 -0700" }, "message": "Now we have a proper C++ library, use std::unique_ptr.\n\nAlso remove the Android.libcxx.mk and other bits of stlport compatibility\nmechanics.\n\nChange-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61\n" }, { "commit": "ff093b31d75658c3404f9b51ee45760f346f06d9", "tree": "16a11ff5a78862defcc169b0af2901360a57ab6a", "parents": [ "b3016551e5f264264dbb633a1ddf03ac97f9c66c" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 30 19:04:27 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 01 08:31:01 2014 -0700" }, "message": "Fix a few 64-bit compilation of 32-bit code issues.\n\nBug: 13423943\n\nChange-Id: I939389413af0a68c0d95b23cd598b7c42afa4383\n" }, { "commit": "e8861b30ac8b2b1ca49386f9c9218f1d6fedc511", "tree": "70ec1c5dc2b917211b9bf0428f2806694f725744", "parents": [ "3f4dcdf6c99f90a2301304d26ce29dc637b4be7f" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Fri Apr 18 17:06:15 2014 +0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Apr 25 10:42:13 2014 -0700" }, "message": "ART: Enables x86_64 disassembly\n\nThis patch\n (a) cuts a REX prefix from the instruction and\n (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes.\n\nChange-Id: I2674678224ca27746b33d4006ed38d497972309f\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "96a4f29350bf279d48bff70e21e3264cce216683", "tree": "185fd3643ae9503c2506c24b26c9869dd34fbbf3", "parents": [ "ae55e6c0c6a6fa393742a00ac5b7748f9ce45344", "fba52f1b4bf753790c1d98265c4b0fabb54c7536" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Apr 24 06:20:29 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 24 06:20:29 2014 +0000" }, "message": "Merge \"ART: Fixes an issue with REX prefix for instructions with no ModRM byte\"" }, { "commit": "fba52f1b4bf753790c1d98265c4b0fabb54c7536", "tree": "a9feb49c87ae2ec5cde2dd45913840e1f9977ade", "parents": [ "9623c6668962559e818d1e7f05a58dcb96c71fa9" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Apr 15 15:41:47 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Thu Apr 17 13:17:30 2014 +0700" }, "message": "ART: Fixes an issue with REX prefix for instructions with no ModRM byte\n\nThere are instructions (such as push, pop, mov) in the x86 ISA\nthat encode first operands in their opcodes (opcode + reg).\nIn order to enable an extended 64bit registers (R9-R15) a special\nprefix REX.B should be emitted before such instructions.\n\nThis patch fixes the issue when REX.R prefix was emitted before\ninstructions with no MorRM byte. So, the REX-prefix was simply\nignored by CPU for those instructions whose operands are encoded\nin their opcodes.\n\nThis patch makes the jni_compiler_test passed with JNI compiler\nenabled for x86_64 target.\n\nChange-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "bd5ea6a2f7c61c4cd7b66fead1bedd96e938369d", "tree": "1c1dde0d817303e669c413a919c192e2f3463bb0", "parents": [ "5e17616b7386159cef8f2fb6ffe3cbc4fb1373e4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 16 16:34:44 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 16 16:35:44 2014 -0700" }, "message": "Preparation for transition to libc++.\n\nMove the dependency on libc++ to its own makefile so that we can switch in a\nsingle place between libc++ and stlport.\n\nChange-Id: Ie61e7d054dcd049e36d5e7298c27d8a4abe6edf7\n" }, { "commit": "d6ed642458c8820e1beca72f3d7b5f0be4a4b64b", "tree": "1b6e0438f786d6eeb5566e176d71d454a6cdb9e5", "parents": [ "f9487c039efb4112616d438593a2ab02792e0304" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Apr 09 23:36:15 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Apr 09 23:36:15 2014 +0000" }, "message": "Revert \"Revert \"Revert \"Use trampolines for calls to helpers\"\"\"\n\nThis reverts commit f9487c039efb4112616d438593a2ab02792e0304.\n\nChange-Id: Id48a4aae4ecce73db468587967968a3f7618b700\n" }, { "commit": "f9487c039efb4112616d438593a2ab02792e0304", "tree": "95f88645bec774d3e8df170bd0f40e4cd0911a34", "parents": [ "b24b0e2bb128532945b31ea62715776d7751f84d" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Tue Apr 08 23:08:12 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Apr 09 13:18:07 2014 -0700" }, "message": "Revert \"Revert \"Use trampolines for calls to helpers\"\"\n\nThis reverts commit 081f73e888b3c246cf7635db37b7f1105cf1a2ff.\n\nChange-Id: Ibd777f8ce73cf8ed6c4cb81d50bf6437ac28cb61\n\nConflicts:\n\tcompiler/dex/quick/mir_to_lir.h\n" }, { "commit": "081f73e888b3c246cf7635db37b7f1105cf1a2ff", "tree": "3ad0cab1dfa3bca814ab162cb04af125e819e623", "parents": [ "754ddad084ccb610d0cf486f6131bdc69bae5bc6" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon Apr 07 18:58:07 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon Apr 07 18:58:07 2014 +0000" }, "message": "Revert \"Use trampolines for calls to helpers\"\n\nThis reverts commit 754ddad084ccb610d0cf486f6131bdc69bae5bc6.\n\nChange-Id: Icd979adee1d8d781b40a5e75daf3719444cb72e8\n" }, { "commit": "754ddad084ccb610d0cf486f6131bdc69bae5bc6", "tree": "18d8314f3f6760b035c2bcda7760782ad4f0e0bf", "parents": [ "97a332b4476d5a2b4ad0650dacc6bfcff882fc57" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Feb 19 14:05:39 2014 -0800" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Fri Apr 04 16:07:46 2014 -0700" }, "message": "Use trampolines for calls to helpers\n\nThis is an ARM specific optimization to the compiler\nthat uses trampoline islands to make calls to runtime\nhelper functions. The intention is to reduce the size\nof the generated code (by 2 bytes per call) without\naffecting performance.\n\nBy default this is on when generating an OAT file. It is\noff when compiling to memory.\n\nTo switch this off in dex2oat, use the command line option:\n--no-helper-trampolines\n\nEnhances disassembler to print the trampoline entry on the\nBL instruction like this:\n\n0xb6a850c0: f7ffff9e bl -196 (0xb6a85000) ; pTestSuspend\n\nBug: 12607709\nChange-Id: I9202bdb7cf21252ad807bd48701f1f6ce8e3d0fe\n" }, { "commit": "c777e0de83cdffdb2e240d439c5595a4836553e8", "tree": "29089f785817b5ae59b8cc333b6fd0e8261bcd94", "parents": [ "0537c5ea92a4fb60a04024cc2b7247f08a3d9096" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 03 17:59:02 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 03 21:17:30 2014 +0100" }, "message": "Disassemble Thumb2 shifts and more VFP instructions.\n\nDisassemble Thumb2 instructions LSL, LSR, ASR, ROR and VFP\ninstructions VABS, VADD, VSUB, VMOV, VMUL, VNMUL, VDIV.\n\nClean up disassembly of VCMP, VCMPE, VNEG and VSQRT. These\ncould have been erroneously used for other insns (VSQRT for\nVMOV was encountered) and one VSQRT branch was unreachable.\n\nRemove duplicate VMOV opcodes from compiler.\n\nChange-Id: I160a1e3e4b6eabb6a5101ce348ffd49c0573257d\n" }, { "commit": "dd7624d2b9e599d57762d12031b10b89defc9807", "tree": "c972296737f992a84b1552561f823991d28403f0", "parents": [ "8464a64a50190c06e95015a932eda9511fa6473d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 17:43:00 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Apr 01 08:24:16 2014 -0700" }, "message": "Allow mixing of thread offsets between 32 and 64bit architectures.\n\nBegin a more full implementation x86-64 REX prefixes.\nDoesn\u0027t implement 64bit thread offset support for the JNI compiler.\n\nChange-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147\n" }, { "commit": "99ad7230ccaace93bf323dea9790f35fe991a4a2", "tree": "095705c674703953bf4c50f6a30a105420b770b5", "parents": [ "a9e3d2ccfdbf7f4c7b1508bcb2b774037399b1d4" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Feb 25 17:41:08 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Mar 26 16:20:09 2014 -0700" }, "message": "Relaxed memory barriers for x86\n\nX86 provides stronger memory guarantees and thus the memory barriers can be\noptimized. This patch ensures that all memory barriers for x86 are treated\nas scheduling barriers. And in cases where a barrier is needed (StoreLoad case),\nan mfence is used.\n\nChange-Id: I13d02bf3f152083ba9f358052aedb583b0d48640\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "7d180cb41d3104af7c85a5b808bb9f57c264c2a6", "tree": "5834b83ef7395a9ee9c5ceb8f1c4b4f2ae052c91", "parents": [ "027f7fa539514d2a50b448de1de39ac307087483" ], "author": { "name": "Dmitriy Ivanov", "email": "dimitry@google.com", "time": "Tue Mar 25 10:31:04 2014 -0700" }, "committer": { "name": "Dmitriy Ivanov", "email": "dimitry@google.com", "time": "Tue Mar 25 10:31:52 2014 -0700" }, "message": "Fix imm5 and shift_type detection\n\nBug: 13628315\nChange-Id: I8ff044cc18721b7ea50c75c796a2fb63a1e189f9\n" }, { "commit": "38e12034f1ef2b32e98b6e49cb36b7cc37a7f1be", "tree": "9a879d4034bce742c8b5ef0680c2da2d8da5139d", "parents": [ "fb5b21d1d598b6b42e5d5ca1dac4a040832558fb" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:06:14 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:16:04 2014 -0700" }, "message": "x86-64 disassembler support.\n\nChange-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0\n" }, { "commit": "c2687ef3ef95c9888af885ec3fa1516b218906ff", "tree": "79604605fc47c44f5bc6d65f3f32b39e71ea2e61", "parents": [ "b9d50a9829b795932eac4cc50a99b4ce80b0ecb4" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Thu Mar 13 15:12:11 2014 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Thu Mar 13 15:12:11 2014 -0700" }, "message": "Avoid bus error from reading unaligned 64-bit literal\n\nChange-Id: I5932f130e6a8d31e09ef615e8544ff0e1073ede9\n" }, { "commit": "2b9aa967b22f6114f25a8f7c72c58dc476dc35a2", "tree": "6e2061ba046fd6e997564e82c25d571b5751b3fb", "parents": [ "3dfc5c168506b89e345c977355a4eabebfede72a", "e6622be6c353c7178f34adf814c58370a51c5ed7" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Mar 10 18:48:31 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Mar 10 18:48:31 2014 +0000" }, "message": "Merge \"AArch64: Add ARM64 Disassembler\"" }, { "commit": "e6622be6c353c7178f34adf814c58370a51c5ed7", "tree": "2b6ed31cd1d2ed27998538ff0da327d47e930113", "parents": [ "e2d080ca23ee6146bc28c2caa6c856bd5af41043" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Feb 27 15:36:47 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Mon Mar 10 18:27:01 2014 +0000" }, "message": "AArch64: Add ARM64 Disassembler\n\nThis patch adds disassembler support for ARM64 based on VIXL.\n\nChange-Id: Ic7f5e197350809632145d932dbae8f6c16aebd13\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "e19649a91702234f9aa9941d76da447a1e0dcc2a", "tree": "76e8f8c99aaf462f2cb52a049a96819fc9dc7c95", "parents": [ "d57abe5f75e2c82052d7396d6ec6eafc7f3af58a" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Thu Feb 27 13:30:55 2014 +0000" }, "committer": { "name": "Stuart Monteith", "email": "srdmarm@gmail.com", "time": "Mon Mar 10 14:11:54 2014 +0000" }, "message": "ARM: Remove duplicated instructions; add vcvt, vmla, vmls disassembler.\n\nRemove kThumb2VcvtID in the assembler which was duplicated.\nAdd vcvt, vmla, vmls in the disassembler.\n\nChange-Id: I14cc39375c922c9917274d8dcfcb515e888fdf26\n" }, { "commit": "b48b9eb6d181a1f52e2e605cf26a21505f1d46ed", "tree": "117d99c16f201b2f14adfe0922e56b9ff433c133", "parents": [ "3c506f9877b4a106d93169b6bb5610b24a84d61c" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Feb 28 16:20:21 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Feb 28 19:03:57 2014 -0800" }, "message": "Fix clang to compile and run host tests.\n\nDon\u0027t use the computed goto interpreter with clang 3.4 as it causes compilation\nto hang.\nAvoid inclusion of LLVM_(HOST|DEVICE)_BUILD_MK except for with portable as it\nsets clang incompatible cflags.\nMost fixes are self-evident, for the quick dex file method inliner the enums\nwere being used with ostreams, so fix the enums and operator out python script\nto allow this.\nNote this change effects portable but this is untestable as portable was broken\nby ELF file and mc linker changes.\n\nChange-Id: Ia54348f6b1bd3f76d3b71c6e8c5f97626386b903\n" }, { "commit": "4028a6c83a339036864999fdfd2855b012a9f1a7", "tree": "c86f355cb39adc7a14469f0a4e5727623fbda443", "parents": [ "0b2b3dbaa3db62c0af0d2f23f6aa1c539afe7443" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Feb 19 20:06:20 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 20 15:46:42 2014 -0800" }, "message": "Inline x86 String.indexOf\n\nTake advantage of the presence of a constant search char or start index\nto tune the generated code.\n\nChange-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "dc781a13ddb4dabf646bb45d0c53b65cab948e5b", "tree": "b74e4a579747ce12297b5a66f04669f42dfffa6a", "parents": [ "89925e948c49616689eb4959aaf0e4ff1de18161" ], "author": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Tue Feb 04 16:22:03 2014 -0800" }, "committer": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Tue Feb 18 17:22:15 2014 -0800" }, "message": "art: convert makefiles to support multilib build\n\nConvert makefiles to allow for building two architectures at the\nsame time. More changes may be necessary to get the tests to\nbuild.\n\nChange-Id: I02ba11706b7e5b5592d76e43c167bcbf0e665b93\n" }, { "commit": "614c2b4e219631e8c190fd9fd5d4d9cd343434e1", "tree": "8236046426615c78eb6b2f6c2ca29b63d5665d97", "parents": [ "6b3697fec487b355d107b693c965919bf5fff906" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Jan 28 17:05:21 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Feb 11 18:10:33 2014 -0800" }, "message": "Support to generate inline long to FP bytecodes for x86\n\nlong-to-float and long-to-double are now generated inline instead of calling\na helper routine. The conversion is done by using x87.\n\nChange-Id: I196e526afec1be212898baceca8527549c3655b6\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "ef7d42fca18c16fbaf103822ad16f23246e2905d", "tree": "c67eea52a349c2ea7f2c3bdda8e73933c05531a8", "parents": [ "822115a225185d2896607eb08d70ce5c7099adef" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Jan 06 12:55:46 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 06 23:20:27 2014 -0800" }, "message": "Object model changes to support 64bit.\n\nModify mirror objects so that references between them use an ObjectReference\nvalue type rather than an Object* so that functionality to compress larger\nreferences can be captured in the ObjectRefererence implementation.\nObjectReferences are 32bit and all other aspects of object layout remain as\nthey are currently.\n\nExpand fields in objects holding pointers so they can hold 64bit pointers. Its\nexpected the size of these will come down by improving where we hold compiler\nmeta-data.\nStub out x86_64 architecture specific runtime implementation.\nModify OutputStream so that reads and writes are of unsigned quantities.\nMake the use of portable or quick code more explicit.\nTemplatize AtomicInteger to support more than just int32_t as a type.\nAdd missing, and fix issues relating to, missing annotalysis information on the\nmutator lock.\nRefactor and share implementations for array copy between System and uses\nelsewhere in the runtime.\nFix numerous 64bit build issues.\n\nChange-Id: I1a5694c251a42c9eff71084dfdd4b51fff716822\n" }, { "commit": "2c498d1f28e62e81fbdb477ff93ca7454e7493d7", "tree": "94654433a4dae83ab75d432304dcc0358aefeb1c", "parents": [ "1dcff62155e8477eb114c8a86eb1beb0797ffc11" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Jan 29 16:02:57 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Feb 05 22:42:21 2014 -0800" }, "message": "Specializing x86 range argument copying\n\nThe ARM implementation of range argument copying was specialized in some cases.\nFor all other architectures, it would fall back to generating memcpy. This patch\nupdates the x86 implementation so it does not call memcpy and instead generates\nloads and stores, favoring movement of 128-bit chunks.\n\nChange-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "7ea5dafc81b2bba7cabad26130bb75dc8f709803", "tree": "dfd021549d31697d4c142699e38fb8fa00e64c58", "parents": [ "6e65720d99bd3387b72d528a46291f1ed8184ede", "4708dcd68eebf1173aef1097dad8ab13466059aa" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jan 28 00:29:31 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 28 00:29:31 2014 +0000" }, "message": "Merge \"Improve x86 long multiply and shifts\"" }, { "commit": "d3266bcc340d653e178e3ab9d74512c8db122eee", "tree": "1a3cf8b8e828994c57c533157bc1f84e50c24a14", "parents": [ "26a302b2bb07d754b958a4013116946fbbd78c62" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jan 24 12:55:31 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jan 24 14:38:53 2014 -0800" }, "message": "Reduce x86 sequence for GP pair to XMM\n\nAdded support for punpckldq which is useful for interleaving\n32-bit values from two xmm registers.\n\nThis new instruction is now used for transfers from GP pairs\nto XMM in order to reduce path length.\n\nChange-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "4708dcd68eebf1173aef1097dad8ab13466059aa", "tree": "92614e1fe36cccda1d2fd7c662c43482ec8bcc85", "parents": [ "a278ac31a1beeebd093ec64026d27a02fdc28807" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 22 09:05:18 2014 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 24 11:49:06 2014 -0800" }, "message": "Improve x86 long multiply and shifts\n\nGenerate inline code for long shifts by constants and do long\nmultiplication inline. Convert multiplication by a constant to a\nshift when we can. Fix some x86 assembler problems and add the new\ninstructions that were needed (64 bit shifts).\n\nChange-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2bf31e67694da24a19fc1f328285cebb1a4b9964", "tree": "e24b7ec3569ea26e91f1a10179b7d1912f594d7e", "parents": [ "3f5b42f1d31c877abca2571a51dd0a5055a9b94c" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 23 12:13:40 2014 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 24 10:01:41 2014 -0800" }, "message": "Improve x86 long divide\n\nImplement inline division for literal and variable divisors. Use the\ngeneral case for dividing by a literal by using a double length multiply\nby the appropriate constant with fixups. This is the Hacker\u0027s Delight\nalgorithm.\n\nChange-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "0adc680c388913a63666797e907f87c4c6b0b4ea", "tree": "845853afb3b58f7288f02ef8abd43d0026fc6782", "parents": [ "805ec1c7016ed46a27a0054397fcec8ff4bbbe92", "bd288c2c1206bc99fafebfb9120a83f13cf9723b" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jan 08 22:56:31 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 08 22:56:31 2014 +0000" }, "message": "Merge \"Add conditional move support to x86 and allow GenMinMax to use it\"" }, { "commit": "ef6a776af2b4b8607d5f91add0ed0e8497100e31", "tree": "dbff2e90823f07915efab7abc5a3e31182b2f2ae", "parents": [ "8ec304764fdc97ee300175ebed16622eddfb6f1f" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Dec 19 17:58:05 2013 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jan 08 14:09:53 2014 -0800" }, "message": "Inline codegen for long-to-double on ARM.\n\nChange-Id: I4fc443c1b942a2231d680fc2c7a1530c86104584\n" }, { "commit": "bd288c2c1206bc99fafebfb9120a83f13cf9723b", "tree": "a9f154c4338b888de313517e95ae6a7ee22e7f1f", "parents": [ "51f46ad5edd888b58d706569342c1a0f51e6ae15" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Dec 20 17:27:23 2013 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Jan 08 11:28:46 2014 -0800" }, "message": "Add conditional move support to x86 and allow GenMinMax to use it\n\nX86 supports conditional moves which is useful for reducing branchiness.\nThis patch adds support to the x86 backend to generate conditional reg\nto reg operations. Both encoder and decoder support was added for cmov.\n\nThe x86 version of GenMinMax used for generating inlined version Math.min/max\nhas been updated to make use of the conditional move support.\n\nChange-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "b122a4bbed34ab22b4c1541ee25e5cf22f12a926", "tree": "624f16271f4481a8fd5aa2f607385f490dc7b3ae", "parents": [ "e40687d053b89c495b6fbeb7a766b01c9c7e039c" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Nov 19 18:00:50 2013 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Dec 20 08:01:57 2013 -0800" }, "message": "Tidy up memory barriers.\n\nChange-Id: I937ea93e6df1835ecfe2d4bb7d84c24fe7fc097b\n" }, { "commit": "d19b55a05b52b7f7da9f894eba63ed03e2a62283", "tree": "06c50a4d0121eae129e8dc920166e2e3953e3468", "parents": [ "f723f0cdc693f81581c0781fa472b1c85a8b42d6" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 12 09:55:34 2013 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 12 13:05:18 2013 -0800" }, "message": "Disassemble more x86 instructions\n\nBy using oatdump on the core.oat, I found a couple more instructions\nthat didn\u0027t disassemble properly. These included another form of imul\nand some FP instructions used by the JNI code.\n\nNow the only unknown opcodes I could find seem to be literal data at\nthe end of the method.\n\nChange-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "f723f0cdc693f81581c0781fa472b1c85a8b42d6", "tree": "5d7b37796a71156d805340d88c0bd7f0078bd153", "parents": [ "8755359a35a4aa915fe3753633015263c7e97b74" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 11 17:50:58 2013 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 11 17:50:58 2013 -0800" }, "message": "Add missing x86 imul opcode to disassembler\n\nWhen playing with ART, I noticed that an integer multiply didn\u0027t\ndisassemble properly. This patch adds the instruction.\n\nChange-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "70b797d998f2a28e39f7d6ffc8a07c9cbc47da14", "tree": "e5607068be133899ff9111e33327e0c2aa525cd1", "parents": [ "057c74a3a2d50d1247d4e6472763ca6f59060762" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 03 15:25:24 2013 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 03 18:32:29 2013 +0000" }, "message": "Unsafe.compareAndSwapLong() intrinsic for x86.\n\nChange-Id: Idbc5371a62dfdd84485a657d4548990519200205\n" }, { "commit": "3e5af82ae1a2cd69b7b045ac008ac3b394d17f41", "tree": "de4cb3a63320db48bc942de670552167e1d7bea3", "parents": [ "5da3778746375b73e7e77c5f1371f29684674776" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 21 15:01:20 2013 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 26 17:50:59 2013 +0000" }, "message": "Intrinsic Unsafe.CompareAndSwapLong() for ARM.\n\n(cherry picked from cb53fcd79b1a5ce608208ec454b5c19f64aaba37)\n\nChange-Id: Iadd3cc8b4ed390670463b80f8efd579ce6ece226\n" }, { "commit": "2247984899247b1402408d39731ff64048f0e274", "tree": "da948b429b97506a1dc165debb4f8b5a4c0a585d", "parents": [ "ba9ece9c58de90b39c39b29dbdaee54b1654c066" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 19 17:04:50 2013 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 19 17:07:08 2013 +0000" }, "message": "Clean up kOpCmp on ARM.\n\nkThumb2CmnRI8M is now used.\n\nChange-Id: I300299258ed99d86c300dee45c904c360dd44638\n" }, { "commit": "ad435ebd9d011eef66ef77e96b065024220c10ad", "tree": "c6b4fcbe0493ffaafbcc4daf4e38cb915813fbc0", "parents": [ "500793f33b8af8bc7ccf5595a66b4b13bce766bc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 15 15:21:25 2013 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 15 15:21:25 2013 +0000" }, "message": "Fix Thumb2 ldrd/strd disassembly.\n\nChange-Id: Ie75aeab5b970640e90e567621ac45ce1a3a7c377\n" } ], "next": "dd577a3c9849105429fe7afb3559773d59aaafb6" }