)]}'
{
  "log": [
    {
      "commit": "0700b69cb0c81c3590726be7fbe5b98531cec76b",
      "tree": "9699ae3c78a2c7546918ba03aa43b0306d4f48a5",
      "parents": [
        "6194403a984dd814f01e6f7c6b270342d760388d"
      ],
      "author": {
        "name": "Raphael Gault",
        "email": "raphael.gault@linaro.org",
        "time": "Wed Sep 30 08:33:10 2020 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 06 08:58:50 2021 +0000"
      },
      "message": "SVE: Extract Intermediate Address for SVE Vector Memory Operations\n\nThis patch introduces an optimization that extracts and factorizes\nthe \"base + offset\" common part for the address computation when\nperforming an SVE vector memory operation (VecStore/VecLoad).\n\nWith SVE enabled by default:\n\nTest: ./art/test.py --simulate-arm64 --run-test --optimizing \\\n(With the VIXL simulator patch)\n\nTest: ./art/test.py --target --64 --optimizing \\\n(On Arm FVP with SVE - See steps in test/README.arm_fvp.md)\n\nTest: 527-checker-array-access, 655-checker-simd-arm.\n\nChange-Id: Icd49e57d5550d1530445a94e5d49e217a999d06d\n"
    },
    {
      "commit": "2558abeb7acd49b7de357ca43b0c34354c20a3a0",
      "tree": "dad63d4e0153765d2edd155ac2c78473a40b4a77",
      "parents": [
        "60e29745625405654fb968ba2572ebddd8a0211d"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Oct 14 18:01:37 2020 +0100"
      },
      "committer": {
        "name": "Ulyana Trafimovich",
        "email": "skvadrik@google.com",
        "time": "Thu Feb 11 15:44:16 2021 +0000"
      },
      "message": "ARM64: Adjust SIMD checker tests for SVE.\n\nAdds SVE-specific checker line for SIMD tests\nusing isaHasFeature() function.\n\nTest: test-art-target with Neon.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n      with FVP arg:\n      -C SVE.ScalableVectorExtension.veclen\u003d[2,4]\n      (SVE vector [128,256] bits wide)\n\nChange-Id: I8f2134861b47437823797da48a3ffb680bafc544\n"
    },
    {
      "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0",
      "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788",
      "parents": [
        "7113885fcd983b33ee1e350865d21517d6297843"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 27 16:50:47 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu May 11 10:06:04 2017 +0100"
      },
      "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n"
    }
  ]
}