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gerrit.witaqua.org / art / 077188411c692f82b0785597fee030810a2a5841 / compiler / optimizing / nodes_vector.h
  1. 0771884 ART: Introduce predicated vector instructions. by Artem Serov · 6 years ago
  2. d71f1dc Enable support of VecLoad/VecStore in LSE by xueliang.zhong · 8 years ago
  3. 0a51605 Revert "Make compiler/optimizing/ symbols hidden." by Vladimir Marko · 7 years ago
  4. e272715 Make compiler/optimizing/ symbols hidden. by Vladimir Marko · 7 years ago
  5. 3db7068 ART: Refactor for bugprone-argument-comment by Andreas Gampe · 7 years ago
  6. 4e3734a Rename HVecReduce::GetKind() to GetReductionKind(). by Vladimir Marko · 8 years ago
  7. aaac0e3 ART: ARM64: Support DotProd SIMD idiom. by Artem Serov · 8 years ago
  8. bbc6e7e Use 'final' and 'override' specifiers directly in ART. by Roland Levillain · 8 years ago
  9. 9434487 Expand comment for HVecMultiplyAccumulate by Hans Boehm · 8 years ago
  10. f5f56c7 Revert "Emit vector mulitply and accumulate instructions for x86." by Hans Boehm · 8 years ago
  11. 6190888 Emit vector mulitply and accumulate instructions for x86. by Gupta Kumar, Sanjiv · 8 years ago
  12. bd78567 Store HIR type in HInstruction::packed_field_. by Vladimir Marko · 8 years ago
  13. 3f8e02c Bug fix in SIMD result detection. by Aart Bik · 8 years ago
  14. 5a0eb0c Minor DCHECK bug fix. by Aart Bik · 8 years ago
  15. 29aa082 Vectorization of saturation arithmetic. by Aart Bik · 8 years ago
  16. d9e4d73 Fix iCache misses for GetKind on x86,x86_64 by Gupta Kumar, Sanjiv · 8 years ago
  17. 66c158e Clean up signed/unsigned in vectorizer. by Aart Bik · 8 years ago
  18. 89ff8b2 ARM64: Workaround for the callee saved FP registers and SIMD. by Artem Serov · 9 years ago
  19. 2dd7b67 Fixed spilling bug (visible on ARM64): missed SIMD type. by Aart Bik · 8 years ago
  20. cced8ba ART: Introduce individual HInstruction cloning. by Artem Serov · 9 years ago
  21. 4d1a9d4 Improve sign and zero extension analysis. by Aart Bik · 9 years ago
  22. 61b9228 ART: Introduce Uint8 loads in compiled code. by Vladimir Marko · 9 years ago
  23. e764d2e Use ScopedArenaAllocator for register allocation. by Vladimir Marko · 9 years ago
  24. 46b6dbc Try to preserve dex pc better in vector code. by Aart Bik · 9 years ago
  25. d5d2f2c ART: Introduce Uint8 compiler data type. by Vladimir Marko · 9 years ago
  26. 0ebe0d8 ART: Introduce compiler data type. by Vladimir Marko · 9 years ago
  27. dbbac8f Implement Sum-of-Abs-Differences idiom recognition. by Aart Bik · 9 years ago
  28. 5e3afa9 Ensure extract is seen as having scalar result. by Aart Bik · 9 years ago
  29. 0148de4 Basic SIMD reduction support. by Aart Bik · 9 years ago
  30. 982334c Revert "Basic SIMD reduction support." by Nicolas Geoffray · 9 years ago
  31. cfa59b4 Basic SIMD reduction support. by Aart Bik · 9 years ago
  32. a57b4ee Revert "Basic SIMD reduction support." by Aart Bik · 9 years ago
  33. 9879d0e Basic SIMD reduction support. by Aart Bik · 9 years ago
  34. b79f4ac Added GVN related attributes to vector nodes. by Aart Bik · 9 years ago
  35. 9858bf7 Revert "Added GVN related attributes to vector nodes." by Nicolas Geoffray · 9 years ago
  36. a79f0b5 Added GVN related attributes to vector nodes. by Aart Bik · 9 years ago
  37. a1633a7 Merge "Min/max SIMDization support." by Aart Bik · 9 years ago
  38. c8e93c7 Min/max SIMDization support. by Aart Bik · 9 years ago
  39. e1811ed ARM64: Share address computation across SIMD LDRs/STRs. by Artem Serov · 9 years ago
  40. d58bc32 Allow same-length integral type mixing in SIMD. by Aart Bik · 9 years ago
  41. db14fcf Pack booleans in the already existing bit field. by Aart Bik · 9 years ago
  42. 8de5916 Factor vector unary/binary shared code out into superclass. by Aart Bik · 9 years ago
  43. f34dd20 ARM64: Support MultiplyAccumulate for SIMD. by Artem Serov · 9 years ago
  44. f3e61ee Implement halving add idiom (with checker tests). by Aart Bik · 9 years ago
  45. 6daebeb Implemented ABS vectorization. by Aart Bik · 9 years ago
  46. f8f5a16 ART vectorizer. by Aart Bik · 9 years ago