)]}' { "log": [ { "commit": "077188411c692f82b0785597fee030810a2a5841", "tree": "f74ced58d91dcb215601175dc7d29854d46aee0d", "parents": [ "1715efa0b46d57d587237829d1c0695aaca2c344" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Feb 24 18:51:42 2020 +0000" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Tue Jun 09 13:11:45 2020 +0000" }, "message": "ART: Introduce predicated vector instructions.\n\nThis CL introduces a minimal changes to the IR to support\nautovectorization with use of predicated execution of SIMD\ninstructions (e.g. Arm SVE).\n\nTest: test-art-target, test-art-host.\nChange-Id: Ibb7c5520fec6b858fb29f0dde19ec65501831a3a\n" }, { "commit": "9922f00cf68aac69209216a0726a45eb6338763c", "tree": "7e43b55e85ed17443af1c6be6532dafbb8550495", "parents": [ "16527e892b13c9e1fb34f8d2e9993e58a72ac662" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 15:05:15 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 09 10:03:58 2020 +0000" }, "message": "arm/arm64: Clean up intrinsic slow paths.\n\nGeneralize and use the slow path template IntrinsicSlowPath\nfrom intrinsics_utils.h.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boot image is unchanged.\nChange-Id: Ia8fa4e1b31c1f190fc5f02671336caec15e4cf4d\n" }, { "commit": "66704db5967a8eed64f53d82594205d6d48a953d", "tree": "9f10505d9e296cf9c24f4810fc0fd695b2dad233", "parents": [ "ef898425c975f150caaed077ca204fa86b951e7f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 14:04:27 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 14:49:09 2020 +0000" }, "message": "x86/x86-64: Clean up intrinsic codegen for SSE4.1.\n\nLet the normal codegen handle the calls if we\u0027re not\nemitting intrinsics because of lack of SSE4.1 support.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: Ic26e65974231bbcb44ad696100e1fa4469165e41\n" }, { "commit": "ef898425c975f150caaed077ca204fa86b951e7f", "tree": "1ad038b90bb860fe1b9a20872b990c7918fcd1e1", "parents": [ "f7290cac4af6a981d98122af1a6d48b0e80da574" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 10:26:06 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 12:41:04 2020 +0000" }, "message": "Run LSA as a part of the LSE pass.\n\nMake LSA a helper class, not an optimization pass. Move all\nits allocations to ScopedArenaAllocator to reduce the peak\nmemory usage a little bit.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I7fc634abe732d22c99005921ffecac5207bcf05f\n" }, { "commit": "fc136524f5a99be31f0c37ff849c07fde5629562", "tree": "523aec667aab870e38418d1a8150459a3236292e", "parents": [ "5158d4a204a8e6404d39d9f76021d5de0eef3174" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 27 09:39:32 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 27 13:10:11 2020 +0000" }, "message": "Revert \"Don\u0027t abort for min/max/abs intrinsics, baseline use them.\"\n\nThis reverts commit 91038d67ce011456176411e8f74ed5d2e2440ed3.\n\nReason for revert: These assertions can be reinstated after\n https://android-review.googlesource.com/1283893 .\n\nChange-Id: I7265be87e86a9eabfdc2e9b5c207b633eebc273b\nTest: Rely on TreeHugger.\n" }, { "commit": "695348f4b0541f4373b46eac5830cdd87f71c076", "tree": "f2f6019f0c394f99aaaf9f2f7deec16bf6116b0f", "parents": [ "1f5300a211202442a07607830c6550773ca50b50" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 19 14:42:02 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 20 08:41:09 2020 +0000" }, "message": "Add compiler type to CompilerOptions.\n\nLet CompilerOptions hold the information whether it is AOT\nor JIT compilation, or Zygote JIT for shared code.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: aosp_taimen-userdebug boots.\nChange-Id: Id9200572406f8e43d99b8b61ef0e3edf43b52fff\n" }, { "commit": "8284e9a69535e2d55a9319fb3e631eb70ea4b6cd", "tree": "0fa06e3c25e70d2da63fb3f488995528ed545893", "parents": [ "ad71c9089364eca8415fd5b9b7ba471d19a421dc" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 15 17:14:33 2020 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue May 19 15:08:01 2020 +0000" }, "message": "Add extra failed inlining reasons\n\nAdded reasons for polymorphic invoke, custom, and unresolved.\n\nAdded a counter for the total number of inline attempts.\n\nTest: run dex2oat on APK with --dump-stats\nChange-Id: I57aa83dc7ac5fa8897b0c197f416baf46fbe9d53\n" }, { "commit": "0ddb338f084b1c46efbfa7a79ad6aa1b63a24ded", "tree": "e36eaa49dd79914622fff402f6ca2e829646c3fb", "parents": [ "8bcba2264f5ba66ef8820e3963e838a67bd6215f" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon May 18 11:15:46 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 15:10:40 2020 +0000" }, "message": "ARM64: Combine LSR+ADD into ADD_shift for Int32 HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nIn case of Int32 the multiplication is done into a 64-bit register\nhigh 32 bits of which are only used.\nThe multiplication result might need some ADD/SUB corrections.\nCurrently it is done by extracting high 32 bits with LSR and applying\nADD/SUB. However we can do correcting ADD/SUB on high 32 bits and extracting\nthose bits with the final right shift. This will eliminate the\nextracting LSR instruction.\n\nThis CL implements this optimization.\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I5ba557aa283291fd76d61ac0eb733cf6ea975116\n" }, { "commit": "1439e573517bb9f0b115aef5d3bbd9090751ebd6", "tree": "d6a1a4aed01719e988a8ac0fb81ed2843667d75f", "parents": [ "4be256069c494550037c81272ca4c27bd4a139df" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 12 12:43:09 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 18 09:11:30 2020 +0000" }, "message": "ART: Optimize ADD/SUB+ADD_shift into ADDS/SUBS+CINC for HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nThe multiplication result might need some corrections to be finalized.\nThe last correction is to increment by 1, if the result is negative.\nCurrently it is done with \u0027add result, temp_result, temp_result, lsr #31 or #63\u0027.\nSuch ADD usually has latency 2, e.g. on Cortex-A55.\nHowever if one of the corrections is ADD or SUB, the sign can be detected\nwith ADDS/SUBS. They set the N flag if the result is negative.\nThis allows to use CINC which has latency 1:\n adds temp_result, temp_result, dividend\n cinc out, temp_result, mi\n\nThis CL implements this optimization.\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: Ia6aac6771908e992c86e32fe1694a82bd1b7af0b\n" }, { "commit": "883c1346b87537ed93f7d4fd88bbbb041c14d320", "tree": "efb8205d15d677d3e3fdf90f0ae09c4a2eba9a4f", "parents": [ "612809740453427ce4c9211062794dde3823ab6d" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon May 11 23:30:29 2020 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri May 15 18:06:16 2020 +0100" }, "message": "Revert^2 \"Remove test_per_src from ART tests.\"\n\nSecond attempt at this, which fixes the asan failures.\n\nRemove test_per_src since it is not supported by atest.\nReplace it with gtest_isolate which is transparent to atest,\nand which still allows us to run tests in parallel.\n\nThe size of test binaries halves (from 1GB to 0.5GB).\nTest run-time on host is unchanged.\nTest run-time on target is 4x faster (tested on walleye).\n\nAdded a gtest_main.cc with the gtest isolated main function,\nand ART-specific initialization.\n\nBug: 147819342\n\nTest: m test-art-host-gtest\nTest: art/tools/run-gtests.sh\nTest: art/test/testrunner/run_build_test_target.py art-gtest-asan\nChange-Id: I515c911bb7d44285495802fc66cd732fc8e6d8df\n" }, { "commit": "f91fc1220f1b77c55317ff50f4dde8e6b043858f", "tree": "3b8416a4fa9b9278d1114d4002485e0cb1c704bf", "parents": [ "33c091eaaa0febedc93cff820def75b122fde867" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 13 09:21:00 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 15 14:09:54 2020 +0000" }, "message": "Optimizing: Run gtests without creating the Runtime.\n\nThe only Optimizing test that actually needs a Runtime is\nthe ReferenceTypePropagationTest, so we make it subclass\nCommonCompilerTest explicitly and change OptimizingUnitTest\nto subclass CommonArtTest for the other tests.\n\nOn host, each test that initializes the Runtime takes ~220ms\nmore than without initializing the Runtime. For example, the\nConstantFoldingTest that has 10 individual tests previously\ntook over 2.2s to run but without the Runtime initialization\nit takes around 3-5ms. On target, running 32-bit gtests on\ntaimen with run-gtests.sh (single-threaded) goes from\n~28m47s to ~26m13s, a reduction of ~9%.\n\nTest: m test-art-host-gtest\nTest: run-gtests.sh\nChange-Id: I43e50ed58e52cc0ad04cdb4d39801bfbae840a3d\n" }, { "commit": "33c091eaaa0febedc93cff820def75b122fde867", "tree": "cbbe7369f8206af3180a9530bcd1729042cdd544", "parents": [ "5d2311a349f208f056b33da8fc9c950aad1a7ffe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 14 14:51:11 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 14 19:15:01 2020 +0100" }, "message": "Code sinking can move around LoadString that can throw.\n\nThe test accidentally used a string part of the boot image, which means\nwe know the instruction won\u0027t throw. However, a change in the boot\nclasspath meant the string \"a\" was not part of the boot image anymore,\nand the test started failing.\n\nThe CL now handles the case the LoadString might throw, and treat it\nlike NewInstance/NewArray.\n\nTest: 672-checker-throw-method, 673-checker-throw-vmethod\nBug: 156559242\nChange-Id: If9df2ed2c7c39c56254970172e315ec5113db64e\n" }, { "commit": "5d2311a349f208f056b33da8fc9c950aad1a7ffe", "tree": "c675c1e49da6057ce1ed8f9f453db9881198f30f", "parents": [ "58520dfba31d6eeef75f5babff15e09aa28e5db8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 13 17:30:32 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 14 08:18:05 2020 +0000" }, "message": "Optimizing: Refactor ImprovedOptimizingUnitTest.\n\nAnd merge all functionality into OptimizingUnitTest.\n\nTest: m test-art-host-gtest\nChange-Id: I69a4e8c489462700ec0eb9ed93d5cdbdb6147f1a\n" }, { "commit": "02ca05a5a6e3f5028c6c2987a81be481d07bc617", "tree": "a364c4a46c573fdfddf607b0e78e5fd3f455c17f", "parents": [ "5868adaefe72cc8bcdcd8325c40f712375a506d1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 12 13:58:51 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 13 08:00:22 2020 +0000" }, "message": "Move HandleCache to HGraph.\n\nThis avoids passing the `VariableSizedHandleScope*` argument\naround and eliminates HGraph::inexact_object_rti_ and its\ninitialization. The latter shall allow running Optimizing\ngtests that do not require type information without creating\na Runtime in future. (To be implemented in a separate CL.)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optmizing\nTest: aosp_taimen-userdebug boots.\nChange-Id: I36fe9bc556c6d610d644c8c14cc74c9985a14d64\n" }, { "commit": "5868adaefe72cc8bcdcd8325c40f712375a506d1", "tree": "a1d4328902c4e860fe69c4e4bb34052de2530df3", "parents": [ "5a62af5dc9e9bafeffcac7820e1a5b7586e58477" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 12 11:50:34 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 13 08:00:22 2020 +0000" }, "message": "Move implementations from class_root.h to -inl.h .\n\nMake it possible to include the definition of enum ClassRoot\nwithout pulling in a lot of other headers.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nChange-Id: Ic90fdd70bfe0c5428a5c9a0d7901ea7e15b03488\n" }, { "commit": "5a62af5dc9e9bafeffcac7820e1a5b7586e58477", "tree": "94308509fc9e9610c2d058e0458648807ccb5ae8", "parents": [ "aba509f1624de7fd68409508d7c1600308a4ccc3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 11 15:16:24 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 13 08:00:22 2020 +0000" }, "message": "Optimizing: Create fewer handles in inliner.\n\nUse ObjPtr\u003c\u003e and bool instead of ReferenceTypeInfo to avoid\ncreating unnecessary temporary Handle\u003c\u003es. This should reduce\ncompiler memory use a little bit.\n\nAnd rewrite ReferenceTypePropagation::IsAdmissible() with\nan explicit loop instead of a tail recursion.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nChange-Id: Ic9952134d669b336fb28e6ea13117446d11dc145\n" }, { "commit": "85af16e673c58cef1eb6d764468b7218bc343dae", "tree": "ef52df17437ac4db52b450199d6406e9875f1987", "parents": [ "5b0bbf33180bbf9e7fbe8c952eda16096c637f8c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 12 15:36:52 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 12 16:54:30 2020 +0000" }, "message": "Fix two bugs around aput-object.\n\n- Fix LSE by not removing stores that may throw.\n- Fix nterp to export the PC before calling the aput-object helper.\n\nTest: 726-array-store\nChange-Id: I4fa6c608fc657433dc62ef72a4e94260281db660\n" }, { "commit": "968db3c09e5059e30044d69f1a5fd9bcd937392e", "tree": "5496a327556b30ac2cd1877b515fa852688036bd", "parents": [ "2750a9884d7579f301c7ff65a6daaf8520af7902" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu May 07 12:44:10 2020 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 12 10:35:49 2020 +0100" }, "message": "ARM64: Combine LSR+ASR into ASR for Int32 HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nThe multiplication is done by multiplying 32-bit numbers into a 64-bit\nresult. The high 32 bits of the result are used. In case of Int32 LSR\nis used to get those bits. After that there might be correction\noperations and ASR. When there are no correction operations between LSR\nand ASR they can be combined into one ASR.\n\nThis CL implements this optimization.\n\nImprovements (Pixel 3):\n little core big core\n jit_aot/LoadCheck.RandomSumInvokeStaticMethod 7.1% 8.3%\n jit_aot/LoadCheck.RandomSumInvokeUserClass 4.6% 12.0%\n benchmarksgame/fasta 3.3% 1.0%\n benchmarksgame/fasta_4 2.4% 2.6%\n benchmarksgame/fastaredux 2.2% 2.2%\n SPECjvm2k8 MPEGAudio 1.7% 1.0%\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I5267b38d3a58319e24152917fabe836d5b346bce\n" }, { "commit": "fc5e2ef08c78bcf4a60c5097ff3a7fa80e358522", "tree": "4c1d538f5faf72617e9088b8f99a368b999b32dd", "parents": [ "685c84775f7dfe23197b080e4730435fd80e6d27" ], "author": { "name": "Christopher Ferris", "email": "cferris@google.com", "time": "Fri May 08 00:08:42 2020 +0000" }, "committer": { "name": "Christopher Ferris", "email": "cferris@google.com", "time": "Fri May 08 07:25:07 2020 +0000" }, "message": "Revert \"Remove test_per_src from ART tests.\"\n\nThis reverts commit 8103e479d8f8447584582b2b70752029f7087776.\n\nReason for revert: asan run fails in multiple ways\n\nTest: ran ./art/test/testrunner/run_build_test_target.py art-gtest-asan\nChange-Id: Ib9f2887436a664b64c6410f56a25ae2dd0e0aab4\n" }, { "commit": "8103e479d8f8447584582b2b70752029f7087776", "tree": "53b2be70d195b785fc1d79b6151e42925b4981fe", "parents": [ "6a8f8c52da06de506b75fa524a56a30794849261" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 28 21:36:49 2020 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu May 07 14:45:38 2020 +0100" }, "message": "Remove test_per_src from ART tests.\n\nRemove test_per_src since it is not supported by atest.\nReplace it with gtest_isolate which is transparent to atest,\nand which still allows us to run tests in parallel.\n\nThe size of test binaries halves (from 1GB to 0.5GB).\nTest run-time on host is unchanged.\nTest run-time on target is 4x faster (tested on walleye).\n\nBug: 147819342\nTest: m test-art-host-gtest\nTest: art/tools/run-gtests.sh\nChange-Id: Id295af00d08b24baa2e421b0f3313df0b2e56fe9\n" }, { "commit": "a6653d304faa3bbd981507570a4ac1107760c6a7", "tree": "6dc333f6f19b932c0fd739b4862c3800b3a51b45", "parents": [ "4d0f795aaa9abd1b36e2704b3851b2cc39c70cdd" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 05 16:30:24 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 07 09:04:21 2020 +0000" }, "message": "ART: Refactor InstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant\n\nInstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant handles\nboth Int32 and Int64 cases. However Int32 cases can have additional\noptimizations. Having them in GenerateDivRemWithAnyConstant makes code\ndifficult to read.\n\nThis CL splits the code of GenerateDivRemWithAnyConstant to:\n* GenerateInt32DivRemWithAnyConstant\n* GenerateInt64DivRemWithAnyConstant\n* GenerateResultDivRemWithAnyConstant\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I267331c026e87d6a233b593586f1b74759382896\n" }, { "commit": "1a719e4de83532a1dcd9ddfad2c92d4130f28ea9", "tree": "445026effb3298ca8e962701ee01f65785be6fe6", "parents": [ "e33dca6d44463606168330d2f84bc616e8c147f6" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Jul 18 14:24:55 2019 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Mon May 04 08:19:17 2020 +0000" }, "message": "RFC: ARM64: Split arm64 codegen into scalar and vector (SVE and NEON).\n\nThis is a first CL in the series of introducing arm64 SVE support\nin ART. The patch splits the codegen functionality into scalar and\nvector ones and for the latter introduces NEON and SVE\nimplementations. SVE one currently is an exact copy of NEON one -\nfor the sake of testing and an easy diff when the next CL comes\nwith an actual SVE instructions support.\n\nThe patch effectively doesn\u0027t change any behavior; NEON mode is\nused for vector instructions, tests pass.\n\nTest: test-art-target.\nChange-Id: I5f7f2c8218330998e5a733a56f42473526cd58e6\n" }, { "commit": "0f5b2bf1aee7e08ce3b0dbf91ee528eb846d372f", "tree": "98a84fb54c5d0a8e44fd159c7cd031e6dda84036", "parents": [ "3bae04718647f92d40e8b4c75fb71195a51fa4bd" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Oct 23 14:07:41 2019 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 01 13:43:49 2020 +0000" }, "message": "ART: Introduce Loop Versioning in SuberblockCloner.\n\nSupport Loop Versioning in SuberblockCloner as a tool to\nenable further optimization (e.g. Dynamic Loop Unrolling).\nThe patch brings the feature in without enabling it.\n\nReplace std::cout with LOG(INFO) for debug dumps.\n\nTest: superblock_cloner_test.\nTest: test-art-target.\n\nChange-Id: I303cabfb752b8c3c8597abfc0ac261e8616e8cee\n" }, { "commit": "5f84607854775be67a8eb2437ce1071af7d477d2", "tree": "4d28da38b7170fad07ce08878cedb239f51279da", "parents": [ "c8150b5def82058c23df377a5006a78e7668afeb" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 09 13:20:11 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Apr 17 15:43:48 2020 +0000" }, "message": "Optimizing: Construct intrinsic HIR in builder.\n\nTo help baseline compiler emit better code, construct\nintermediate representation for intrinsics that have\ncorresponding HIR classes in the instruction builder,\ninstead of doing it in the instruction simplifier.\n\nNote: The generated code is sometimes different than\nbefore because GVN uses instruction ids for input\nordering for commutative operations.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nChange-Id: Ifa3a5774f8f3fbff4e3ca359c38eceee993d62cd\n" }, { "commit": "c8150b5def82058c23df377a5006a78e7668afeb", "tree": "8f0e15b91cd55b978ca7f152206f0a550353810a", "parents": [ "b2028739a2db03623ed76f5028ede1333c48f4c9" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 31 18:28:00 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Apr 17 10:35:45 2020 +0000" }, "message": "ART: Refactor SIMD slots and regs size processing.\n\nART vectorizer assumes that there is single size of SIMD\nregister used for the whole program. Make this assumption explicit\nand refactor the code.\n\nNote: This is a base for the future introduction of SIMD slots of\nsize other than 8 or 16 bytes.\n\nTest: test-art-target, test-art-host.\nChange-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c\n" }, { "commit": "b47b978486572492140b63b0c8c5daa58dc28d41", "tree": "546c065d9396ef25bbd08b02d5ef4f6d269babfc", "parents": [ "e778fa6ead79e9cb26810d484c5a594e9612de9b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Dec 04 21:02:09 2019 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Apr 14 10:26:59 2020 +0000" }, "message": "ART: Fix vectorizer HalvingAdd idiom.\n\nIsAddConst2 function tried to extract addition chains\nfor the halving add idiom: (A + B) \u003e\u003e 1. The problem\nwas that regular shift right (x \u003e\u003e 1) was accepted for the\nidiom (with {A: x, B: 0}) and not processed as a shift - which\nbroke the assumptions on shifts right and operand signedness.\nThis CL fixes that.\n\nTest: 646-checker-simd-hadd.\nTest: test-art-target.\n\nChange-Id: Icf71e1a8e8c54e68114d7d5d6c4aa8a47ea5234d\n" }, { "commit": "2f40d24aea4b9b2726c994de71b17ae2f82e9238", "tree": "75194271dac88df6183b8e8034298942d74bc12b", "parents": [ "605c5914b9561c67b4e8b142715410a569f9ca45" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 08 12:56:45 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 09 11:23:00 2020 +0000" }, "message": "Small cleanup in InstructionBuilder.\n\nRefactor BuildInvoke() to reduce runtime state transitions\n(fewer ScopedObjectAccess objects) and separate the class\ninit check for static methods from the instruction creation\nin preparation for allocating replacement instructions for\nintrinsics such as Math.abs().\n\nDelay Handle\u003c\u003e creation in ProcessClinitCheckForInvoke until\nit\u0027s actually needed. Change function parameters to ObjPtr\u003c\u003e\ninstead of Handle\u003c\u003e if they cannot cause thread suspension.\n\nTest: aosp_taimen-userdebug boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I8d5ebf5db76f0c8b1fec790a2f8621818d64b4dc\n" }, { "commit": "605c5914b9561c67b4e8b142715410a569f9ca45", "tree": "7b7f1a73d19ae4df007f50784e16f8f2b65f4f58", "parents": [ "32b24fdc3466d01f799e0ef39859b103d5c701bc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 08 15:12:39 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 09 09:13:47 2020 +0000" }, "message": "Add more DCHECKs to investigate build bot failure.\n\nTest: test.py\nChange-Id: I625564895dd701fb04f1ceb3b7bb21ffa273e776\n" }, { "commit": "fbf53b5e38fef38a2bfdccb433e61d5d4ee802bc", "tree": "fb731d75bcb0fa71d7fa85e664aa1fd34f40cbf5", "parents": [ "4fa07a5727551018e2dcd93d41dac98f20212e99" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 01 15:20:14 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 02 13:02:04 2020 +0000" }, "message": "DCHECK to ensure processing instruction doesn\u0027t leave an exception.\n\nTest: test.py\nChange-Id: I254355c2e4682a94bea71053a19ea8e682e19871\n" }, { "commit": "4fa07a5727551018e2dcd93d41dac98f20212e99", "tree": "8214358e517601c67706a4fbbb4010408a45780a", "parents": [ "d31def587a914c1d306355a7331c24d7b13ad5ca" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Mar 31 20:52:09 2020 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Apr 01 17:19:07 2020 +0100" }, "message": "Add explicit compiler option to enable test-specific features.\n\nWe can no longer rely on checking the \"core.art\" image name,\nsince we plan to remove it and use the shipped boot image.\n\nThis option enables test-specific features, such as $noinline$.\n\nTest: ./art/test.py -r --optimizing --64\nBug: 147817558\nChange-Id: Iadac6e1b0f46e83efd0551fb8462a6b268ad33d8\n" }, { "commit": "f368882656cce265d732cba237fac7bc312934a6", "tree": "157fc1c36079d64f065d2a46d955f3d96ba5e352", "parents": [ "aacb4b84078eacbee31f168676750ca73514217e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 25 15:04:03 2020 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 26 14:20:58 2020 +0000" }, "message": "Add more debugging info around ResolveField.\n\nTo better diagnose the DCHECK that we have hit here:\nhttps://android-build.googleplex.com/builds/git_master-art-host-linux-art-jit/6325844/logs/build.log\n\nTest: test.py\nChange-Id: If160b74055c27cd02bde27e29c7e7f731c458f4d\n" }, { "commit": "41617b18f1c09e3031710d58fdb93c5aa43399ac", "tree": "36a0f3e3dc27e97980b96e1150ede718aee775fa", "parents": [ "842555d72ee7511c193a65f34841cc92170a1850" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Mar 18 21:19:06 2020 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Mar 25 14:10:23 2020 +0000" }, "message": "Add more logging and sanity checks for JIT mini-debug-info.\n\nUsed when diagnosing b/151137723. Keep it around.\n\nBug: 151137723\nTest: test.py -r --jit\nChange-Id: I10cc613c7396607e221fdc1f5972d26c1ac03fa8\n" }, { "commit": "30fd85157260c91327c6b5a0816d312dd505c0e0", "tree": "355823ab233177d529baa873911cf08bb5b5deec", "parents": [ "80dc7dc20855bf680fa598127f26e6047821bdd0" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Feb 20 20:27:58 2020 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Mar 12 12:10:49 2020 +0000" }, "message": "Refactor RemoveNativeDebugInfoForJit.\n\nThis is partial revert of CL/1099280 (Remove global maps).\n\nIt somewhat resurrects the lazy method removal.\n\nThe original goal was to only remove methods from the GC,\nand do all of them in bulk for simplicity and efficiency.\n\nHowever, this is proving infeasible since we have several\ncorner cases which remove methods outside the GC code path.\n\nThe behaviour for the GC code path is preserved by this CL.\nInstead of passing method array, the methods are individually\nmarked for removal and then repacking is immediately forced.\nThe only difference is that coroner cases are done lazily.\n\nTest: ./art/test.py -b -r --host --jit --64\nChange-Id: I42729545d6b51df788d92f9cf149a6e065b90c68\n" }, { "commit": "b1fe5e18318c3af8d0cedc3f19cb6bc51817b859", "tree": "4d88d27299206410ab0908baa9f7d0be14075790", "parents": [ "69828ac1c6de77fadb3660d6f20b52d46440a0a9" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 10 14:30:49 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 10 17:08:03 2020 +0000" }, "message": "HStringBuilderAppend cannot be null.\n\nFix DCHECK() failure where we replaced an instruction\nwith non-null result (HInvoke StringBuilder.toString())\nwith an instruction that did not report that the result\ncannot be null (HStringBuilderAppend) and then used the\nresult as both receiver and argument for String.equals().\nThe fix is to preserve the \"cannot be null\" invariant.\n\nTest: Additional test in 697-checker-string-append.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 151107293\nBug: 19575890\nChange-Id: I205f002bf8d2dfee6079ea0e14786ca0ab2e2e9c\n" }, { "commit": "e521eb041875fbaf99eca5e6d2b438e7040b1dd8", "tree": "8546c64797ca6612ac206899e1dae549e3e1a85e", "parents": [ "8a1a0f719e42746840f88aad079711e9d951b797" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Feb 27 18:51:24 2020 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Mar 04 22:23:22 2020 +0000" }, "message": "ART: Fix a compiler crash for VectorizeDef() idioms.\n\nSAD vectorization idiom (and DotProduct which was based on it)\nhad a bug when some instruction in the loop was visited twice\ncausing a compiler crash. GenerateVecOp() was called for both\nthe idiom root instruction and its argument in the idiom\nvectorization routine; however the argument could have been\nalready processed by that time. It happened when two vectorization\nidioms\u0027 matched patterns had a common sub-expression.\n\nTest: test-art-target.\nTest: 623-checker-loop-regressions.\nChange-Id: I8823c52f8ef62377c29310f0e335b9728d11068a\n" }, { "commit": "6a8e66c753abdb53847107c1cb2f13e9114c811d", "tree": "ea8ca2171ca63818e4d9c3dcdd1d9d80af16d96e", "parents": [ "725da8fb9665abfb9c9c6aaca147120e46381b2d" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Feb 20 19:15:49 2020 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Sat Feb 22 07:24:40 2020 +0000" }, "message": "Remove JIT native debug info on failed commits.\n\nThis could happen if single-implementation assumptions are invalid,\nand would result in temporary double entries in JIT debug info.\n\nTest: ./art/test.py -b -r --host --gcstress --jit --32 -t 068\nChange-Id: I765c9310b6cc4fa440e4121780f8b9053388bd3d\n" }, { "commit": "1868de9c954e057c30ff9a086a213c86a75d7fb6", "tree": "cea533316ad0d1605a62620571426c28fbae147b", "parents": [ "5b768893456ca3a998b7a2a93490229febbec1cf" ], "author": { "name": "Eric Holk", "email": "eholk@google.com", "time": "Wed Feb 12 09:10:21 2020 -0800" }, "committer": { "name": "Eric Holk", "email": "eholk@google.com", "time": "Fri Feb 21 18:51:23 2020 +0000" }, "message": "Refactor inliner\n\nThis change rearranges some of the inliner code. The main goal is to\nmake some of the larger functions more readable and make clearer how to\nmodify the inliner in the future.\n\nSome of the specific changes include:\n\n* Code to find the actually call target has been factored into a\n separate method.\n\n* The call to TryInlineFromEarlyCache has been made into an early exit\n rather than a fall through case. This lowers the indentation level for\n the main inline case.\n\n* Split the initial checks for whether inlining is possible into\n IsInliningAllowed, IsInliningSupported, and\n IsInliningBudgetAvailable. This is to make it more clear why these\n restrictions are in place. Note that some of these checks are now in a\n different order.\n\n* Factor the checks that come after the inlined body has been optimized\n into a separate method. These haven\u0027t been further broken down yet,\n but this would be worthwhile future work.\n\n* Remove CanAllocateRegistersFor. We should be able to allocate\n registers for any compiler we support, and if not, this should be\n caught when we try to allocate registers instead.\n\nBug: 149392334\nTest: ./test/testrunner/testrunner.py --host --optimizing --no-jvmti --ndebug \\\n \t\t\t\t --64\nChange-Id: Ic1b919e306b7b93944ee5686e2a487b2190c087c\n" }, { "commit": "5b768893456ca3a998b7a2a93490229febbec1cf", "tree": "4c88c226cd01758dccd0bbbeeca4d415c069813e", "parents": [ "3cd802e4b80973b2c3893590c90d4bd5859d6dea" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Feb 19 15:49:02 2020 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Feb 21 13:05:33 2020 +0000" }, "message": "Make `libart(d)-disassembler` a requirement of `libart(d)-compiler`.\n\nThe constructor of `art::HGraphVisualizerDisassembler` (which is part\nof `libart(d)-compiler.so`) may dynamically load\n`libart(d)-disassembler.so`; add `libart(d)-disassembler` to the\n`runtime_libs` property of module `libart(d)-compiler` to make sure\nthe former can be found.\n\nAlso promote the failure to dynamically load\n`libart(s)-disassembler.so` in\n`art::HGraphVisualizerDisassembler::HGraphVisualizerDisassembler` from\n`WARNING` to `ERROR`.\n\nTest: art/tools/buildbot-build.sh --host \\\n \u0026\u0026 art/test/testrunner/testrunner.py --host --optimizing \\\n -t 640-checker-integer-valueof\nBug: 149749169\nChange-Id: I307bdf8b71e47ed8da1d6d62ab688c500b3f9c80\n" }, { "commit": "2925311f957f50bbec2b034c98877d22f702ee76", "tree": "31c6bd25134b287622c9998e016606ab2d84607b", "parents": [ "f8f51c9697b1f2a41ea750703087e98c46402f08" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 17 09:40:14 2020 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 17 14:09:02 2020 +0000" }, "message": "Prevent entering IMT conflict trampoline with j.l.Object methods.\n\nThis ensures that only interface methods enter the trampoline.\n\nTest: 725-imt-conflict-object\nChange-Id: Id730d921f213ee0f6d927dea5df69d57be431df0\n" }, { "commit": "67e4a4db302b69fe6e2242aef56f5512bfa8cb34", "tree": "e52dc2c6fd6f8b97e00604307c547ecf35f8df0b", "parents": [ "41b605c5ad4b06ea127ac56c6e3a4c92e8913efd" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Feb 06 15:11:36 2020 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Feb 14 15:31:47 2020 +0000" }, "message": "ART: ARM64: Improve FP IsInfinity intrinsic.\n\nImprove instruction choice; the change brings 4.5%\nperf improvement on a simple microbenchmark.\n\nTest: test-art-target.\nTest: 082-inline-execute.\nChange-Id: I5117d9740caf788d7f0170d3f90a3631e6e57c1b\n" }, { "commit": "54f4fbd1a6834f06dc9b644b865423fdc03afb15", "tree": "4f55b2a196453a8a197a1787a688cc299682e55d", "parents": [ "2d3de3a40015af07f7645a298f77b398af0c6c2c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 12 10:52:22 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Feb 13 09:14:02 2020 +0000" }, "message": "Remove MIPS support from Optimizing.\n\nTest: aosp_taimen-userdebug boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 147346243\nChange-Id: I97fdc15e568ae3fe390efb1da690343025f84944\n" }, { "commit": "002eac6f818dc89c75487ba928fbe5901e4f82e8", "tree": "f49de3d98802b5bd95ed51a3b46b735f58c77f6d", "parents": [ "75bca74ab46799f0b9a2663184efe4735b3bd8c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 04 10:16:51 2020 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 04 13:22:16 2020 +0000" }, "message": "Only flush visualizer output at the end of the compilation.\n\nOtherwise multiple threads compiling will mix their output.\n\nTest: run-tests\nBug: 147094528\nChange-Id: I905c8874cbe2c02c2d79577024d4606a3784b67a\n" }, { "commit": "d71f1dc15e264f9d2122c427a4d99d49b525bfd3", "tree": "9bb30ad7c9420e738ec84f55d6c01b2f3a754ff7", "parents": [ "c124d1dd977a2ddcd6e4928cfe6c0698f44d6523" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Wed Jan 24 17:24:16 2018 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jan 28 17:10:34 2020 +0000" }, "message": "Enable support of VecLoad/VecStore in LSE\n\nChanges:\n- Enable VecLoad and VecStore support in LSE.\n- This CL is based on Mingyao\u0027s CL: More general store elimination.\n- The new gtest load_store_elimination_test is to test some corner cases\n where ArrayGet/ArraySet/VecLoad/VecStore are mixed and overlap.\n- The new java 530-checker-lse-simd.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nTest: load_store_elimination_test\nTest: 530-checker-lse-simd\nTest: ./art/test/run-test --optimizing --64 --gcstress 667-checker-simd-alignment\nTest: m -j80 art-check-testing-apex-gen\n\nChange-Id: I2d2024ec75a2aaef56b527db98abb40c5f16be79\n" }, { "commit": "c1cd1330c65e8b9b13bcd93bd9634eed6453c5dc", "tree": "4fe4f02f8107e761f246745259260356a3bac12f", "parents": [ "08a1d1ba90c69e4b39f2df90eacee2c5413f8b4e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 25 13:08:24 2020 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 25 13:08:24 2020 +0000" }, "message": "Fix braino in arm64 codegen.\n\nPointers are 64bit there...\n\nBug: 148303458\nTest: 597-deopt-busy-loop\nChange-Id: Iee003f883665e4a668068b8e056380abc2f5fab4\n" }, { "commit": "6a67bea2203783db7569cd99cc86e2b63f5e28a7", "tree": "5634c31c3da4eb68294015909bf91b7dfd107087", "parents": [ "4d7b689fe667a65138eceb311767a3d624fb0e4b" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 20 13:05:55 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 20 15:27:36 2020 +0000" }, "message": "Update InstructionBuilder\u0027s IsInBootImage for boot image extension.\n\nFor boot image extension, check both the class being in the\nboot image space and the descriptor being in image classes.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nBug: 119800099\nChange-Id: I56f81d7b7aed20f5ee5c4ffd4d2e01aacd42d243\n" }, { "commit": "a18f5aeaecf9088f1ba1c43e7577dc149f85673f", "tree": "88a98d98edab2c83821a8df17768788245c039a1", "parents": [ "7ee34a1eeba20c1b438f7bcad75adba65dd2a840" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Dec 13 12:53:39 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 08 14:50:06 2020 +0000" }, "message": "Fix StringBuilder append assumptions.\n\nDo not rely on use ordering, it can be different because of\nSimplifyReturnThis(); just use HBackwardInstructionIterator.\nInstead of checking that we find a StringBuilder.toString(),\ncheck that it is the invoke we\u0027re trying to simplify.\n\nAdd regression test 699-checker-string-append2.\n\nTest: testrunner.py --host --jvm -t 699-checker-string-append2\nBug: 19575890\nBug: 146014745\nChange-Id: I7b16f376c16ba5a4107e9718e0acf17d82280f54\n" }, { "commit": "7ee34a1eeba20c1b438f7bcad75adba65dd2a840", "tree": "dc8988724cf4fc414e366c78ad62f5a05366eecb", "parents": [ "7b0df59ff262975916ca9245b4c5092105d971bf" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue Dec 10 11:36:33 2019 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jan 08 14:43:19 2020 +0000" }, "message": "Add OptimizingUnitTestHelper::GraphChecker methods\n\nGraphChecker should be always used in gtests where it is possible.\nCurrently only ImprovedOptimizingUnitTest allows unit tests to use\nGraphChecker. Unit tests based on OptimizingUnitTest cannot use this\nfunctionality.\n\nAnother issue is that GraphChecker has reference type information\nchecks which unit tests cannot satisfy.\n\nThe CL resolves the issues by:\n* Adding a public GraphChecker::SetRefTypeInfoCheckEnabled.\n* Adding a private OptimizingUnitTestHelper::CheckGraph(HGraph* graph,\nbool check_ref_type_info).\n* Adding a public OptimizingUnitTestHelper::CheckGraph(graph) to perform\nall checks.\n* Adding a public\nOptimizingUnitTestHelper::CheckGraphSkipRefTypeInfoChecks(graph) to\nperform all checks but reference type information checks.\n* Updating ImprovedOptimizingUnitTest::CheckGraph to use\nOptimizingUnitTestHelper::CheckGraph.\n\nTo demonstrate how the new API can be used, unit tests for the\nLoad-Store-Analysis pass are updated.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I7ca0983e66d9904073f0d711b3de96cccfe42746\n" }, { "commit": "796aa2cfcde9c88fa0a3176899e25bab3468ebd2", "tree": "9f4be44ef08e5abbdcb16ed6e8d15459bb743222", "parents": [ "57cacb720e6f995aa1a42df6e2e6470a9ec57261" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 10:20:05 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 11:31:30 2019 +0000" }, "message": "[baseline] Check that the profiling info is not null.\n\nZygote cannot allocate profiling infos.\n\nTest: 689-zygote-jit-deopt\nChange-Id: I85e8b7f16b81ba4de435a5417dbb2588c34414b0\n" }, { "commit": "57cacb720e6f995aa1a42df6e2e6470a9ec57261", "tree": "bb73a113c94bc397cd7c99a4c64e033bf29b9803", "parents": [ "013d1ee96b928f3bda9031e94d4a69f827133ce6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Dec 08 22:07:08 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 09:48:00 2019 +0000" }, "message": "Refactor OSR related code to prepare for \"true\" OSR.\n\n- Make the compiler restore all callee-save registers.\n- Make the compiler return any value in a core register: this simplifies\n the current stub, and will also avoid having to look at the return\n type (and reading the shorty) when returning to an nterp frame.\n- Add OsrData and offsets of its members to be used by nterp.\n\nTest: test.py\nBug: 27094810\nChange-Id: Ifa4f4877ab8b1f0c6a96feccea30c909942eb2fa\n" }, { "commit": "52506e2a29b172a4e055ea545800e48b2ca508d5", "tree": "23599ea08495d98f6fdc6c9bf8e39719d3ac8632", "parents": [ "90ceea36a9c6ea123a5e1ad6b001230890406e2f" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Dec 04 15:59:37 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 13 07:12:02 2019 +0000" }, "message": "Add ImprovedOptimizingUnitTest::CreateParameters for subclasses\n\nSubclasses of ImprovedOptimizingUnitTest might need a different number\nof graph parameters. Currently only a parameter is defined and created.\nThis CL adds ImprovedOptimizingUnitTest::CreateParameters which\nsubclasses can override to create as many parameters as they need. All\ncreated parameters are added to the entry basic block. The default\nimplementation of ImprovedOptimizingUnitTest::CreateParameters does\nnothing.\n\nTest: run-gtests.sh\nChange-Id: I2c6a58232e36d3562fc2bc0cdc289dd739094a73\n" }, { "commit": "43f2f75df04495aa3dfd9bb80cf3180887d3b20e", "tree": "f1faf031608da284924e6ccd75b56307d55d17b1", "parents": [ "9317031cd016e02a26cdeea8045df9925b33ffe2" ], "author": { "name": "Alex Light", "email": "allight@google.com", "time": "Wed Dec 04 17:48:45 2019 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Dec 05 08:13:02 2019 +0000" }, "message": "Revert^4 \"Implement Dot Product Vectorization for x86\"\n\nThis reverts commit 8e895008a3e2f2813bb46cb0c6bc76884e46e9ac.\n\nReason for revert: The test failure seems unrelated.\nBug: 144947842\n\nChange-Id: I7b437f0443d71a5c762e1a8372564ed989971cc9\n" }, { "commit": "9b5271e53a76cbe3d269d1b70da7f13b9d944db1", "tree": "ff89e3a40d274e812f5727d7ff7930d19d447d35", "parents": [ "a00b54b74bee06c006b8bebfbef85e2801de293c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 04 14:39:46 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 04 14:39:46 2019 +0000" }, "message": "Get the baseline information from the graph.\n\nBaseline could be set by the compiler options or the JIT.\n\nTest: test.py\nBug: 119800099\nChange-Id: I702bd7642dfd3353c9ad99cb6ac425c090e16101\n" }, { "commit": "4f2e0889d10ae930f944c3c3f3d76e920a86c665", "tree": "f376f84b1c0fa5d64948c35a0340ab5fc5d093c2", "parents": [ "a59af8aeaad8fe7d68d8f8de63eab9cf85b6ab31" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Sun Dec 01 09:57:10 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 03 14:32:35 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API (continued (2)).\n\nMove newly added occurrences of `vixl::aarch64::FPRegister` to\n`vixl::aarch64::VRegister` in `compiler/optimizing/common_arm64.h`.\n\nTest: mmma art\nBug: 144490441\nChange-Id: Id343d64fa00373994db7bf11f5e737cca3a4f2fd\n" }, { "commit": "a59af8aeaad8fe7d68d8f8de63eab9cf85b6ab31", "tree": "83195c74b135731cc4555254763a8f449691c1b0", "parents": [ "5c8cc64b5f1580faf510f27527e7e22987174963" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 17:42:32 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 03 14:32:09 2019 +0000" }, "message": "JIT baseline: trigger optimized compilation on hotness threshold.\n\n- Add a new hotness count in the ProfilingInfo to not conflict with\ninterpreter hotness which may use it for OSR.\n- Add a baseline flag in the OatQuickMethodHeader to identify baseline\ncompiled methods.\n- Add a -Xusetieredjit flag to experiment and test.\n\nBug: 119800099\nTest: test.py with Xusetieredjit to true\n\nChange-Id: I8512853f869f1312e3edc60bf64413dee9143c52\n" }, { "commit": "20036d80f246b564331e0943aa07ec3b50fc15d9", "tree": "68c421f9da0c7ff7453ba5093203b94f9ec283c6", "parents": [ "36ec598a4d887746291d003c97c2cb28b5987768" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 28 16:15:00 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 28 17:16:57 2019 +0000" }, "message": "JIT baseline: don\u0027t update inline caches for intrinsics.\n\nWe already know the target.\n\nBug: 119800099\nTest: test.py --baseline\nChange-Id: I14cdafe233fec83a1f69e307326858c591309c34\n" }, { "commit": "457e9fa3833ef11530056d010f247ad087fd2184", "tree": "54b8a9dcf44646c3e43a9085d581660c5d9a0132", "parents": [ "17a39babb7f42cbe108d6fab2760cbdc68b821a2" ], "author": { "name": "Usama Arif", "email": "usama.arif@linaro.org", "time": "Mon Nov 11 15:29:59 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 28 09:51:05 2019 +0000" }, "message": "ARM64: FP16 greater/less/greaterEquals/lessEquals intrinsics for ARMv8\n\nThis CL implements intrinsics for greater, greaterEquals, less,\nlessEquals methods with ARMv8.2 FP16 instructions. This requires the\nARMv8.2 AArch64 asimd half precision extension.\n\nThe time required in milliseconds to execute the below code for the four\nintrinsics on Pixel3 is (The code below is for FP16.less but is similar\nfor the rest of the intrinsics):\n\n- Java implementation libcore.util.FP16.less():\n - big cluster only: 19876\n - little cluster only: 47525\n- arm64 Intrinisic implementationi for less:\n - big cluster only: 14526 (~27% faster)\n - little cluster only: 45815 (~4% faster)\n\n- Java implementation libcore.util.FP16.lessEquals():\n - big cluster only: 19856\n - little cluster only: 47419\n- arm64 Intrinisic implementation for lessEquals:\n - big cluster only: 14469 (~27% faster)\n - little cluster only: 45762 (~4% faster)\n\n- Java implementation libcore.util.FP16.greater():\n - big cluster only: 19854\n - little cluster only: 47623\n- arm64 Intrinisic implementation for greater:\n - big cluster only: 14519 (~27% faster)\n - little cluster only: 45722 (~4% faster)\n\n- Java implementation libcore.util.FP16.greaterEquals():\n - big cluster only: 19865\n - little cluster only: 47216\n- arm64 Intrinisic implementation for greaterEquals:\n - big cluster only: 14485 (~27% faster)\n - little cluster only: 45729 (~4% faster)\n\npublic static boolean benchmarkComparison(){\n boolean ret \u003d false;\n long before \u003d 0;\n long after \u003d 0;\n before \u003d System.currentTimeMillis();\n for(long i \u003d 0; i \u003c 1e9; i++){\n // FP16.toHalf(12.3) \u003d 0x4a26, FP16.toHalf(12.4) \u003d 0x4a33\n // FP16.toHalf(-12.3) \u003d 0xca26, FP16.toHalf(-12.4) \u003d 0xca33\n ret |\u003d FP16.less((short) 0x4a26,(short) 0x4a33);\n ret |\u003d FP16.less((short) 0x4a33,(short) 0x4a26);\n ret |\u003d FP16.less((short) 0xca26,(short) 0xca33);\n ret |\u003d FP16.less((short) 0xca33,(short) 0xca26);\n }\n after \u003d System.currentTimeMillis();\n System.out.println(\"Time of FP16.less (ms): \" + (after - before));\n System.out.println(ret);\n return ret;\n}\n\nTest: 580-fp16\nTest: art/test/testrunner/run_build_test_target.py -j80 art-test-javac\nChange-Id: Id1a2c3e7328c82c798fcaf1fa74f5908a822cd0b\n" }, { "commit": "17a39babb7f42cbe108d6fab2760cbdc68b821a2", "tree": "5a01000d3ffe684343bae6e69b31a74c9cb6b151", "parents": [ "49af4cae5674c68d492659ab4b4015c3a6562970" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 20:57:48 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 20:58:28 2019 +0000" }, "message": "JIT baseline: Don\u0027t update the inline cache for an intrinsic.\n\nWe already know its target.\n\nTest: 597-deopt-busy-loop with heap poisoning\nBug: 119800099\nChange-Id: Ic0bd780b48e6ee31e2007c04528476fcb7fcc5bf\n" }, { "commit": "e2a3aa988630b3c2952ac44943f03dde60454195", "tree": "acee7012af6e2b161c91e6cd8b7b4d12eb5aa927", "parents": [ "a2c4d61e482a15974e3e220bcd62a64043ee536f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 25 17:52:58 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 14:04:43 2019 +0000" }, "message": "Baseline JIT: update inline caches in compiled code.\n\nIn trying to remove profiling from interpreter, to speed up\ninterpreter performance.\n\nBug: 119800099\nTest: test.py --baseline\nChange-Id: Ica1fa41a889b31262d9f5691b30a31fbcec01b34\n" }, { "commit": "8e895008a3e2f2813bb46cb0c6bc76884e46e9ac", "tree": "c30e54521e1b31eb50e282b54be138f888d9870e", "parents": [ "7c9cfe8b3f986e7cbc18350ad7b9b72f58f5846c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 26 14:05:40 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 26 14:06:21 2019 +0000" }, "message": "Revert \"Revert^2 \"Implement Dot Product Vectorization for x86\"\"\n\nThis reverts commit 7cf5607f472020711e36eedbbfebb25b40d3f90e.\n\nBug: 144947842\n\nReason for revert: Seems to have broken android.jvmti.cts.JvmtiHostTest1936#testJvmt\n\nChange-Id: Ied6ff6ddf1cb2e3e76adcaa0fda5e36af254b7c5\n" }, { "commit": "7c9cfe8b3f986e7cbc18350ad7b9b72f58f5846c", "tree": "838641fd0cecba43abb2a1382aa41c4e2ccc00f1", "parents": [ "d3ed4ada0d2bf6ffa0e997692734fe5016d365e3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 25 17:40:21 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 26 10:31:02 2019 +0000" }, "message": "Honor the --baseline flag for the JIT.\n\nTest: art -Xcompiler-option --baseline uses the baseline compiler.\nChange-Id: I2a5a3ed0038ca965ab1f0cebffb7900e90bae43a\n" }, { "commit": "aedc9bc5ebdacadc9efe4465173e1b7ca7edc226", "tree": "5889afe345495e831f6c390f215fc0ca611b630d", "parents": [ "3c036885d2d5e6129c1d6b5933be2fce13fbdc79" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 04 15:31:42 2019 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 25 13:54:49 2019 +0000" }, "message": "Ensure we can always enter OSR code\n\nWhen the the loop header is not the target of a back-edge,\nwe used to never enter the OSR code even if it\u0027s been compiled.\n\nTest: testrunner.py --host --jit -t 570-checker-osr-locals\n (it used to get stuck, you can kill the dalvikvm to check that\n the weirdLoop was OSR-compiled)\nBug: 136743846\n\nChange-Id: Iae55463eff92adccf9adec842e04f8ff6d9d8568\n" }, { "commit": "142816a6ac2a9261d37cffb7a7367a96f712fde2", "tree": "de5be36fdf80681d3ce517b095e9f2058918a498", "parents": [ "986914bfd60c1cace9726e9029598d72cbf279e1" ], "author": { "name": "Usama Arif", "email": "usama.arif@linaro.org", "time": "Wed Nov 06 16:15:31 2019 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Nov 20 09:18:26 2019 +0000" }, "message": "ARM64: Pass simd half floating point feature to VIXL macroassembler.\n\nVIXL requires NEONHalf CPUFeature to emit half floating points\nNEON instructions.\n\nTest: codegen_test\n\nChange-Id: I797d7a27087103491871e86d283f9860d3f20624\n" }, { "commit": "26f6330d72e90b3162f8ead17a774a78effc82fc", "tree": "55897a392a4eaf43e664cf9be090c8bbcdb1ad92", "parents": [ "a6d7f50d36365e2dc8d19d7b25328b0aff7fd5ce" ], "author": { "name": "Neeraj Solanki", "email": "neeraj.solanki@intel.com", "time": "Tue Oct 15 14:04:15 2019 +0530" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Nov 19 14:04:33 2019 +0000" }, "message": "Partial loop unrolling during auto-vectorization for x86_64 architectures.\n\nTest: ./test.py --host --64\n\nChange-Id: I5186b025a7343f5b1190c1eb4de1610090d113c8\nSigned-off-by: Neeraj Solanki \u003cneeraj.solanki@intel.com\u003e\n" }, { "commit": "56f1332113c3b8b1844c04683b9cb9dc5a0bd346", "tree": "849942dca13874ef8e86f6ad9cce76ad5152b429", "parents": [ "3e20d0a7748c8810bff9fe99298758930fbe5300" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 15 14:07:19 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 15 17:42:51 2019 +0000" }, "message": "Fix pruning invoke environment for StringBuilder append pattern.\n\nTest: Extra test in 697-checker-string-append\nTest: testrunner.py --host --optimizing\nBug: 19575890\nBug: 144300699\nChange-Id: I3934eb01a62dbbed8b8f9f94ce3ba02051538bb0\n" }, { "commit": "52f8e5c2d3f9a475f6877b716642cf2af41dd4d7", "tree": "1f589f16e497675a4ae3daf6445d5aa8b0bd7bfd", "parents": [ "2221bafe9ad4f7f69d8dc67fa19aaee0f2e51bcd" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Nov 13 17:30:27 2019 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 14 15:11:39 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API (continued).\n\nMove newly added occurrences of `vixl::aarch64::FPRegister` to\n`vixl::aarch64::VRegister` in `compiler/optimizing/intrinsics_arm64.cc`.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I32010cc4c44212f49facf96b50a3d59f3333b4b1\n" }, { "commit": "681692b6291008caaddf4971eab7ea9f9b25d9ca", "tree": "cad26b5b6016cc27baa480e5f4b83faac3317ef0", "parents": [ "665aac46784684dfb85fe999f6a566ed0cf173ef" ], "author": { "name": "Usama Arif", "email": "usama.arif@linaro.org", "time": "Wed Oct 30 16:23:26 2019 +0000" }, "committer": { "name": "Hans Boehm", "email": "hboehm@google.com", "time": "Tue Nov 12 20:58:17 2019 +0000" }, "message": "ARM64: FP16.rint() intrinsic for ARMv8\n\nThis CL implements an intrinsic for rint() method with\nARMv8.2 FP16 instructions.\n\nThis intrinsic implementation achieves bit-level compatibility with the\noriginal Java implementation android.util.Half.rint().\n\nThe time required in milliseconds to execute the below code on Pixel3:\n- Java implementation android.util.Half.rint():\n - big cluster only: 19828\n - little cluster only: 61457\n- arm64 Intrinisic implementation:\n - big cluster only: 14186 (~28% faster)\n - little cluster only: 54405 (~11% faster)\n\nAnalysis of this function with simpleperf showed that approximately only\n60-65% of the time is spent in libcore.util.FP16.rint. So the percentage\nimprovement using intrinsics is likely to be more than the numbers stated\nabove.\n\nAnother reason that the performance improvement with intrinsic is lower\nthan expected is because the java implementation for values between -1 and\n1 (abs \u003c 0x3c00) only requires a few instructions and should almost give\na similar performance to the intrinsic in this case. In the benchmark function\nbelow, 46.8% of the values tested are between -1 and 1.\n\npublic static short benchmarkrint(){\n short ret \u003d 0;\n long before \u003d 0;\n long after \u003d 0;\n before \u003d System.currentTimeMillis();\n for(int i \u003d 0; i \u003c 50000; i++){\n for (short h \u003d Short.MIN_VALUE; h \u003c Short.MAX_VALUE; h++) {\n ret +\u003d FP16.rint(h);\n }\n }\n after \u003d System.currentTimeMillis();\n System.out.println(\"Time of FP16.rint (ms): \" + (after - before));\n System.out.println(ret);\n return ret;\n}\n\nTest: 580-fp16\nTest: art/test/testrunner/run_build_test_target.py -j80 art-test-javac\nChange-Id: I075c3e85a36fd9bce14deee437c5b961bd667b5d\n" }, { "commit": "665aac46784684dfb85fe999f6a566ed0cf173ef", "tree": "343d6956068b1c21e0fc4af018e1322d7685411b", "parents": [ "b9f02c2f8624bbf0746939e3b2735a1537a567b6" ], "author": { "name": "Usama Arif", "email": "usama.arif@linaro.org", "time": "Tue Oct 29 11:13:18 2019 +0000" }, "committer": { "name": "Hans Boehm", "email": "hboehm@google.com", "time": "Tue Nov 12 20:58:17 2019 +0000" }, "message": "ARM64: FP16.ceil() intrinsic for ARMv8\n\nThis CL implements an intrinsic for ceil() method with\nARMv8.2 FP16 instructions.\n\nThis intrinsic implementation achieves bit-level compatibility with the\noriginal Java implementation android.util.Half.ceil().\n\nThe time required in milliseconds to execute the below code on Pixel3:\n- Java implementation android.util.Half.ceil():\n - big cluster only: 19447\n - little cluster only: 62638\n- arm64 Intrinisic implementation:\n - big cluster only: 14260 (~27% faster)\n - little cluster only: 54387 (~13% faster)\n\nAnalysis of this function with simpleperf showed that approximately only\n60-65% of the time is spent in libcore.util.FP16.ceil. So the percentage\nimprovement using intrinsics is likely to be more than the numbers stated\nabove.\n\nAnother reason that the performance improvement with intrinsic is lower\nthan expected is because the java implementation for values between -1 and\n1 (abs \u003c 0x3c00) only requires a few instructions and should almost give\na similar performance to the intrinsic in this case. In the benchmark function\nbelow, 46.8% of the values tested are between -1 and 1.\n\npublic static short benchmarkCeil(){\n short ret \u003d 0;\n long before \u003d 0;\n long after \u003d 0;\n before \u003d System.currentTimeMillis();\n for(int i \u003d 0; i \u003c 50000; i++){\n for (short h \u003d Short.MIN_VALUE; h \u003c Short.MAX_VALUE; h++) {\n ret +\u003d FP16.ceil(h);\n }\n }\n after \u003d System.currentTimeMillis();\n System.out.println(\"Time of FP16.ceil (ms): \" + (after - before));\n System.out.println(ret);\n return ret;\n}\n\nTest: 580-fp16\nTest: art/test/testrunner/run_build_test_target.py -j80 art-test-javac\nChange-Id: I5474c1d0d7c08ec77a6f82c4fb67f555253bfa67\n" }, { "commit": "b9f02c2f8624bbf0746939e3b2735a1537a567b6", "tree": "ac6ad1f4125bd459a3b424cb5ff8b8029a3d5c7e", "parents": [ "f1b18facd1edd6c8652c42085c5432c878507c8e" ], "author": { "name": "Usama Arif", "email": "usama.arif@linaro.org", "time": "Fri Oct 25 17:37:33 2019 +0100" }, "committer": { "name": "Hans Boehm", "email": "hboehm@google.com", "time": "Tue Nov 12 20:58:17 2019 +0000" }, "message": "ARM64: FP16.floor() intrinsic for ARMv8\n\nThis CL implements an intrinsic for floor() method with ARMv8.2 FP16\ninstructions. This intrinsic calls a template GenerateFP16Round function\nwhich will be used to implement other intrinisics such as ceil and\nrint.\n\nThis intrinsic implementation achieves bit-level compatibility with the\noriginal Java implementation android.util.Half.floor().\n\nThe time required in milliseconds to execute the below code on Pixel3:\n- Java implementation android.util.Half.floor():\n - big cluster only: 18623\n - little cluster only: 60424\n- arm64 Intrinisic implementation:\n - big cluster only: 14213 (~24% faster)\n - little cluster only: 54398 (~10% faster)\n\nAnalysis of this function with simpleperf showed that approximately only\n60-65% of the time is spent in libcore.util.FP16.floor. So the percentage\nimprovement using intrinsics is likely to be more than the numbers stated\nabove.\n\nAnother reason that the performance improvement with intrinsic is lower\nthan expected is because the java implementation for values between -1 and\n1 (abs \u003c 0x3c00) only requires a few instructions and should almost give\na similar performance to the intrinsic in this case. In the benchmark function\nbelow, 46.8% of the values tested are between -1 and 1.\n\npublic static short benchmarkFloor(){\n short ret \u003d 0;\n long before \u003d 0;\n long after \u003d 0;\n before \u003d System.currentTimeMillis();\n for(int i \u003d 0; i \u003c 50000; i++){\n for (short h \u003d Short.MIN_VALUE; h \u003c Short.MAX_VALUE; h++) {\n ret +\u003d FP16.floor(h);\n }\n }\n after \u003d System.currentTimeMillis();\n System.out.println(\"Time of FP16.floor (ms): \" + (after - before));\n System.out.println(ret);\n return ret;\n}\n\nTest: 580-fp16\nTest: art/test/testrunner/run_build_test_target.py -j80 art-test-javac\n\nChange-Id: Iad1dd032d456af54932f13c5cf27228f8652a0b5\n" }, { "commit": "7d48dcd51db4b950c22ec78ef3caa53fdf4214d3", "tree": "72600968b1daf5682018880f20ca07610e62b8e7", "parents": [ "f05f04b429a63eb036f501866a863109f05b95b2" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Oct 16 12:46:28 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 31 14:56:52 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API\n\nVIXL has had FPRegister as an alias for VRegister for backward\ncompatibility. In the latest upstream VIXL the alias has been removed and all\nFPRegister based API has became VRegister based. As AOSP VIXL is being\nupdated to the latest upstream VIXL all uses of FPRegister based API\nmust be replaced with VRegister based API.\nThis CL moves ART from FPRegister based API to VRegister based API.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I12541c16d0557835ea19c8667ae18c6601359b05\n" }, { "commit": "7cf5607f472020711e36eedbbfebb25b40d3f90e", "tree": "71f30133f4650656911f2fb72e3b8d203b355635", "parents": [ "d55b844e39c4d5eb1a56de6cb95c891659f8a27f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 29 10:17:53 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 31 09:19:22 2019 +0000" }, "message": "Revert^2 \"Implement Dot Product Vectorization for x86\"\n\nThis reverts commit b8c884e5f22390386b202459ab55ef3046631e42.\n\nAnd fixes a codegen bug (the reason why the original CL was\nreverted).\n\nTest: 684-checker-simd-dotprod\nTest: DEX2OAT_HOST_INSTRUCTION_SET_FEATURES\u003d\"sse4.1\" test.py --host\nTest: test.py --host --jit --gcstress\nChange-Id: Ibef925d1037abc9cb5f3d4dbd79f1d1eceae2f71\nSigned-off-by: Shalini Salomi Bodapati \u003cshalini.salomi.bodapati@intel.com\u003e\n" }, { "commit": "45217376b527cd17d758152c54960e6786288e31", "tree": "cc2ae731f7ebfe61af74fa8150025064a0245a8a", "parents": [ "8b236fac816beb18e4919e2c4260da843257a4e3" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Apr 03 10:46:13 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Oct 29 15:40:27 2019 +0000" }, "message": "Fix intersecting live ranges created by instruction scheduler\n\nWhen scheduling code like the following:\nLOOP:\n v2\u003dphi(v0, v1)\n use(v2)\n v1\u003d...\n goto LOOP\n\nthe instruction scheduler can move \u0027v1\u003d...\u0027 before \u0027use(v2)\u0027. This\ncauses live ranges of v1 and v2 to intersect and results to a MOV\ninstruction to be created.\n\nThe CL fixes this.\n\nImprovements, Pixel3:\n Little CPU, arm64\n micro/GCCLoops\n Example12 14.1%\n Example10b 11.0%\n Example23 8.1%\n Example24 6.6%\n Example10a 5.0%\n FFT workload 4.7%\n Compress workload 1.2%\n\n Little CPU, arm32\n micro/GCCLoops\n Example23 7.5%\n Example24 4.3%\n MonteCarlo workload 1.35%\n\n Big CPU, arm32 and arm64\n No significant improvements\n\nNo significant regressions (\u003e 5%) are found.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I1e4282af18f2d51fde5325a0c00a57e8bbc4fbed\n" }, { "commit": "7f958e36546bc0ebf92573da24ff620179526243", "tree": "a712a5527fdb5fe0b3e14b6f17fea90a89f55ecc", "parents": [ "7814c122dd35ac5c79e7b76b12f1ae95201739a1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 24 09:03:58 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 25 08:16:27 2019 +0000" }, "message": "Revert^2 \"ARM64: toHalf() intrinsic for ARMv8\"\n\nThis reverts commit 67bf99b8a575b15c117a3fbf7aae421330e4795a.\n\nReason for revert: The original CL was reverted because\nof build breakages not directly related to the CL itself.\n\nChange-Id: Ic98e9912701d81d73bc3af719a7e3a8e44e8c058\n" }, { "commit": "67bf99b8a575b15c117a3fbf7aae421330e4795a", "tree": "2077b459c5b43c3b1399544faf07a326e253681a", "parents": [ "2cc0c0f4b6a76dfb1ad205cfd79efe7efe2904d6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 23 13:29:10 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 23 13:29:10 2019 +0000" }, "message": "Revert \"ARM64: toHalf() intrinsic for ARMv8\"\n\nThis reverts commit 2cc0c0f4b6a76dfb1ad205cfd79efe7efe2904d6.\n\nReason for revert: Broke some builds. To be investigated.\n\nBug: 143205070\nChange-Id: Ib36e149cc5ed7f53c932c0b611b43c28d19f22dc\n" }, { "commit": "2cc0c0f4b6a76dfb1ad205cfd79efe7efe2904d6", "tree": "5ff5f5f7c5c25f441a36506a84988fa95d2dbd46", "parents": [ "b8c884e5f22390386b202459ab55ef3046631e42" ], "author": { "name": "Usama Arif", "email": "usama.arif@linaro.org", "time": "Tue Oct 15 15:36:51 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 23 12:04:00 2019 +0000" }, "message": "ARM64: toHalf() intrinsic for ARMv8\n\nThis CL implements an intrinsic for toHalf() method with\nARMv8.2 FP16 instructions.\n\nThis intrinsic implementation achieves bit-level compatibility with the\noriginal Java implementation android.util.Half.toFloat().\n\nThe time required to execute the below code on Pixel3:\n- Java implementation android.util.Half.toFloat():\n - big cluster only: 2136ms\n - little cluster only: 6442ms\n- arm64 Intrinisic implementation:\n - big cluster only: 1347ms (~37% faster)\n - little cluster only: 4937ms (~ 23% faster)\n\nint benchmarkToHalf() {\n int result \u003d 0;\n // 5.9605E-8 is the smallest positive subnormal number that can be\n // represented by FP16. This is 0x33800032 in float bits.\n int raw_input \u003d 0x33800032;\n long before \u003d 0;\n long after \u003d 0;\n before \u003d System.currentTimeMillis();\n do {\n float input \u003d Float.intBitsToFloat(raw_input);\n short output \u003d FP16.toHalf(input);\n result +\u003d output;\n } while (++raw_input !\u003d 0x477fff00);\n // 65535 is the max possible integer that can be represented by FP16.\n //This is 0x477fff00 in float bits.\n after \u003d System.currentTimeMillis();\n System.out.println(\"Time of FP16.toHalf (ms): \" + (after - before));\n return result;\n}\n\nTest: 580-fp16\nTest: art/test/testrunner/run_build_test_target.py -j80 art-test-javac\nTest: test-art-host, test-art-target\n\nChange-Id: I69b152682390e5ffa5b3fdca60b496261191655d\n" }, { "commit": "b8c884e5f22390386b202459ab55ef3046631e42", "tree": "2077b459c5b43c3b1399544faf07a326e253681a", "parents": [ "4b7caeee57767f6bce7bb138a1299c0ae84bebf9" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 23 11:59:49 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 23 11:59:49 2019 +0000" }, "message": "Revert \"Implement Dot Product Vectorization for x86\"\n\nThis reverts commit 4b7caeee57767f6bce7bb138a1299c0ae84bebf9.\n\nReason for revert: Test failure in jit-gcstress mode.\n+Exception in thread \"main\" java.lang.Error: Expected: 131072, found: 0\n+ at other.TestCharShort.expectEquals(TestCharShort.java:474)\n+ at other.TestCharShort.testDotProd(TestCharShort.java:486)\n+ at other.TestCharShort.run(TestCharShort.java:525)\n+ at Main.main(Main.java:28)\n\nChange-Id: I251cf666e8335499d227910987b2d49629c3f53d\n" }, { "commit": "4b7caeee57767f6bce7bb138a1299c0ae84bebf9", "tree": "7d744af39f9b09108e9ba81a85023a79a46f9853", "parents": [ "3981da539bdf249da2be5c4c9dbc4ee59e64d332" ], "author": { "name": "Shalini Salomi Bodapati", "email": "shalini.salomi.bodapati@intel.com", "time": "Tue Oct 15 15:16:22 2019 +0530" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 23 10:37:54 2019 +0000" }, "message": "Implement Dot Product Vectorization for x86\n\n8% improvement in microbench for integral data types\n\nTest: ./test.py --host --64\nChange-Id: I26b584f29d677283195c69b68650651368c656d1\nSigned-off-by: Shalini Salomi Bodapati \u003cshalini.salomi.bodapati@intel.com\u003e\n" }, { "commit": "98e97c6953e970ce99e53640c963fa79a525b1eb", "tree": "8cecf0e18d95b78118e439394060b0c940f05ac8", "parents": [ "47c4ccdee17fd6f814b23fc6342498627cb448ab" ], "author": { "name": "Nick Desaulniers", "email": "ndesaulniers@google.com", "time": "Fri Oct 18 14:25:19 2019 -0700" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Oct 21 07:38:54 2019 +0000" }, "message": "[art] fix -Wimplicit-int-float-conversion\n\nkPrimIntMax cannot be precisely represented as an IEEE 754 single\nprecision float.\n\nkPrimLongMax cannot be precisely represented as an IEEE 754 single\nprecision float or double precision double.\n\nAccept the imprecision as per the local comments in the code.\n\nBug: 139945549\nTest: mm\nChange-Id: I598544fb2cd8904b321803ed04202ba0a694cdc1\nSigned-off-by: Nick Desaulniers \u003cndesaulniers@google.com\u003e\n" }, { "commit": "706e778ef7a84ddfef82e8e2e43f852960849935", "tree": "46a213bcc6926956298275629aa2b42eeebc0ed1", "parents": [ "352482c000830755405f5da3624891ff4690a36a" ], "author": { "name": "Nick Desaulniers", "email": "ndesaulniers@google.com", "time": "Wed Oct 16 10:02:23 2019 -0700" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 17 13:26:49 2019 +0000" }, "message": "[art] fix -Wimplicit-int-float-conversion\n\nkPrimIntMax and kPrimLongMax are too large in value to be precisely\nrepresented by IEEE 754 single and double precision, respectively.\n\nThe code in question is clamping the `value` to the above kConstants.\nIn this case, the imprecision doesn\u0027t result in logical errors. Accept\nthe imprecision via explicit cast.\n\nFixes:\nart/compiler/optimizing/nodes.cc:1597:22: error: implicit conversion\nfrom \u0027const int32_t\u0027 (aka \u0027const int\u0027) to \u0027float\u0027 changes value from\n2147483647 to 2147483648 [-Werror,-Wimplicit-int-float-conversion]\n if (value \u003e\u003d kPrimIntMax)\n ~~ ^~~~~~~~~~~\nart/compiler/optimizing/nodes.cc:1605:22: error: implicit conversion\nfrom \u0027const int64_t\u0027 (aka \u0027const long\u0027) to \u0027float\u0027 changes value from\n9223372036854775807 to 9223372036854775808\n[-Werror,-Wimplicit-int-float-conversion]\n if (value \u003e\u003d kPrimLongMax)\n ~~ ^~~~~~~~~~~~\nart/compiler/optimizing/nodes.cc:1629:22: error: implicit conversion\nfrom \u0027const int64_t\u0027 (aka \u0027const long\u0027) to \u0027double\u0027 changes value from\n9223372036854775807 to 9223372036854775808\n[-Werror,-Wimplicit-int-float-conversion]\n if (value \u003e\u003d kPrimLongMax)\n ~~ ^~~~~~~~~~~~\n\nBug: 139945549\nTest: mm\nChange-Id: I60582c13cfaceb6c6b217e13d7e9bd04d94874fe\nSigned-off-by: Nick Desaulniers \u003cndesaulniers@google.com\u003e\n" }, { "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0", "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f", "parents": [ "e2727154f25e0db9a5bb92af494d8e47b181dfcf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n" }, { "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf", "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8", "parents": [ "c78860b91ae07eed92f86876e7a03132adea6fcd" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 10 10:46:42 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 08:22:00 2019 +0000" }, "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n - before:\n arm: 2396152\n arm64: 3345280\n - after:\n arm: 2016176 (-371KiB, -15.9%)\n arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n" }, { "commit": "adb66f967432ff1f0d51726923a64943c9f1d35b", "tree": "1444900ef83edb837c446361ef38bbf17c17f50c", "parents": [ "ff258063f2748aadf0ea83d0d284b1bedaf792d9" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Oct 10 12:59:43 2019 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Oct 10 17:34:37 2019 +0000" }, "message": "Revert^2 \"JIT: Separate code allocation and initialization.\"\n\nThis reverts commit 63b0c26aae3e7237166dd781eb7a15fbc7c091c2.\n\nTest: ./art/test.py -b -r --host --all-gc -t 708\nReason for revert: Reland after bug fix.\nChange-Id: Ic13e2799bf4bdd8ca468f72cc0f3b72f224f2b08\n" }, { "commit": "98416bf06592493ee6fde039af5eaa5efab73acc", "tree": "a0052ec5364ce1068639a9b7d7355683eb691371", "parents": [ "63b0c26aae3e7237166dd781eb7a15fbc7c091c2" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Sep 09 14:52:12 2019 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu Oct 10 13:06:08 2019 +0100" }, "message": "Fix uses of MaybeRecordImplicitNullCheck without special scopes\n\nMaybeRecordImplicitNullCheck is a function which uses\nCodeGenerator::RecordPcInfo() and requires an exact PC. However for ARM32/ARM64,\nwhen CodeGenerator::RecordPcInfo() is used without VIXL special scopes (EmissionCheckScope,\nExactAssemblyScope) there is no guarantee of an exact PC. Without the special scopes VIXL might\nemit veneer/literal pools affecting a PC.\nThe ARM32 code generator has uses of MaybeRecordImplicitNullCheck without the\nspecial scopes.\n\nThis CL fixes missing special scopes in the ARM32/ARM64 code generators.\nIt also changes API to prevent such cases:\n1. A variant of CodeGenerator::RecordPcInfo with native_pc as a\nparameter is added. The old variant (where Assembler::CodePosition is used) is\nkept and documented that Assembler::CodePosition is target-dependent and\nmight be imprecise.\n2. CodeGenerator::MaybeRecordImplicitNullCheck is made virtual. Checks\nare added to ARM32/ARM64 code generators that\nMaybeRecordImplicitNullCheck is invoked within VIXL special scopes.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\n\nChange-Id: Ic66c16e7bdf4751cbc19a9de05846fba005b7f55\n" }, { "commit": "63b0c26aae3e7237166dd781eb7a15fbc7c091c2", "tree": "5713f52331c0cd3b881df80f4314f9ea2a0f09db", "parents": [ "e1b36f09cb478a39ba443f6acb11cd1901c01c1d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 09 20:12:15 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 09 20:12:15 2019 +0000" }, "message": "Revert \"JIT: Separate code allocation and initialization.\"\n\nThis reverts commit e1b36f09cb478a39ba443f6acb11cd1901c01c1d.\n\nReason for revert: Crashes in art::jit::JitMemoryRegion::FreeCode\nhttps://logs.chromium.org/logs/art/buildbucket/cr-buildbucket.appspot.com/8900060997388741808/+/steps/test_libcore/0/stdout\n\nChange-Id: I40259baec9acbb7889732548f8b31e0a48651cd9\n" }, { "commit": "e1b36f09cb478a39ba443f6acb11cd1901c01c1d", "tree": "75642c703fee9fce7cd09af344dd26d485379b13", "parents": [ "449011217844401ed491ad0f89dcba21cc26bfc4" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Oct 04 17:44:33 2019 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Oct 09 15:51:56 2019 +0000" }, "message": "JIT: Separate code allocation and initialization.\n\nAllocate(reserve) both code and data first,\nand then initialise(commit) both of them.\n\nThis is useful since we know the address sooner\nfor the purpose of debug info generation.\n\nTest: ./art/test.py -b -r --jit --host --64\nChange-Id: I4971a8801004efbc6c2b27884834dda775b72664\n" }, { "commit": "2bb44fe818f2bf1d867a6ae490ef69c7f3a51e97", "tree": "c1860179daba52ab0d53707650c1e85194399629", "parents": [ "59770df741b87b201e83ef81cbcfac9df048d19b" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 04 12:28:14 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 09 08:25:22 2019 +0000" }, "message": "ARM64: Change code emitted by ClinitCheck.\n\nChange the code from MVN+CBNZ to CMP+BLO. The latter is\nbetter optimized in ARM64 CPUs. To avoid increasing code\nsize, this requires the preceding load to be changed from\nLDR to LDRB for a single byte of the 32-bit field.\n\nThis shows small but measurable improvement on a few Golem\nbenchmarks, for example MicroLambda, KotlinAutoReversiBench\nand KotlinImgProc-GaussianBlurOpt.\n\nTest: testrunner.py --target --optimizing\nBug: 36692143\nChange-Id: Ia73f791d7026220ef38e73bd5ee19fcc4877564d\n" }, { "commit": "444e998f5987007bd2783b4d88a9970d1a17736f", "tree": "ef8a93058e973c2c0cf022ea2265679cbb783580", "parents": [ "44ab2cd97c7f4086013a766f442d2f9f619efcc8" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Oct 02 17:59:23 2019 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Oct 08 13:43:16 2019 +0000" }, "message": "JIT mini-debug-info: Generate the debug info sooner.\n\nWe need to add the debug info before the entry-point is set,\notherwise there is window of time when we are missing it.\n\nTest: test.py -b -r --optimizing --jit --host --64\nChange-Id: I3bbad0c96d68e9603bac131faee498b8b9f62699\n" }, { "commit": "988c3911671598d7c840c65bf1cdfafa1e05c582", "tree": "2ee476b2dbd75fa9c36cfdb28dbcede539eac195", "parents": [ "4bbc62ba98a74885dcc7fd21b468808774db5a8b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Sep 25 19:33:35 2019 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 01 12:20:13 2019 +0000" }, "message": "Fix null checks on volatile reference field loads on ARM64.\n\nART\u0027s compiler adds a null check HIR instruction before each field\nload HIR instruction created in the instruction builder phase. When\nimplicit null checks are allowed, the compiler elides the null check\nif it can be turned into an implicit one (i.e. if the offset is within\na system page range).\n\nOn ARM64, the Baker read barrier thunk built for field reference loads\nneeds to check the lock word of the holder of the field, and thus\nincludes an explicit null check if no null check has been done before.\nHowever, this was not done for volatile loads (implemented with a\nload-acquire instruction on ARM64). This change adds this missing null\ncheck.\n\nTest: art/test/testrunner/testrunner.py --target --64 -t 1004-checker-volatile-ref-load\nBug: 140507091\nBug: 36141117\nChange-Id: Ie94f2e73d2f439ae4460549d7b71848401602a21\n" }, { "commit": "f84ef3192bcc167c627e8e13a48b112f017821c2", "tree": "12384b891140205768689bde6e3dfd43f734f529", "parents": [ "d0d215acfcdc1cdab12ce7cd1e261f5b5f3aa1bd" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 24 19:30:44 2019 -0700" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 26 00:35:55 2019 +0000" }, "message": "Implement \u003c\u003c operator for ProfileCompilationInfo::DexRefence\n\nIt avoids the need to use inner fields in the inliner.\n\nBug: 139884006\nTest: m test-art-host-gtest\nChange-Id: I3b2276094829a0e431dc145bf1ff13cbfa746742\n" }, { "commit": "4ad95214341f03d11f06e82fd92ac22b3605586d", "tree": "3dde60deb636cb33f4c59bb26d9f9b516d908ad0", "parents": [ "45cdd05e32bdff1cea8581bc9ecf8a8cb08d6f5b" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Sep 23 23:39:41 2019 -0400" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 26 00:35:55 2019 +0000" }, "message": "Make explicit which methods retrieve info about *hot* methods\n\nRename some methods to better highlight that they refer to hot methods and not\nto any method (e.g. a non-hot, startup methods).\n\nBug: 139884006\nTest: m test-art-host\n\nChange-Id: Ieb3a36c434104d1cde28ca18a5b335cc8a24e537\n" }, { "commit": "48349ad38887f65da76df268f8e548d508d8c6a1", "tree": "0e89e6cde84b2120aaf9ad9d362e61ab8d3b95c2", "parents": [ "1ba7fec112f61342d5fc2b16542fad141fd25bf1" ], "author": { "name": "Neeraj Solanki", "email": "neeraj.solanki@intel.com", "time": "Mon Aug 05 23:16:56 2019 +0530" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Sep 24 17:16:38 2019 +0000" }, "message": "AVX support for bitwise instructions (Xor, Or, And, Andn)\n\nTest: ./test.py --host --64, test-art-host-gtest\n\nChange-Id: Ia8302d12d3ebb8447d73db576fb5b945485c11e1\nSigned-off-by: Neeraj Solanki \u003cneeraj.solanki@intel.com\u003e\n" }, { "commit": "53d220e4ab1fc09921e11cabd8fdba388079f792", "tree": "6d0f5dc6a509f903e1706996a90792ad5863877d", "parents": [ "d7ea0437a8dd11253b55651fcfab23b65d504ee2" ], "author": { "name": "David Horstmann", "email": "david.horstmann@linaro.org", "time": "Tue Jul 16 16:00:10 2019 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Sep 23 12:10:12 2019 +0000" }, "message": "ART: Improve VisitStringGetCharsNoCheck intrinsic for compressed strings, using SIMD\n\nThe previous implementation of VisitStringGetCharsNoCheck\ncopies one character at a time for compressed strings (that\nuse 8 bits per char).\n\nInstead, use SIMD instructions to copy 8 chars at once\nwhere possible.\n\nOn a Pixel 3 phone:\n\nMicrobenchmarks for getCharsNoCheck on varying string\nlengths show a speedup of up to 80% (big cores) and\n70% (little cores) on long strings, and around 30% (big)\nand 20% (little) on strings of only 8 characters.\n\nThe overhead for strings of \u003c 8 characters is ~3%,\nand is immediately amortized for strings of more\nthan 8 characters.\n\nDhrystone shows a consistent speedup of around 6% (big)\nand 4% (little).\n\nThe getCharsNoCheck intrinsic is used by the StringBuilder\nappend() method, which is used by the String concatenate\noperator (\u0027+\u0027).\n\nImage size change:\n Before:\n boot-core-libart.oat: 549040\n boot.oat: 3789080\n boot-framework.oat: 13356576\n After:\n boot-core-libart.oat: 549024 (-16B)\n boot.oat: 3789144 (+64B)\n boot-framework.oat: 13356576 (+ 0B)\n\nTest: test_art_target.sh, test_art_host.sh\nTest: 536-checker-intrinsic-optimization\n\nChange-Id: I865e3df6d4725e151ae195a86e02e090dae8dd29\n" }, { "commit": "4ba700af65f8346a96ba8d1dec051358a09487f4", "tree": "eaada5d02371099b84a5d0d27f210f635400f7ba", "parents": [ "1550a669adb7e9328879bed24d9edc22eb97c994" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Sep 16 15:45:17 2019 -0700" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Sep 20 20:31:49 2019 +0000" }, "message": "Clean up the use of profile_key / dex_locations\n\nThe profile key / dex locations names were sometimes used interchangeably\ndespite not being quite the same. Make clear, through renaming, which one\nis which.\n\nBug: 139884006\nTest: m test-art-host\nChange-Id: I9c79b2f2e577b873ee890333895cc90a7891499e\n" }, { "commit": "4eb6eb40e88214fcc874d93e75660cb580cb4d58", "tree": "4d13edeab88bd6fd724388c48385b0c3cca4f3a8", "parents": [ "c971eafeff43e4e26959a6e86b62ab0a8f1a6e1c" ], "author": { "name": "Balaram Makam", "email": "b.makam@samsung.com", "time": "Tue Sep 10 09:41:29 2019 -0500" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 18 01:20:03 2019 +0000" }, "message": "[optimizing] Improve constant folding on logical and\n\nConstant fold a \u0026 ~a \u003d ~a \u0026 a \u003d 0.\n\nTest: added test to 442-checker-constant-folding\nTest: test-art-host,test-art-target\nChange-Id: Ib637c93e99ce22dd1ecd5684d05ce5ca4c9c823a\n" }, { "commit": "7f8678ec4d2abec1f540fb441be60604bec86b6e", "tree": "e36b4d32dfc47fcebadf0ee5c7e4d1e3d51412a6", "parents": [ "84e5bb990d48263849bab132d80d753495bc7204" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Aug 30 16:22:28 2019 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Sep 06 18:40:59 2019 +0000" }, "message": "Revert^2 \"Prevent overflow for AOT hotness counters\"\n\nFixed bug where sbc usage was incorrect. sbc does -1 + carry.\n\nTest: test/run-test --always-clean --runtime-option -Xcheck:jni --64 674-hotness-compiled\nTest: test/run-test --always-clean --runtime-option -Xcheck:jni 674-hotness-compiled\nBug: 139883463\n\nThis reverts commit 7ab07777b08db86dda2891f3e7ae15df8f25a599.\n\nChange-Id: I6f8ac0320592a94314386b04cdb0c7e0e6da6994\n" }, { "commit": "87fb032ee1e7ae98df26c646c450ef44e23fc805", "tree": "6754b2d2a0e38277885a691d1be6f0d796478cc7", "parents": [ "a86a5d162e6b59a32e8ea7991e6c8a157aca5a0a" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Aug 20 10:34:02 2019 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Sun Sep 01 21:08:43 2019 +0000" }, "message": "Fix JIT data dual mapping for apps.\n\nWe don\u0027t use it now, but it would be nice to make it functional.\n\nMark the read-only memory as const, and fix the compile errors.\n\nTest: test.py -b --host --jit\nBug: 119800099\nChange-Id: Ic1c45072f3c97f560e843f95fb87b95f754c6e03\n" }, { "commit": "7ab07777b08db86dda2891f3e7ae15df8f25a599", "tree": "1b0b2fa585e49e4a7913c09d67794763197c6490", "parents": [ "154445799432cb53d23cd011485132be07c39b5a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 30 08:26:59 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 30 08:57:20 2019 +0000" }, "message": "Revert \"Prevent overflow for AOT hotness counters\"\n\nThis reverts commit 79e6eb8b79be6249358b7801bc511290dacf10d0.\n\nBug: 139883463\n\nReason for revert: 674-hotness-compiled fails on target.\n\nChange-Id: I02fce74d70a4ae69dd5b4ae3924aa11728d9e16f\n" }, { "commit": "79e6eb8b79be6249358b7801bc511290dacf10d0", "tree": "1a04d214dd6223423abd442d8d9b0b61a3db2336", "parents": [ "bae88c0759d48acf29b58d960ad2665e3462dfda" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Aug 26 12:33:46 2019 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Aug 29 16:05:52 2019 +0000" }, "message": "Prevent overflow for AOT hotness counters\n\nPrevious, the addition did not have a check for overflow and might wrap\naround since the counter is only 16 bits.\n\nModified the test to exercise this.\n\nThe slowdown from fixing the overflow is 2% average on golem arm32/64.\nOverall this brings the slowdown from the counter to ~15% from ~13%.\n\nThe benchmarks that regress the most are loopy ones that I would\nconsider non-representative. Code size increases by 0.6%.\n\nBug: 139883463\nTest: test/run-test --host --64 --prebuild 674-hotness-compiled\nTest: test/run-test --host --prebuild 674-hotness-compiled\nTest: test/run-test --64 --prebuild 674-hotness-compiled\nTest: test/run-test ---prebuild 674-hotness-compiled\n\nChange-Id: Icf0ab2aedbc40ab10c9d952ce0f9c7b5e5feaf15\n" }, { "commit": "9ac8e4327bd732e4b3b9b8dc6a29560013338d21", "tree": "b56840a0c7b0874f73e5db7259861c04f87df796", "parents": [ "29e740fe64a8caeb04e0d686b4d1e290ba5ad1e6" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Aug 13 13:16:13 2019 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Aug 22 20:00:55 2019 +0000" }, "message": "JIT mini-debug-info: Allocate entries in the JIT data space.\n\nTest: test.py -b --host --jit\nTest: device boots\nBug: 119800099\nChange-Id: I7efa1e6e6660239cbd6438b829e08dd9cd079343\n" }, { "commit": "8fc2f95291206806599d4f2a50da529da85155b6", "tree": "c3c9de9a9a925d6ab790f6db466d1f9c17ed1010", "parents": [ "9ce340f829f836560278ecd078fbefcf19c9d629" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Jul 31 18:40:09 2019 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Aug 16 09:10:55 2019 +0000" }, "message": "JIT mini-debug-info: Remove global maps.\n\nKeep the extra bookkeeping information in JITCodeEntry.\n\nAlso do the compression eagerly during GC rather then lazily.\n\nTest: test.py -b --host --jit\nBug: 119800099\nChange-Id: Ie6cc682033a32c01d4c2cac242d8a4201116f940\n" }, { "commit": "9ce340f829f836560278ecd078fbefcf19c9d629", "tree": "3327d6d7dd3c0ff86861cdab67791ee7c8dbe3b8", "parents": [ "d4fc62c66328c0944348a314e3770b4f2b8006ce" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Tue Jan 22 17:46:09 2019 +0000" }, "committer": { "name": "Hans Boehm", "email": "hboehm@google.com", "time": "Thu Aug 15 20:35:11 2019 +0000" }, "message": "ARM64: toFloat() intrinsics with ARMv8 FP16.\n\nThis CL intrinsifies toFloat() method with ARMv8.2 FP16 instructions.\n\nThis CL depends on the android framework and libcore changes:\nmoving FP16 implementations into libcore.\n\nTested with local micro benchmark on Pixel 3, compared to original\nandroid.util.Half.toFloat() Java implementation, this intrinsic is\n50% faster.\n\nIn real-life case, the FP16 toFloat() intrinsic can help\naccelerate ColorLong ARGB decoding in Android framework.\n\nThis intrinsic implementation archieves bit-level compatibility with the\noriginal Java implementation android.util.Half.toFloat().\n\nTest: 580-fp16\nTest: art/test/testrunner/run_build_test_target.py -j80 art-test-javac\nTest: test-art-host, test-art-target\n\nChange-Id: I059c69747067b84f2c532465e32a1dcd3c25269f\n" } ], "next": "be53085e183be3edafdf03cac58624c87383e7e9" }