)]}' { "log": [ { "commit": "aaac0e3cbfe72217cad204d0122f2b73a602d2dd", "tree": "d148274452b3a409c9d6b8ef749c34185375d2ea", "parents": [ "7dca45b9677c16a54347cdc0d08bfa2bdd94b464" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Aug 07 00:52:22 2018 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Sep 25 14:47:48 2018 +0100" }, "message": "ART: ARM64: Support DotProd SIMD idiom.\n\nImplement support for vectorization idiom which performs dot\nproduct of two vectors and adds the result to wider precision\ncomponents in the accumulator.\n\nviz. DOT_PRODUCT([ a1, .. , am], [ x1, .. , xn ], [ y1, .. , yn ]) \u003d\n [ a1 + sum(xi * yi), .. , am + sum(xj * yj) ],\n for m \u003c\u003d n, non-overlapping sums,\n for either both signed or both unsigned operands x, y.\n\nThe patch shows up to 7x performance improvement on a micro\nbenchmark on Cortex-A57.\n\nTest: 684-checker-simd-dotprod.\nTest: test-art-host, test-art-target.\n\nChange-Id: Ibab0d51f537fdecd1d84033197be3ebf5ec4e455\n" }, { "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403", "tree": "0fbce767bc383358cf4cd65aafc74140e1850982", "parents": [ "19379b58bd433da91230e4fe6cd96e7416d16adc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 24 16:58:47 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 28 11:06:07 2018 +0100" }, "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n" }, { "commit": "18ba1dacaaf426cbeb3c0aff6db9c58a752f9a96", "tree": "e6d82d3b8856137a1b09a2843ea88165d97afbfe", "parents": [ "0e32908d0ee4be5905cdd409dd3c45331fc98465" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed May 16 19:06:32 2018 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 04 13:12:18 2018 +0100" }, "message": "ART: Implement loop full unrolling.\n\nPerforms whole loop unrolling for small loops with small\ntrip count to eliminate the loop check overhead, to have\nmore opportunities for inter-iteration optimizations.\n\ncaffeinemark/FloatAtom: 1.2x performance on arm64 Cortex-A57.\n\nTest: 530-checker-peel-unroll.\nTest: test-art-host, test-art-target.\nChange-Id: Idf3fe3cb611376935d176c60db8c49907222e28a\n" }, { "commit": "0e32908d0ee4be5905cdd409dd3c45331fc98465", "tree": "592ffd19b21379b0815345302b04911932fa90f9", "parents": [ "b5271dd44a30f498689e503340d3c8d01bf31f07" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Jun 12 10:23:27 2018 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 04 13:12:13 2018 +0100" }, "message": "ART: Refactor scalar loop optimizations.\n\nRefactor scalar loop peeling and unrolling to eliminate repeated\nchecks and graph traversals, to make the code more readable and\nto make it easier to add new scalar loop opts.\n\nThis is a prerequisite for full unrolling patch.\n\nTest: 530-checker-peel-unroll.\nTest: test-art-target, test-art-host.\nChange-Id: If824a95f304033555085eefac7524e59ed540322\n" }, { "commit": "a043111e3a2c09b549708a6227a1f54d91da76aa", "tree": "393fe11cfceccebf474e4bdf36ff79b70b97f589", "parents": [ "213ee2da6a1c58d0fc12c937bbd9c9974ca00aca" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 09:32:54 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 18:43:19 2018 +0100" }, "message": "Move instruction_set_ to CompilerOptions.\n\nRemoves CompilerDriver dependency from ImageWriter and\nseveral other classes.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing\nChange-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465\n" }, { "commit": "cf43fb6a1e676cc6bbc04c6591640f18643b1839", "tree": "2573ba1024307763c54df655333f1e2477d0ea82", "parents": [ "9076eb66ad173933d7fbd5ce328d31c7f97fd202" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Feb 15 14:43:48 2018 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue May 15 19:33:45 2018 +0100" }, "message": "ART: Enable scalar loop peeling and unrolling.\n\nTurn on scalar loop peeling and unrolling by default.\n\nTest: 482-checker-loop-back-edge-use, 530-checker-peel-unroll\nTest: test-art-host, test-art-target, boot-to-gui\nChange-Id: Ibfe1b54f790a97b281e85396da2985e0f22c2834\n" }, { "commit": "3f08e9bb0dfbe9a51e1b378ae20a9338358349eb", "tree": "315a297945abd28e1f6375095c065ab40691fdde", "parents": [ "cf659ae8b91e4ea84ffb4adb294eac5759d6666f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue May 01 13:42:03 2018 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue May 01 14:14:53 2018 -0700" }, "message": "Remove some SIMD recognition code.\n\nTest: : test-art-host,target\n\nChange-Id: I7f00315c61ed99723236283bc39a4c7fb279df47\n" }, { "commit": "2477320a8d9de58ede68e2645ea53c10f71dcd57", "tree": "f428a6856e10d8ebaff0bb2da544a8d41c35ab77", "parents": [ "5a87e19e4bf1b6719c2aad3effde1b38d2c3085c" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Apr 26 10:28:51 2018 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Apr 26 10:28:51 2018 -0700" }, "message": "Step 1 of 2: conditional passes.\n\nRationale:\nThe change adds a return value to Run() in preparation of\nconditional pass execution. The value returned by Run() is\nbest effort, returning false means no optimizations were\napplied or no useful information was obtained. I filled\nin a few cases with more exact information, others\nstill just return true. In addition, it integrates inlining\nas a regular pass, avoiding the ugly \"break\" into\noptimizations1 and optimziations2.\n\nBug: b/78171933, b/74026074\n\nTest: test-art-host,target\nChange-Id: Ia39c5c83c01dcd79841e4b623917d61c754cf075\n" }, { "commit": "72411e6b3b286d91e4da894cd5b12e7a3dc88f40", "tree": "9bffb94a66fb5df1df05a53afa367406d069c773", "parents": [ "ddc694267aee845c9b61779be2a5487eb65b1757" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 19 16:18:07 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Apr 17 16:09:05 2018 +0100" }, "message": "ART: Implement scalar loop peeling.\n\nImplement scalar loop peeling for invariant exits elimination\n(on arm64). If the loop exit condition is loop invariant then\nloop peeling + GVN + DCE can eliminate this exit in the loop\nbody. Note: GVN and DCE aren\u0027t applied during loop optimizations.\n\nNote: this functionality is turned off by default now.\n\nTest: test-art-host, test-art-target, boot-to-gui.\n\nChange-Id: I98d20054a431838b452dc06bd25c075eb445960c\n" }, { "commit": "121f2038e9c8afe12f8f4096b7c84a167e7adea5", "tree": "655e2bba77ac34208c54b290286104b124003e59", "parents": [ "f9635aab3f2db9b1b13184e8146530a53246b82c" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Oct 23 19:19:06 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Mar 26 19:46:23 2018 +0100" }, "message": "ART: Implement scalar loop unrolling.\n\nImplement scalar loop unrolling for small loops\n(on arm64) with known trip count to reduce loop check\nand branch penalty and to provide more opportunities\nfor instruction scheduling.\n\nNote: this functionality is turned off by default now.\n\nTest: cloner_test.cc\nTest: test-art-target, test-art-host\n\nChange-Id: Ic27fd8fb0bc0d7b69251252da37b8b510bc30acc\n" }, { "commit": "29aa08219ff72409e9f10ae2a5da4e6e604baad1", "tree": "2ccde97263f82b6a2f1a83d5b674f46c412c2909", "parents": [ "8e68c6c85ad188e306cd66f8b620350f996fe242" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Mar 08 11:28:00 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Mar 15 09:49:18 2018 -0700" }, "message": "Vectorization of saturation arithmetic.\n\nRationale:\nBecause faster is better.\n\nBug: b/74026074\n\nTest: test-art-host,target\n\nChange-Id: Ifa970a62cef1c0b8bb1c593f629d8c724f1ffe0e\n" }, { "commit": "2ca10eb3f47ef3c2535c137853f7a63d10bb908b", "tree": "3684d1d5ef4791795b64620e97f952896c5a2011", "parents": [ "02f41015a0933f146b886c62bb5b02c322ddf882" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Nov 15 15:17:53 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Nov 20 10:38:26 2017 -0800" }, "message": "Refactored optimization passes setup.\n\nRationale:\nRefactors the way we set up optimization passes\nin the compiler into a more centralized approach.\nThe refactoring also found some \"holes\" in the\nexisting mechanism (missing string lookup in\nthe debugging mechanism, or inablity to set\nalternative name for optimizations that may repeat).\n\nBug: 64538565\n\nTest: test-art-host test-art-target\nChange-Id: Ie5e0b70f67ac5acc706db91f64612dff0e561f83\n" }, { "commit": "38a3f21959d5c68d3034d4d3cef0cc231ebce78a", "tree": "fae9ab2b683bd2494a1480c7453e1beeace0e836", "parents": [ "df12b6fbd98883cc1714f731847b7628f2fb7f11" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Oct 20 17:02:21 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Oct 27 10:50:36 2017 -0700" }, "message": "Alignment optimizations in vectorizer.\n\nRationale:\nSince aligned data access is generally better (enables more efficient\naligned moves and prevents nasty cache line splits), computing and/or\nenforcing alignment has been added to the vectorizer:\n\n (1) If the initial alignment is known completely and suffices,\n then a static peeling factor enforces proper alignment.\n (2) If (1) fails, but the base alignment allows, dynamically peeling\n until total offset is aligned forces proper aligned access patterns.\n\nBy using ART conventions only, any forced alignment is preserved\nover suspends checks where data may move.\n\nNote 1:\nCurrent allocation convention is just 8 byte alignment on arrays/strings,\nso only ARM32 benefits. However, all optimizations are implemented in\na general way, so moving to a 16 byte alignment will immediately\ntake advantage of any new convention!!\n\nNote 2:\nThis CL also exposes how bad the choice of 12 byte offset of arrays\nreally is. Even though the new optimizations fix the misaligned, it\nrequires peeling for the most common case: 0 indexed loops. Therefore,\nwe may even consider moving to a 16 byte offset. Again the optimizations\nin this CL will immediately take advantage of that new convention!!\n\nTest: test-art-host test-art-target\n\nChange-Id: Ib6cc0fb68c9433d3771bee573603e64a3a9423ee\n" }, { "commit": "6e9b137f0439b3ceedb8114bd93fa9fb746e42fa", "tree": "1fc138f4f0727fe4e78141fb2979c665d1fe157b", "parents": [ "4c3682649ebcaef4ab237f523f8e39ebd65e4f8d" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 05 16:48:30 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 12 18:04:48 2017 +0100" }, "message": "ARM: Support SIMD reduction for 32-bit backend.\n\nSupport SIMD reduction (add, min, max) and SAD (for int-\u003eint only)\nidioms for arm (32-bit) backend.\n\nTest: test-art-target, test-art-host\nTest: 661-checker-simd-reduc, 660-checker-simd-sad-int\n\nChange-Id: Ic6121f5d781a9bcedc33041b6c4ecafad9b0420a\n" }, { "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1", "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07", "parents": [ "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 14:49:14 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 06 17:53:50 2017 +0100" }, "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n" }, { "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32", "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af", "parents": [ "e1e347dace0ded83774999bb26c37527dcdb1d5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 22:50:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 25 15:45:01 2017 +0100" }, "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n" }, { "commit": "dbbac8f812a866b1b53f3007721f66038d208549", "tree": "05cecd927afccd33fc1c14b39ada47e86873f560", "parents": [ "2406bf17998e15bd40677a907beb3e9c41facce4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Sep 01 13:06:08 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Sep 21 10:20:55 2017 -0700" }, "message": "Implement Sum-of-Abs-Differences idiom recognition.\n\nRationale:\nCurrently just on ARM64 (x86 lacks proper support),\nusing the SAD idiom yields great speedup on loops\nthat compute the sum-of-abs-difference operation.\nAlso includes some refinements around type conversions.\n\nSpeedup ExoPlayerAudio (golem run):\n1.3x on ARM64\n1.1x on x86\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: Ia2b711d2bc23609a2ed50493dfe6719eedfe0130\n" }, { "commit": "b92cc33a7a6a827da577627dc274440ac29652a8", "tree": "9fbc71433d4ea89be61aec6de0d33d142c11f039", "parents": [ "f56311a966a9e8e476287cd47d615a91a83c1d04" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Sep 06 15:53:17 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Sep 06 15:53:17 2017 -0700" }, "message": "Pass stats into the loop optimization phase.\n\nTest: market scan.\nChange-Id: I58b23b8d254883f30619ea3602d34bf93618d432\n" }, { "commit": "0148de41a5c77c2f61252c219f1a02413c7c4a32", "tree": "91736a82a7e98721a44879b6597b5aea386e8e3b", "parents": [ "c101222c854a0c476f5b6ae64e20adbd38126a3c" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Sep 05 09:25:01 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Sep 05 10:20:09 2017 -0700" }, "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is a revert of Icb5d6c805516db0a1d911c3ede9a246ccef89a22\nand thus a revert^2 of I2454778dd0ef1da915c178c7274e1cf33e271d0f\nand thus a revert^3 of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\nand thus a revert^4 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\n\nPS1-2 shows what needed to change\n\nTest: test-art-host test-art-target\n\nBug: 64091002\nChange-Id: I647889e0da0959ca405b70081b79c7d3c9bcb2e9\n" }, { "commit": "982334cef17d47ef2477d88a97203a9587a4b86f", "tree": "7e65d03a4533f21286cf68e66696bd0a7a54ef54", "parents": [ "cfa59b49cde265dc5329a7e6956445f9f7a75f15" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Sep 02 12:54:16 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Sep 02 12:54:16 2017 +0000" }, "message": "Revert \"Basic SIMD reduction support.\"\n\nFails 530-checker-lse on arm64.\n\nBug: 64091002, 65212948\n\nThis reverts commit cfa59b49cde265dc5329a7e6956445f9f7a75f15.\n\nChange-Id: Icb5d6c805516db0a1d911c3ede9a246ccef89a22\n" }, { "commit": "cfa59b49cde265dc5329a7e6956445f9f7a75f15", "tree": "eed953f62e796f7e64252520a40d7e77d1f117af", "parents": [ "82a63734d3067ea0c96f8ba15bc40caaf798c625" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 31 09:08:13 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Sep 01 10:32:50 2017 -0700" }, "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is a revert^2 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\nand thus a revert of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n\nPS1-2 shows what needed to change, with regression tests\n\nTest: test-art-host test-art-target\n\nBug: 64091002, 65212948\nChange-Id: I2454778dd0ef1da915c178c7274e1cf33e271d0f\n" }, { "commit": "a57b4ee7b15ce6abfb5fa88c8dc8a516fe40e0d9", "tree": "c7ed7e8cb7439a8e689e399e34559aa46a97cdbd", "parents": [ "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Aug 30 21:21:41 2017 +0000" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Aug 30 21:21:41 2017 +0000" }, "message": "Revert \"Basic SIMD reduction support.\"\n\nThis reverts commit 9879d0eac8fe2aae19ca6a4a2a83222d6383afc2.\n\nGetting these type check failures in some builds. Need time to look at this better, so reverting for now :-(\n\n\ndex2oatd F 08-30 21:14:29 210122 226218 \ncode_generator.cc:115] Check failed: CheckType(instruction-\u003eGetType(), locations-\u003eInAt(0)) PrimDouble C\n\nChange-Id: I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n" }, { "commit": "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2", "tree": "c75ab69be15630f86824bb202577eaa1ff91c4ee", "parents": [ "60f734443d54d48fad86dce6d80d8cef22a134d0" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Aug 15 10:51:25 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Aug 30 09:10:40 2017 -0700" }, "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: I7880c135aee3ed0a39da9ae5b468cbf80e613766\n" }, { "commit": "b29f684b74216e8d652c48ab9f86cc7d1b327e54", "tree": "393839a3b0e3d3aa0fde20beaef846303ce098c7", "parents": [ "bf3710ecec95b2716d1c706b5661192dd9ea6c66" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jul 28 15:58:41 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Aug 08 11:11:00 2017 -0700" }, "message": "Set basic framework for detecting reductions.\n\nRationale:\nRecognize reductions in loops. Note that reductions are *not*\noptimized yet (we would proceed with e.g. unrolling and vectorization).\nThis CL merely sets up the basic detection framework. Also does\na bit of cleanup on loop optimization code.\n\nBug: 64091002\nTest: test-art-host\n\nChange-Id: I0f52bd7ca69936315b03d02e83da743b8ad0ae72\n" }, { "commit": "14a68b4aa9620e4fd58907255b049fb5c18bd1ec", "tree": "692319b6a9344d84a2e8916c388be954d8878c41", "parents": [ "afdcd847498abc0f4e295bece443afabf8aaf868" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jun 08 14:06:58 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jun 27 11:29:07 2017 -0700" }, "message": "Unrolling and dynamic loop peeling framework in vectorizer.\n\nRationale:\nThis CL introduces the basic framework for dynamically peeling\n(to obtain aligned access) and unrolling the vector loop (to reduce\nlooping overhead and allow more target specific optimizations\non e.g. SIMD loads and stores).\n\nNOTE:\nThe current heuristics are \"bogus\" and merely meant to exercise\nthe new framework. This CL focuses on introducing correct code for\nthe vectorizer. Heuristics and the memory computations for alignment\nare to be implemented later.\n\nTest: test-art-target, test-art-host\n\nChange-Id: I010af1475f42f92fd1daa6a967d7a85922beace8\n" }, { "commit": "1a0a519c82044ec3e6d3910ff0602b11292de47a", "tree": "342691a82a58ddb0660b9111622b2ff67d92f898", "parents": [ "8979f71079ec18fa8d3c0915549ec03ee1fbadf5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 22 11:56:01 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 22 12:09:16 2017 +0100" }, "message": "Fix loop optimization in the presence of environment uses.\n\nWe should not remove instructions that have deoptimize as\nusers, or that have environment uses in a debuggable setup.\n\nbug: 62536525\nbug: 33775412\nTest: 656-loop-deopt\nChange-Id: Iaec1a0b6e90c6a0169f18c6985f00fd8baf2dece\n" }, { "commit": "19680d3655433e98582983ed0a6d44d6b4822951", "tree": "15113506e75b1480c5c1d3cfdf9df4480f30eae8", "parents": [ "0a5ace58e973da278049f837bf2cdbaf7b44849c" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu May 11 10:38:36 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon May 29 17:57:39 2017 +0200" }, "message": "MIPS64: ART Vectorizer\n\nMIPS64 implementation which uses MSA extension. Also extended all\nrelevant checker tests to test MIPS64 implementation.\n\nTest: booted MIPS64R6 in QEMU\nTest: ./testrunner.py --target --optimizing -j1 in QEMU\n\nChange-Id: I8b8a2f601076bca1925e21213db8ed1d41d79b52\n" }, { "commit": "304c8a5dfe92d5677e9561270b19313d3e450c59", "tree": "a5345d8d3467dde5f509dcc5dd0b3b170b021e60", "parents": [ "14538fb50832ac20445af5a92003bc250f486c22" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue May 23 11:01:13 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed May 24 15:56:14 2017 +0000" }, "message": "Support for narrow operands in \"dangerous\" operations.\n\nThis is a revert^2 of commit 636e870d55c1739e2318c2180fac349683dbfa97.\n\nRationale:\nUnder strict conditions, even operations that are sensitive\nto higher order bits can vectorize by inspecting the operands\ncarefully. This enables more vectorization, as demonstrated\nby the removal of quite a few TODOs.\n\nTest: test-art-target, test-art-host\nChange-Id: Ic2684f771d2e36df10432286198533284acaf472\n" }, { "commit": "9231690d586ecf45d5d9481bc5df5a5ad2628c89", "tree": "d48bf8b22461f6488821be6117ff2da4cc176093", "parents": [ "636e870d55c1739e2318c2180fac349683dbfa97" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 23 08:06:07 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 23 08:06:07 2017 +0000" }, "message": "Revert \"Support for narrow operands in \"dangerous\" operations.\"\n\nFails on armv8 / speed-profile\n\nThis reverts commit 636e870d55c1739e2318c2180fac349683dbfa97.\n\nChange-Id: Ib2a09b3adeba994c6b095672a1e08b32d3871872\n" }, { "commit": "636e870d55c1739e2318c2180fac349683dbfa97", "tree": "6c726b0b918e26aba5b5f9ec1bc900045ef2c3e3", "parents": [ "de31d084f7d64c94911aef927798559d39759f95" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu May 18 14:45:27 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu May 18 17:18:24 2017 -0700" }, "message": "Support for narrow operands in \"dangerous\" operations.\n\nRationale:\nUnder strict conditions, even operations that are sensitive\nto higher order bits can vectorize by inspecting the operands\ncarefully. This enables more vectorization, as demonstrated\nby the removal of quite a few TODOs.\n\nTest: test-art-target, test-art-host\nChange-Id: I2b0fda6a182da9aed9ce1708a53eaf0b7e1c9146\n" }, { "commit": "c8e93c736c149ce41be073dd24324fb08afb9ae4", "tree": "8e7154cf1bbcee8f5837ee9cb930174e2516ac03", "parents": [ "92f4672f811a4eccdc596f7c2235804abd196fde" ], "author": { "name": "Aart Bik", "email": "ajcbik@ajcbik2.mtv.corp.google.com", "time": "Wed May 10 10:49:22 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon May 15 11:44:58 2017 -0700" }, "message": "Min/max SIMDization support.\n\nRationale:\nThe more vectorized, the better!\n\nTest: test-art-target, test-art-host\n\nChange-Id: I758becca5beaa5b97fab2ab70f2e00cb53458703\n" }, { "commit": "f3e61ee363fe7f82ef56704f06d753e2034a67dd", "tree": "a00f1fce4a2e284b0a03f941f530afc5b5c56b59", "parents": [ "741a81af441cbcb7255229bf250bc009d2894e92" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Apr 12 17:09:20 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Apr 19 10:30:57 2017 -0700" }, "message": "Implement halving add idiom (with checker tests).\n\nRationale:\nFirst of several idioms that map to very efficient SIMD instructions.\nNote that the is-zero-ext and is-sign-ext are general-purpose utilities\nthat will be widely used in the vectorizer to detect low precision\nidioms, so expect that code to be shared with many CLs to come.\n\nTest: test-art-host, test-art-target\nChange-Id: If7dc2926c72a2e4b5cea15c44ef68cf5503e9be9\n" }, { "commit": "6daebeba6ceab4e7dff5a3d65929eeac9a334004", "tree": "6aa2948896c6a731531451840a9a8bb26854cdd8", "parents": [ "7cd18fb5a7ce83d98b1bbc3c55583fc5f93dc16f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Apr 03 14:35:41 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Apr 05 09:24:01 2017 -0700" }, "message": "Implemented ABS vectorization.\n\nRationale:\nThis CL adds the concept of vectorizing intrinsics\nto the ART vectorizer. More can follow (MIN, MAX, etc).\n\nTest: test-art-host, test-art-target (angler)\nChange-Id: Ieed8aa83ec64c1250ac0578570249cce338b5d36\n" }, { "commit": "f8f5a16ed7bad1e18179e38453e59c96a944de10", "tree": "53369083a97103563467cc5910a439a1864dd0b1", "parents": [ "7298b1ae3e9af5fdb46d168302a26cfbf5d475f5" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 06 15:35:29 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Mar 31 10:58:11 2017 -0700" }, "message": "ART vectorizer.\n\nRationale:\nMake SIMD great again with a retargetable and easily extendable vectorizer.\n\nProvides a full x86/x86_64 and a proof-of-concept ARM implementation. Sample\nimprovement (without any perf tuning yet) for Linpack on x86 is about 20% to 50%.\n\nTest: test-art-host, test-art-target (angler)\nBug: 34083438, 30933338\n\nChange-Id: Ifb77a0f25f690a87cd65bf3d5e9f6be7ea71d6c1\n" }, { "commit": "92685a8a56fba7191612cf210f9c667b5ceda2af", "tree": "563009abe4387cb83c63320504148cedfc764bc3", "parents": [ "5c90d0b0f332436f7ca5c028256bf5e91e9023d4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Mar 06 11:13:43 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Mar 06 15:20:04 2017 -0800" }, "message": "Pass driver to loop opt. Add new side_effects phase.\n\nRationale:\nBreak-out CL of ART Vectorizer: number 3.\nThe purpose is making the original CL smaller\nand easier to review.\n\nBug: 34083438\nTest: test-art-host\nChange-Id: I7cece807ee4f5fcaeae41f1deed33ac263447b77\n" }, { "commit": "6b69e0acb0e4c506ce2587e362c38e36e41e34ab", "tree": "976f08c78d3c5efa2dac8ec0409f36fae51456cb", "parents": [ "93939824c7e6e16cf98941cd4724278e87d6259d" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 11 10:20:43 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 13 10:04:42 2017 -0800" }, "message": "Complete unrolling of loops with small body and trip count one.\n\nRationale:\nAvoids the unnecessary loop control overhead, suspend check,\nand exposes more opportunities for constant folding in the\nresulting loop body. Fully unrolls loop in execute() of\nthe Dhrystone benchmark (3% to 8% improvements).\n\nTest: test-art-host\n\nChange-Id: If30f38caea9e9f87a929df041dfb7ed1c227aba3\n" }, { "commit": "df7822ecf033cecf48d950f3ae34f7043c8df738", "tree": "f392a69377e1e281bcd85d811b656c6d14280ab4", "parents": [ "6746874b84a44ab8dff18457eec546a1ebb22e93" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Dec 06 10:05:30 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Dec 09 08:42:18 2016 -0800" }, "message": "Added polynomial induction variables analysis. With tests.\n\nRationale:\nInformation on polynomial sequences is nice to further enhance\nBCE and last-value assignment. In this case, this CL enables more\nloop optimizations for benchpress\u0027 Sum (80 x speedup). Also\nchanged rem-based geometric induction to wrap-around induction.\n\nTest: test-art-host\n\nChange-Id: Ie4d2659edefb814edda2c971c1f70ba400c31111\n" }, { "commit": "807868eac75a39e79ee6309ed4cbe038407efa29", "tree": "74d9953120599bde842895ab4e7ed33fefb0fa13", "parents": [ "3387b2a9e6ca4e7015c4182eee2f70a746972ca2" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Nov 03 17:51:43 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Nov 04 08:14:23 2016 -0700" }, "message": "Account for early exit loop.\n\nRationale:\nlast value computation is obviously only right if\nthe loop does not have early exits; only needed\nif cycle leaks to outside loop in any way.\n\nBug:32633772\nTest: 623-checker-loop-regressions\nChange-Id: Id60beca4704491cff611ad12a24bfc63c09d32c3\n" }, { "commit": "cc42be074ed15235426cdbcb34f357ead2be2caf", "tree": "d0ac4dca432e1bb26e21634f21ffc3e05db5020e", "parents": [ "a8188191477b7b5b01a3c4426c51c48cd55f6678" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Oct 20 16:14:16 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Oct 24 12:55:48 2016 -0700" }, "message": "Improved induction variable analysis and loop optimizations.\n\nRationale:\nRather than half-baked reconstructing cycles during loop optimizations,\nthis CL passes the SCC computed during induction variable analysis\nto the loop optimizer (trading some memory for more optimizations).\nThis further improves CaffeineLogic from 6000us down to 4200us (dx)\nand 2200us to 1690us (jack). Note that this is on top of prior\nimprovements in previous CLs. Also, some narrowing type concerns\nare taken care of during transfer operations.\n\nTest: test-art-host\nChange-Id: Ice2764811a70073c5014b3a05fb51f39fd2f4c3c\n" }, { "commit": "9abf894ad0e5a6a1594ee1fa3924965e25e5f86f", "tree": "5080bd832d4f2234897404195b5d9865f950f47c", "parents": [ "6e5fa09510c7280168e040382d27dd8b55760d9a" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Oct 14 09:49:42 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Oct 18 09:02:47 2016 -0700" }, "message": "Enable last value generation of periodic sequence.\n\nRationale:\nThis helps to eliminate more dead induction. For example,\nCaffeineLogic when compiled with latest Jack improves with\na 1.3 speedup (2900us -\u003e 2200us) due to eliminating first\nloop (second loop can be removed also, but for a later\ncase). The currently benchmarks.dex has a different construct\nfor the periodics, however, still to be recognized.\n\nTest: test-art-host\nChange-Id: Ia81649a207a2b1f03ead0855436862ed4e4f45e0\n" }, { "commit": "482095d3a03892b76f5b835c9e7ea4bc80638501", "tree": "642cb6b52f68e4e6d03475e80dc2845c5e4f50f6", "parents": [ "0d7398fd5407938aba75c50bd323af27e83ccb9f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Oct 10 15:39:10 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Oct 11 10:39:42 2016 -0700" }, "message": "Improved and simplified loop optimizations.\n\nRationale:\nEmpty preheader simplification has been simplified\nto a much more general empty block removal optimization\nstep. Incremental updating of induction variable\nanalysis enables repeated elimination or simplification\nof induction cycles.\n\nThis enabled an extra layer of optimization for\ne.g. Benchpress Loop (17.5us. -\u003e 0.24us. -\u003e 0.08us).\nSo the original 73x speedup is now multiplied\nby another 3x, for a total of about 218x.\n\nTest: 618-checker-induction et al.\nChange-Id: I394699981481cdd5357e0531bce88cd48bd32879\n" }, { "commit": "8c4a8542ff5f899f430a65feaa114d6288077224", "tree": "8582d2cbab0dcab323b984caa164f4c3bc65613d", "parents": [ "78c6fefdb9008cb6dc9f0014d4616b457009c6c8" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Oct 06 11:36:57 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Oct 07 08:16:16 2016 -0700" }, "message": "Improved and simplified loop optimizations.\n\nRationale:\nThis CL merges some common cases into one, thereby simplifying\nthe code quite a bit. It also prepares for more general induction\ncycles (rather than the simple phi-add currently used). Finally,\nit generalizes the closed form elimination with empty loops.\nAs a result of the latter, elaborate but weird code like:\n\n private static int waterFall() {\n int i \u003d 0;\n for (; i \u003c 10; i++);\n for (; i \u003c 20; i++);\n for (; i \u003c 30; i++);\n for (; i \u003c 40; i++);\n for (; i \u003c 50; i++);\n return i;\n }\n\nnow becomes just this (on x86)!\n\n mov eax, 50\n ret\n\nChange-Id: I8d22ce63ce9696918f57bb90f64d9a9303a4791d\nTest: m test-art-host\n" }, { "commit": "9620230700d4b451097c2163faa70627c9d8088a", "tree": "695b96b9efeaa4c2cb3816e51904e19540fe3883", "parents": [ "4aa6a93c46a959df1ab71ee7a68ad345338046ef" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Oct 04 17:33:56 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Oct 05 11:50:42 2016 -0700" }, "message": "Refactoring of graph linearization and linear order.\n\nRationale:\nOwnership of graph\u0027s linear order and iterators was\na bit unclear now that other phases are using it.\nNew approach allows phases to compute their own\norder, while ssa_liveness is sole owner for graph\n(since it is not mutated afterwards).\n\nAlso shortens lifetime of loop\u0027s arena.\n\nTest: test-art-host\nChange-Id: Ib7137d1203a1e0a12db49868f4117d48a4277f30\n" }, { "commit": "5ed20f90acd05e1f8697340f11113f0c61c22492", "tree": "470b26b33054a2398bdf115f6592777b1b7698bd", "parents": [ "d3a9ce9d30a59587413310e66ea51c8f7adb0a1d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 05 13:49:44 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 05 13:49:44 2016 +0100" }, "message": "Make it possible to pass an arena allocator to HLoopOptimization.\n\nloop_optimization_test uses memory from HLoopOptimization\u0027s\nallocator, which is scoped by the Run method.\n\nFix is to pass custom allocator.\n\ntest: m test-art-host-gtest\nChange-Id: I359330e22202519f400a26da5403eeb00f0b2db4\n" }, { "commit": "ebe167422f6197b9df0698bbeb944a0e4eea5f2d", "tree": "60bb0084030cadfed694261c36c5722f4f945869", "parents": [ "2a5c5160771ad528bc9b3ac36ac5785a184c956d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 05 09:55:42 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 05 09:55:42 2016 +0100" }, "message": "Properly scope HLoopOptimization\u0027s allocator.\n\nHOptimization classes do not get their destructor called,\nas they are arena objects. So the scope for the optimization\nallocator needs to be the Run method.\n\nAlso anticipate bisection search breakage by adding\nHLoopOptimization to the list of recognized optimizations.\n\nChange-Id: I7770989c39d5700a3b6b0a20af5d4b874dfde111\n" }, { "commit": "281c681a0852c10f5ca99b351650b244e878aea3", "tree": "33036cbfb76ee497eedf60e0e5785a2267c9dd02", "parents": [ "a845d07bbd57f8beaea8b4fb47192a3382ef25b2" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Aug 26 11:31:48 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Oct 03 15:15:27 2016 -0700" }, "message": "A first implementation of a loop optimization framework.\n\nRationale:\nWe are planning to add more and more loop related optimizations\nand this framework provides the basis to do so. For starters,\nthe framework optimizes dead induction, induction that can be\nreplaced with a simpler closed-form, and eliminates dead loops\ncompletely (either pre-existing or as a result of induction\nremoval).\n\nSpeedup on e.g. Benchpress Loop is 73x (17.5us. -\u003e 0.24us.)\n[with the potential for more exploiting outer loop too]\n\nTest: 618-checker-induction et al.\n\nChange-Id: If80a809acf943539bf6726b0030dcabd50c9babc\n" } ] }