)]}'
{
  "log": [
    {
      "commit": "69aa60163989c33a008115205d39732a76ecc1dc",
      "tree": "058392dc104a8e7b3594a548239dca2d3ec06cce",
      "parents": [
        "aa77f6e5839b2ad3bf8ca2c06a44ec92e2667af1"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 10:34:25 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 16:01:49 2015 +0100"
      },
      "message": "Revert \"Revert \"Pass current method to HNewInstance and HNewArray.\"\"\n\nProblem exposed by this change was fixed in:\nhttps://android-review.googlesource.com/#/c/154031/\n\nThis reverts commit 7b0e353b49ac3f464c662f20e20e240f0231afff.\n\nChange-Id: I680c13dc9db9ba223ab11c7af255222860b4e6d2\n"
    },
    {
      "commit": "7b0e353b49ac3f464c662f20e20e240f0231afff",
      "tree": "b5c936df891b08521176065ccaddb1f9e27c9f46",
      "parents": [
        "e21aa42e1341d34250742abafdd83311ad9fa737"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 09:25:50 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 09:25:50 2015 +0000"
      },
      "message": "Revert \"Pass current method to HNewInstance and HNewArray.\"\n\n082-inline-execute fails on x86.\n\nThis reverts commit e21aa42e1341d34250742abafdd83311ad9fa737.\n\nChange-Id: Ib3fd25faee2e0128001e40d3d51a74f959bc4449\n"
    },
    {
      "commit": "e21aa42e1341d34250742abafdd83311ad9fa737",
      "tree": "d2c9f8530e59876588d32f04b4effc25ebc0fa89",
      "parents": [
        "c47908e8c32fd58bc4dc75998a80f706954db1dc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 08 15:35:07 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 08 15:36:27 2015 +0100"
      },
      "message": "Pass current method to HNewInstance and HNewArray.\n\nAlso remove unsed CodeGenerator::LoadCurrentMethod.\n\nChange-Id: I4b8d3f2a30b8e2c76b6b329a72555483c993cb73\n"
    },
    {
      "commit": "38207af82afb6f99c687f64b15601ed20d82220a",
      "tree": "f9360949b92e5b6b01c5828c03ac67d01adffe1d",
      "parents": [
        "6a0d5e7fe6dc0c9d3dd941ab991203f2d5d1c354"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 01 15:46:22 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 04 14:39:06 2015 +0100"
      },
      "message": "Use HCurrentMethod in HInvokeStaticOrDirect.\n\nChange-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66\n"
    },
    {
      "commit": "fd88f16100cceafbfde1b4f095f17e89444d6fa8",
      "tree": "fdb6d0520ca419acef9e953e74dcbd7d908bc4dd",
      "parents": [
        "1aebdae18678403bdac078cbbe1f7dd4243c44f3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 03 11:23:52 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 03 11:23:52 2015 +0100"
      },
      "message": "Factorize code for common LocationSummary of HInvoke.\n\nThis is one step forward, we could factorize more, but\nI wanted to get this out of the way first.\n\nChange-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85\n"
    },
    {
      "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33",
      "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5",
      "parents": [
        "2006b7b9b8e32722bd0d640c62549d8a0ac624b6"
      ],
      "author": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Wed Apr 22 13:56:20 2015 -0700"
      },
      "committer": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Fri May 29 18:45:49 2015 -0700"
      },
      "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n"
    },
    {
      "commit": "9bd88b0933a372e6a7b64b850868e6a7998567e2",
      "tree": "bcd275674c1234842b757ea8e100c4030f9ac6fe",
      "parents": [
        "01cb410f4ad23135671d821ba36c269f8c82affa"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@linaro.org",
        "time": "Wed Apr 22 16:24:46 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri May 22 12:01:07 2015 +0100"
      },
      "message": "ARM64: Move xSELF from x18 to x19.\n\nThis patch moves xSELF to callee saved x19 and removes support for\nETR (external thread register), previously used across native calls.\n\nChange-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n"
    },
    {
      "commit": "48fb0b7be18a783de9cd1b246042c1ec5b732c49",
      "tree": "4b977dd414301330586dd828736dd6ff03056647",
      "parents": [
        "45970a4cde2fb12e1cb1515aaf0d9cb9869c5116",
        "07276db28d654594e0e86e9e467cad393f752e6e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue May 19 11:43:08 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue May 19 11:43:08 2015 +0000"
      },
      "message": "Merge \"Don\u0027t do a null test in MarkGCCard if the value cannot be null.\""
    },
    {
      "commit": "07276db28d654594e0e86e9e467cad393f752e6e",
      "tree": "6450e07d64045f0c0949b3423501316b672641c7",
      "parents": [
        "17f1bc531ea2f8c1a6fac3def13dee1b901949dd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 18 14:22:09 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 18 19:15:52 2015 +0100"
      },
      "message": "Don\u0027t do a null test in MarkGCCard if the value cannot be null.\n\nChange-Id: I45687f6d3505178e2fc3689eac9cb6ab1b2c1e29\n"
    },
    {
      "commit": "2f9d1379fdebcdeeac52eaeff25ad5697c6b6ffb",
      "tree": "6fe7dd64fc17928540cac48162c4b6471fc2ab6a",
      "parents": [
        "5969307a254fb731a464119506b2cef9404871b9",
        "da40309f61f98c16d7d58e4c34cc0f5eef626f93"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 18 15:25:39 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon May 18 15:25:40 2015 +0000"
      },
      "message": "Merge \"Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.\""
    },
    {
      "commit": "c66671076b12a0ee8b9d1ae782732cc91beacb73",
      "tree": "e8007c01f0bce06dcd3b0d6e2db9e7079fc4dd04",
      "parents": [
        "ef4366a159ecdd357c98e577583bbe224d065128"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri May 15 16:08:45 2015 +0800"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri May 15 16:10:29 2015 +0100"
      },
      "message": "Opt compiler: Speedup div/rem by constants on arm32 and arm64.\n\nThis patch also includes:\n1. Add java test for div/rem negative constants.\n2. Fix a thumb2 encoding issue where the last operand is\n   \"reg, shift #amount\" in some instructions.\n3. Support a simple filter in arm32 assembler test to filter out\n   unsupported cases, such as \"smull r0, r0, r1, r2\".\n4. Add smull arm32 assembler test.\n5. Add smull/umull thumb2 test.\n6. Add test for the thumb2 encoding issue which is fixed in this\n   patch.\n\nChange-Id: I1601bc9c38f70f11909f2816fe3ec105a158951e\n"
    },
    {
      "commit": "2d27c8e338af7262dbd4aaa66127bb8fa1758b86",
      "tree": "e01e0bc57359df0bdf00c3da694c5403fb7fc9e6",
      "parents": [
        "3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Apr 28 15:48:45 2015 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Apr 29 14:09:17 2015 +0100"
      },
      "message": "Refactor InvokeDexCallingConventionVisitor in Optimizing.\n\nChange-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34\n"
    },
    {
      "commit": "da40309f61f98c16d7d58e4c34cc0f5eef626f93",
      "tree": "7525c544dc9acae0e1041757149be2eabb733dc8",
      "parents": [
        "021190bf584662e75b269ef47cd48e2044e34fe4"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 24 17:35:39 2015 +0800"
      },
      "committer": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 24 17:38:13 2015 +0800"
      },
      "message": "Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.\n\nIt should be a bit faster than load/store single registers and reduce\nthe code size.\n\nChange-Id: I67b8302adf6174b7bb728f7c2afd2c237e34ffde\n"
    },
    {
      "commit": "27eac12a66a73eb38b5ccb45b62350cf341299d0",
      "tree": "7cc7eea6dd543720da2921c11f68296f5df37b07",
      "parents": [
        "e40d82ffe388458c2674ec051f1dd897362692eb",
        "ad4450e5c3ffaa9566216cc6fafbf5c11186c467"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Apr 20 15:20:15 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Apr 20 15:20:15 2015 +0000"
      },
      "message": "Merge \"Opt compiler: Implement parallel move resolver without using swap.\""
    },
    {
      "commit": "09a99965bb27649f5b1d373f76bfbec6a2500c9e",
      "tree": "a1584b26a5b6f3dee692d0b21373de27734c965f",
      "parents": [
        "2e0f89b1b61685f7c322a4c6ec3e3b4839e76d64"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Apr 15 11:47:56 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Mon Apr 20 14:45:01 2015 +0100"
      },
      "message": "Opt compiler: ARM64: Follow other archs for a few codegen stubs.\n\nCode generation for HInstanceFieldGet, HInstanceFieldSet,\nHStaticFieldGet, and HStaticFieldSet are refactored to follow the\nstructure used for other backends.\n\nChange-Id: I34a3bd17effa042238c6bf199848cbc2ec26ac5d\n"
    },
    {
      "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467",
      "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab",
      "parents": [
        "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:48:56 2015 +0800"
      },
      "committer": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:54:08 2015 +0800"
      },
      "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n"
    },
    {
      "commit": "69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d",
      "tree": "b7f99172f921d7100959ab48210097906794d043",
      "parents": [
        "e015a31e509c3f4de8a90b57b77329ba6609ce2f"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Tue Apr 14 20:04:41 2015 +0800"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Apr 14 17:29:08 2015 +0100"
      },
      "message": "ARM64: Remove suspend register.\n\nIt also clean up build/remove frame used by JNI compiler and generates\nstp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and\noptimizing compiler.\n\nChange-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d\n"
    },
    {
      "commit": "c6b4dd8980350aaf250f0185f73e9c42ec17cd57",
      "tree": "ef8d73e37abc04aecb430072a8bc463c73398fee",
      "parents": [
        "dd97393aca1a3ff2abec4dc4f78d7724300971bc"
      ],
      "author": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Tue Apr 07 20:32:43 2015 +0100"
      },
      "committer": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Thu Apr 09 16:47:50 2015 +0100"
      },
      "message": "Implement CFI for Optimizing.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2\n"
    },
    {
      "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648",
      "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b",
      "parents": [
        "a109632b240f3c9355ca95500f6f48e4478e3c51"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Apr 01 14:03:04 2015 -0700"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Apr 01 14:05:13 2015 -0700"
      },
      "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n"
    },
    {
      "commit": "82e52ce8364e3e1c644d0d3b3b4f61364bf7089a",
      "tree": "d26020cbee67645a46838c57747d2ba1533ba5d1",
      "parents": [
        "ebbb1e322d8c89e69424a543faa03402e5b63673"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Mar 26 16:50:57 2015 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Tue Mar 31 15:53:57 2015 +0100"
      },
      "message": "ARM64: Update to VIXL 1.9.\n\nUpdate VIXL\u0027s interface to VIXL 1.9.\n\nChange-Id: Iebae947539cbad65488b7195aaf01de284b71cbb\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "d75948ac93a4a317feaf136cae78823071234ba5",
      "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d",
      "parents": [
        "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 27 09:53:16 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 27 12:01:40 2015 +0000"
      },
      "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n"
    },
    {
      "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430",
      "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0",
      "parents": [
        "e295e6ec5beaea31be5d7d3c996cd8cfa2053129"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Mar 24 02:39:46 2015 +0000"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Mar 24 02:39:46 2015 +0000"
      },
      "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n"
    },
    {
      "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129",
      "tree": "4d8a657d23d511743ce35bee596544d7f652efdb",
      "parents": [
        "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Sat Mar 07 06:37:59 2015 -0800"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Mar 23 16:39:37 2015 -0700"
      },
      "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n"
    },
    {
      "commit": "eeefa1276e83776f08704a3db4237423b0627e20",
      "tree": "d7c647ca77703f3712f567704f40b00d59a125de",
      "parents": [
        "02c0bac34c246c1bd974dbb86d292d4b52ba98e4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 13 18:52:59 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 16 10:48:21 2015 +0000"
      },
      "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n"
    },
    {
      "commit": "579885a26d761f5ba9550f2a1cd7f0f598c2e1e3",
      "tree": "58d144157b7a24bbdf7f8892631a15abeefa2c9f",
      "parents": [
        "2eb5168bd9e43b80452eaee5be32c063e124886e"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Sun Feb 22 20:51:33 2015 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Mon Mar 02 14:16:56 2015 +0000"
      },
      "message": "Opt Compiler: ARM64: Enable explicit memory barriers over acquire/release\n\nImplement remaining explicit memory barrier code paths and temporarily\nenable the use of explicit memory barriers for testing.\n\nThis CL also enables the use of instruction set features in the ARM64\nbackend. kUseAcquireRelease has been replaced with PreferAcquireRelease(),\nwhich for now is statically set to false (prefer explicit memory barriers).\n\nPlease note that we still prefer acquire-release for the ARM64 Optimizing\nCompiler, but we would like to exercise the explicit memory barrier code\npath too.\n\nChange-Id: I84e047ecd43b6fbefc5b82cf532e3f5c59076458\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "dc23d8318db08cb42e20f1d16dbc416798951a8b",
      "tree": "e7a883bb3263ccb971898df98bc58700604c1d1d",
      "parents": [
        "e5f5953e744060fde3b4489cea4d934d529e3e32"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Feb 16 11:15:43 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Feb 18 09:53:32 2015 +0000"
      },
      "message": "Avoid generating jmp +0.\n\nWhen a block branches to a non-following block, but blocks\nin-between do branch to it, we can avoid doing the branch.\n\nChange-Id: I9b343f662a4efc718cd4b58168f93162a24e1219\n"
    },
    {
      "commit": "3d087decd1886b818adcccd4f16802e5e54dd03e",
      "tree": "2be4d4a62d972e33150b517ff71b3023a095c8bd",
      "parents": [
        "ca9a26859d2ca8e106316dd5f16b60a325f0533c"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Wed Jan 28 11:57:05 2015 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Feb 05 20:12:31 2015 +0000"
      },
      "message": "Opt Compiler: ARM64: Enable Callee-saved register, as defined by AAPCS64.\n\nFor now we block kQuickSuspendRegister - x19, since Quick and the runtime\nuse this as a suspend counter register.\n\nChange-Id: I090d386670e81e7924e4aa9a3864ef30d0580a30\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "1cf95287364948689f6a1a320567acd7728e94a3",
      "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed",
      "parents": [
        "4a50662eeaa0b1a26be66e7584fb765151dabc59"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Dec 12 19:22:03 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 29 10:52:14 2015 +0000"
      },
      "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n"
    },
    {
      "commit": "878d58cbaf6b17a9e3dcab790754527f3ebc69e5",
      "tree": "1c1af4ef938ad06a783da51e2c6276d6b0628da6",
      "parents": [
        "b80c3154d3b6359d8ad4ce50d3a6a68224400cdd"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Jan 15 23:24:00 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Jan 28 15:32:40 2015 -0800"
      },
      "message": "ART: Arm64 optimizing compiler intrinsics\n\nImplement most intrinsics for the optimizing compiler for Arm64.\n\nChange-Id: Idb459be09f0524cb9aeab7a5c7fccb1c6b65a707\n"
    },
    {
      "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c",
      "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8",
      "parents": [
        "c698b78a17043d8898deb817098181595fbe734e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 22 13:50:01 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 23 09:20:42 2015 +0000"
      },
      "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n  between backends.\n- Remove explicit stack overflow check support: we need to adjust\n  them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n"
    },
    {
      "commit": "988939683c26c0b1c8808fc206add6337319509a",
      "tree": "876e94428276547a29c27ccf17509a42dfe7cda1",
      "parents": [
        "59add47cabce3735ccd470cd3b5dac8b112e09ab"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 12:32:32 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 18:50:25 2015 +0000"
      },
      "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n"
    },
    {
      "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea",
      "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242",
      "parents": [
        "4d2c611bf17ff309abfa152e56c0b98a21ec8787"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Mon Jan 12 18:45:46 2015 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Wed Jan 21 14:26:35 2015 +0000"
      },
      "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n"
    },
    {
      "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f",
      "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f",
      "parents": [
        "12c03ac7575db242a6f35739bb459e8277115da4"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Thu Jan 08 17:35:35 2015 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Jan 16 17:27:03 2015 +0000"
      },
      "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n"
    },
    {
      "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd",
      "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4",
      "parents": [
        "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 13 09:20:58 2015 -0500"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Jan 15 11:21:37 2015 -0500"
      },
      "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine.  This fails for X86,\nwhere a double in an XMM register takes up 8 bytes.  Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce",
      "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518",
      "parents": [
        "893e8881e31180721512c1b9e5ffacb03aad2e45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 07 16:01:24 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 08 13:57:51 2015 +0000"
      },
      "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n  (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n  registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n"
    },
    {
      "commit": "02d81cc8d162a31f0664249535456775e397b608",
      "tree": "8bce70d3d44dcc9384d72e4edc1505e4d1a6ea07",
      "parents": [
        "8558375377946aabbbda6ab584e13f754590bd89"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Mon Jan 05 16:08:49 2015 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Mon Jan 05 18:23:33 2015 +0000"
      },
      "message": "Opt Compiler: ARM64: Add support for rem-float, rem-double and volatile.\n\nAdd support for rem-float, rem-double and volatile memory accesses\nusing acquire-release and memory barriers.\n\nChange-Id: I96a24dff66002c3b772c3d8e6ed792e3cb59048a\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8",
      "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519",
      "parents": [
        "6004796d6c630696127df2494dcd4f30d1367a34"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Dec 18 17:45:56 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Dec 18 17:45:56 2014 +0000"
      },
      "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n"
    },
    {
      "commit": "6004796d6c630696127df2494dcd4f30d1367a34",
      "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97",
      "parents": [
        "407d77f344cfbdbbfb50531c5f0766bc0892e2fe"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Dec 15 00:01:18 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Dec 18 14:59:50 2014 +0000"
      },
      "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n  out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n"
    },
    {
      "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c",
      "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955",
      "parents": [
        "776b880f66edb21cb3b4225877e494ec7a9ec1a2"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 10:36:50 2014 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 14:36:14 2014 +0000"
      },
      "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7"
    },
    {
      "commit": "02164b352a1474c616771582ca9a73a2cc514c1f",
      "tree": "6c124ec6e19f18343b69df8cddcb74e17447f294",
      "parents": [
        "32f5b4d2c8c9b52e9522941c159577b21752d0fa"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Nov 13 14:05:07 2014 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Fri Nov 28 13:10:25 2014 +0000"
      },
      "message": "Opt Compiler: Arm64: Add support for more IRs plus various fixes.\n\nAdd support for more IRs and update others.\n\nChange-Id: Iae1bef01dc3c0d238a46fbd2800e71c38288b1d2\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa",
      "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c",
      "parents": [
        "eea79dd779ba199658ada7264f8f96d776e53f19"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Tue Nov 25 20:05:46 2014 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Fri Nov 28 12:02:58 2014 +0000"
      },
      "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6",
      "tree": "3db61320369973e463f67927a8983d7eb0d9f860",
      "parents": [
        "255a5bde2f0014dc86a564555106a4291c0867b4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 08:47:18 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 08:47:18 2014 +0000"
      },
      "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n"
    },
    {
      "commit": "67555f7e9a05a9d436e034f67ae683bbf02d072d",
      "tree": "9a01b7c69032b08b3c55c18076f68c1e397d8a35",
      "parents": [
        "bf75c5cf32a47eecadcc5e4a324237c1f1d09cde"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Tue Nov 18 10:55:16 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Nov 18 15:36:36 2014 +0000"
      },
      "message": "Opt compiler: Add support for more IRs on arm64.\n\nChange-Id: I4b6425135d1af74912a206411288081d2516f8bf\n"
    },
    {
      "commit": "f0e3937b87453234d0d7970b8712082062709b8d",
      "tree": "e552c1173ee90fea1d2ba11cc08878efe65ba0be",
      "parents": [
        "59321e0e10ea09694efecf6154704e2743b9bffd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 17:50:07 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 17:55:24 2014 +0000"
      },
      "message": "Do a parallel move in BoundsCheckSlowPath.\n\nThe two locations of the index and length could overlap,\nso we need a parallel move. Also factorize the code for\ndoing a parallel move based on two locations.\n\nChange-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4\n"
    },
    {
      "commit": "fc19de8b201475231751b9df08fce01a093e5c2b",
      "tree": "7c0e9c923a37d059f1707156d69f4908aca308ac",
      "parents": [
        "a89086e3be94fb262c4c4feb15241b30616c3b8f"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Fri Nov 07 17:13:31 2014 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Mon Nov 10 17:31:38 2014 +0000"
      },
      "message": "Opt compiler: Add arm64 support for a few more IRs.\n\nChange-Id: I781ddcbc61eb2b04ae80b1c7697e1ed5694bd5b9"
    },
    {
      "commit": "a89086e3be94fb262c4c4feb15241b30616c3b8f",
      "tree": "82878d8a6c5418c43ff45857b81db7c88af7d455",
      "parents": [
        "974bc2747b345667e07692109d63675ec50955a3"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Fri Nov 07 17:13:25 2014 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Mon Nov 10 17:31:17 2014 +0000"
      },
      "message": "Opt compiler: Add arm64 support for floating-point.\n\nChange-Id: I0d97ab0f5ab770fee62c819505743febbce8835e"
    },
    {
      "commit": "de58ab2c03ff8112b07ab827c8fa38f670dfc656",
      "tree": "c872bfbcad1e90845008140bbddcc43e56dc19d2",
      "parents": [
        "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 05 12:46:03 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Nov 06 16:49:52 2014 +0000"
      },
      "message": "Implement try/catch/throw in optimizing.\n\n- We currently don\u0027t run optimizations in the presence of a try/catch.\n- We therefore implement Quick\u0027s mapping table.\n- Also fix a missing null check on array-length.\n\nChange-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f\n"
    },
    {
      "commit": "6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f",
      "tree": "9df58b57af13240a93a6da4eefcf03f70cce9ad9",
      "parents": [
        "c6e0955737e15f7c0c3575d4e13789b3411f4993"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Oct 31 00:33:20 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Mon Nov 03 20:01:04 2014 -0800"
      },
      "message": "Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.\n\nFix associated errors about unused paramenters and implict sign conversions.\nFor sign conversion this was largely in the area of enums, so add ostream\noperators for the effected enums and fix tools/generate-operator-out.py.\nTidy arena allocation code and arena allocated data types, rather than fixing\nnew and delete operators.\nRemove dead code.\n\nChange-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b\n"
    },
    {
      "commit": "5319defdf502fc4569316473846b83180ec08035",
      "tree": "909c6b29f065c79c8368a283946947cbb582d1c7",
      "parents": [
        "37a7188810e865a1ee0a7bdc2d01d62c1f1ea49e"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Thu Oct 23 10:03:10 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 23 13:44:42 2014 +0100"
      },
      "message": "ART: optimizing compiler: initial support for ARM64.\n\nThe ARM64 port uses VIXL for code generation, to which it defers work\nlike label binding and branch resolving, register type coherency\nchecking, and immediate values handling.\n\nChange-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\nSigned-off-by: Alexandre Rames \u003calexandre.rames@arm.com\u003e\n"
    }
  ]
}