)]}'
{
  "log": [
    {
      "commit": "91d65e024846717fce3572106cffe9b957b8902c",
      "tree": "22ea1a91afdd552a31bb2365a9eae034ae0a1c9b",
      "parents": [
        "1bcbcf8e848d18b19d248c3d15f77c888f2b5f04"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Jan 19 15:59:16 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Jan 19 15:59:16 2016 +0000"
      },
      "message": "Fix various typos in ART\u0027s comments and string literals.\n\nChange-Id: I85d628055b1a61647a77fef730c9631c234e22a2\n"
    },
    {
      "commit": "c928591f5b2c544751bb3fb26dc614d3c2e67bef",
      "tree": "b6c8a5e08c4d4c7a66a70f4d91e209ededf22334",
      "parents": [
        "5ee288c9dd99614e3a238f5efceeec6456e3499d"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Dec 18 10:38:42 2015 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jan 08 12:55:31 2016 +0000"
      },
      "message": "ARM Baker\u0027s read barrier fast path implementation.\n\nIntroduce an ARM fast path implementation in Optimizing for\nBaker\u0027s read barriers (for both heap reference loads and GC\nroot loads).  The marking phase of the read barrier is\nperformed by a slow path, invoking the runtime entry point\nartReadBarrierMark.\n\nOther read barrier algorithms continue to use the original\nslow path based implementation, which has been renamed as\nGenerateReadBarrierSlow/GenerateReadBarrierForRootSlow.\n\nBug: 12687968\nChange-Id: Ie7ee85b1b4c0564148270cebdd3cbd4c3da51b3a\n"
    },
    {
      "commit": "3e3e4a762c23c3de66436b30e9fc65f35dad344c",
      "tree": "8a039c333528790c52a080311511f36186c6ff9f",
      "parents": [
        "fb9f4ad455eced3a07bef1d4772ab1fe34ec133b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Dec 17 14:28:35 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Dec 17 14:31:05 2015 +0000"
      },
      "message": "Fix braino in parallel move resolver.\n\nReiterating over the moves needs to set i to -1, not 0.\n\nbug:26241132\n\nChange-Id: Iaae7eac5b421b0ee1b1ce89577c8b951b2d4dae8\n"
    },
    {
      "commit": "ec7802a102d49ab5c17495118d4fe0bcc7287beb",
      "tree": "08649609604b9c96bc48ca071c48b0af5abb1a3f",
      "parents": [
        "b2e436ffcda1d7a87e7bf9133d8ed878388c73c2"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 01 20:57:57 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 08 11:10:18 2015 +0100"
      },
      "message": "Add DCHECKs to ArenaVector and ScopedArenaVector.\n\nImplement dchecked_vector\u003c\u003e template that DCHECK()s element\naccess and insert()/emplace()/erase() positions. Change the\nArenaVector\u003c\u003e and ScopedArenaVector\u003c\u003e aliases to use the new\ntemplate instead of std::vector\u003c\u003e. Remove DCHECK()s that\nhave now become unnecessary from the Optimizing compiler.\n\nChange-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc\n"
    },
    {
      "commit": "225b6464a58ebe11c156144653f11a1c6607f4eb",
      "tree": "3f1c6067c3841c892edaa1a60a61af9c559cb4e4",
      "parents": [
        "6a9984e62c08bcd78c8e49dd40b1f0f9d53513b7"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 28 12:17:40 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 29 10:49:35 2015 +0100"
      },
      "message": "Optimizing: Tag arena allocations in code generators.\n\nAnd completely remove the deprecated GrowableArray.\n\nReplace GrowableArray with ArenaVector in code generators\nand related classes and tag arena allocations.\n\nLabel arrays use direct allocations from ArenaAllocator\nbecause Label is non-copyable and non-movable and as such\ncannot be really held in a container. The GrowableArray\nnever actually constructed them, instead relying on the\nzero-initialized storage from the arena allocator to be\ncorrect. We now actually construct the labels.\n\nAlso avoid StackMapStream::ComputeDexRegisterMapSize() being\npassed null references, even though unused.\n\nChange-Id: I26a46fdd406b23a3969300a67739d55528df8bf4\n"
    },
    {
      "commit": "6e18dcb5d2c35c646f2c95cb776abb79799f52ae",
      "tree": "7db4912d4d10f465a162dc93be717526dbb075c4",
      "parents": [
        "595335100a947693b9af5fb6c0b5b3c1f0b91788"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jul 28 17:26:55 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jul 28 17:26:55 2015 -0400"
      },
      "message": "Parallel Move Resolver: Perform Stack/Stack first\n\nOn machines like x86, by the time other parallel moves are done, there\nmay be no free registers available to move/swap without having to save\nand restore a register.\n\nTo avoid this, perform stack/stack first, while there is a good chance\nthat there is a destination register that we can use.  On the X86, this\navoids a lot of push eax/pop eax code.\n\nChange-Id: I57076271b5672c931a93888ff23e30b2567f43b8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467",
      "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab",
      "parents": [
        "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:48:56 2015 +0800"
      },
      "committer": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:54:08 2015 +0800"
      },
      "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n"
    },
    {
      "commit": "669d8a1edbb2a78e08731a9cd6d8e815b0ec49db",
      "tree": "240d26edb4af28ccd7fa65a9fecc39f718d3d603",
      "parents": [
        "ee2da343bb2a54d9d77e29226e0317ccc913c8c1",
        "e14590bdfed24df30e6b7545fc819ba03ff8bba1"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Thu Apr 16 09:40:38 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 16 09:40:39 2015 +0000"
      },
      "message": "Merge \"Revert \"[optimizing] Improve x86 parallel moves/swaps\"\""
    },
    {
      "commit": "e14590bdfed24df30e6b7545fc819ba03ff8bba1",
      "tree": "1fe89a424c91dae7adc07ebd620dce8297a0854e",
      "parents": [
        "a5c19ce8d200d68a528f2ce0ebff989106c4a933"
      ],
      "author": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Wed Apr 15 18:57:27 2015 +0000"
      },
      "committer": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Wed Apr 15 18:57:27 2015 +0000"
      },
      "message": "Revert \"[optimizing] Improve x86 parallel moves/swaps\"\n\nThis reverts commit a5c19ce8d200d68a528f2ce0ebff989106c4a933.\n\nThis commit introduces a performance regression on CaffeineLogic of 30%.\n\nChange-Id: I917e206e249d44e1748537bc1b2d31054ea4959d\n"
    },
    {
      "commit": "9021825d1e73998b99c81e89c73796f6f2845471",
      "tree": "13e1038931cbb8bf8b8d0f4e3f51553ba1bfa983",
      "parents": [
        "858d28ca2e73a785977f53141e775a7d4841b89d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Apr 15 11:56:51 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Apr 15 12:53:42 2015 +0100"
      },
      "message": "Type MoveOperands.\n\nThe ParallelMoveResolver implementation needs to know if a move\nis for 64bits or not, to handle swaps correctly.\n\nBug found, and test case courtesy of Serguei I. Katkov.\n\nChange-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506\n"
    },
    {
      "commit": "a5c19ce8d200d68a528f2ce0ebff989106c4a933",
      "tree": "4638a8d8e5b1562ec5ed05967490fec1ef7f0d17",
      "parents": [
        "6d80318c382a3490ab605b46fa7cb22c5e823fec"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Apr 01 12:51:05 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Apr 10 12:08:31 2015 -0400"
      },
      "message": "[optimizing] Improve x86 parallel moves/swaps\n\nAdd a new constructor to ScratchRegisterScope that will supply a\nregister if there is a free one, but not spill to force one.  Use this\nto generated alternate code that doesn\u0027t use a temporary, as the\nspill/restore of a register generates extra instructions that aren\u0027t\nnecessary on x86.\n\nHere is the benefit for a 32 bit memory-to-memory exchange with no\nfree registers:\n\u003c        50    \t       push eax\n\u003c        53    \t       push ebx\n\u003c  8B44244C    \t       mov eax, [esp + 76]\n\u003c  8B5C246C    \t       mov ebx, [esp + 108]\n\u003c  8944246C    \t       mov [esp + 108], eax\n\u003c  895C244C    \t       mov [esp + 76], ebx\n\u003c        5B    \t       pop ebx\n\u003c        58    \t       pop eax\n---\n\u003e  FF742444    \t       push [esp + 68]\n\u003e  FF742468    \t       push [esp + 104]\n\u003e  8F44244C    \t       pop [esp + 72]\n\u003e  8F442468    \t       pop [esp + 100]\n\nAvoid using xchg instruction, as it is slow on smaller processors.\n\nChange-Id: Id29ee3abd998577baaee552d55d23e60ae0c7871\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "a2d15b5e486021bef330b70c21e99557cb116ee5",
      "tree": "71d7da32199f1342202099c9c7c0baa30094299f",
      "parents": [
        "dcff612c3a6e1427749771c4559f198fa480f709"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 31 18:13:51 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 31 18:31:39 2015 +0100"
      },
      "message": "Fix wrong assumptions about ParallelMove.\n\nRegisters involved in single and double operations can\ndrag stack locations as well, so it is possible to update\na single stack location with a slot from a double stack location.\n\nbug:19999189\n\nChange-Id: Ibeec7d6f1b3126c4ae226fca56e84dccf798d367\n"
    },
    {
      "commit": "f7a0c4e421b5edaad5b7a15bfff687da28d0b287",
      "tree": "5423a2357661b80d75cb2e3a2b5395a3fe3cd9b5",
      "parents": [
        "0f2433bfcb02a662fe739e8e2b068abc2958e4c1"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Feb 10 17:08:47 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Feb 10 19:12:59 2015 +0000"
      },
      "message": "Improve ParallelMoveResolver to work with pairs.\n\nChange-Id: Ie2a540ffdb78f7f15d69c16a08ca2d3e794f65b9\n"
    },
    {
      "commit": "42d1f5f006c8bdbcbf855c53036cd50f9c69753e",
      "tree": "fb885c3df20797b55f19e5ceccf72dac1c13017b",
      "parents": [
        "36740379b9b1c81b7eb06ea9c9df411d0a9a765e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 16 09:14:18 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 16 11:22:08 2015 +0000"
      },
      "message": "Do not use register pair in a parallel move.\n\nThe ParallelMoveResolver does not work with pairs. Instead,\ndecompose the pair into two individual moves.\n\nChange-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f\n"
    },
    {
      "commit": "48c310c431b110f6ab54907da20c4fa39a8f76b8",
      "tree": "3f8e75544539544feda353a1f225145e5ee41fa0",
      "parents": [
        "c40a4350daac81ddbfc5f6ceab934f2180dc4ec6"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 14 10:45:05 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 14 14:45:40 2015 +0000"
      },
      "message": "Remove constant moves after emitting them in parallel resolver.\n\nThis fixes the case where a constant move requires a scratch\nregister. Note that there is no backend that needs this for now,\nbut X86 might with the move to hard float.\n\nChange-Id: I37f6b8961b48f2cf6fbc0cd281e70d58466d018e\n"
    },
    {
      "commit": "277ccbd200ea43590dfc06a93ae184a765327ad0",
      "tree": "d89712e93da5fb2748989353c9ee071102cf3f33",
      "parents": [
        "ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Nov 03 21:36:10 2014 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Nov 04 18:40:08 2014 -0800"
      },
      "message": "ART: More warnings\n\nEnable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,\nand -Wunused-but-set-parameter for GCC builds.\n\nChange-Id: I81bbdd762213444673c65d85edae594a523836e5\n"
    },
    {
      "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f",
      "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a",
      "parents": [
        "a3c4d72210de174552f47b2d117b1946f274af1e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 11:47:51 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 14:42:13 2014 +0100"
      },
      "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n"
    },
    {
      "commit": "e27f31a81636ad74bd3376ee39cf215941b85c0e",
      "tree": "12dd6a1153b78b831c887f65f0bcef715e89719d",
      "parents": [
        "dfc2091d2fb8a7694f69acf8bd39ce4953e026c2"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 17:53:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 18:05:00 2014 +0100"
      },
      "message": "Enable the register allocator on ARM.\n\n- Also fixes a few bugs/wrong assumptions in code not hit by x86.\n- We need to differentiate between moves due to connecting siblings within\n  a block, and moves due to control flow resolution.\n\nChange-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38\n"
    },
    {
      "commit": "86dbb9a12119273039ce272b41c809fa548b37b6",
      "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5",
      "parents": [
        "c936622863a50bdda9b10062515dfc02a8c8b652"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 04 11:12:39 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 10:02:06 2014 +0100"
      },
      "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n   allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n   inputs/output to be at a specific location, and the allocator\n   needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n"
    },
    {
      "commit": "4e3d23aa1523718ea1fdf3a32516d2f9d81e84fe",
      "tree": "78593d033513a98486a409e7b23678ccced12cd5",
      "parents": [
        "59f3f62534581311c7c403c832f56c272426a17c"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu May 22 18:32:45 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri May 23 10:00:44 2014 +0100"
      },
      "message": "Import Dart\u0027s parallel move resolver.\n\nAnd write a few tests while at it.\n\nA parallel move resolver will be needed for performing multiple moves\nthat are conceptually parallel, for example moves at a block\nexit that branches to a block with phi nodes.\n\nChange-Id: Ib95b247b4fc3f2c2fcab3b8c8d032abbd6104cd7\n"
    }
  ]
}