)]}' { "log": [ { "commit": "d9ffd0dd7266f6a5e76f29d98dbe1a04f64cbb9b", "tree": "7589320b18206648538734493fe5590023fecf5c", "parents": [ "fe5c430e6ef71e8f8932ece9631a4e9bfc8b7916" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Wed Jun 22 10:27:55 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Aug 05 13:24:41 2016 -0700" }, "message": "Implement a graph coloring register allocator\n\nTest: m test-art-host\n\nChange-Id: I8c0d77f339ab02b33588a54b96ecce5c8322cfce\n" }, { "commit": "8f49d4b04bab40bfd32ed7c8dfe501dea172bd79", "tree": "53ebbc7573f6ebd9c53e00f62e93358e9c4405af", "parents": [ "360b4b0137ce5f0bb771e2ddbfd4735cae932565" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Thu Jul 14 13:24:00 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Wed Jul 20 09:33:48 2016 -0700" }, "message": "Refactor register allocation to be pluggable\n\nAllow alternate register allocation strategies to be implemented\nin subclasses of a common register allocation base class.\n\nTest: m test-art-host\n\nChange-Id: I7c5866aa9ddff8f53fcaf721bad47654ab221b4f\n" }, { "commit": "e9288851eb6b62ece28f510d978d3793723b9a51", "tree": "3d422c4dfa7437b4891504ee452bf50b4852a9c5", "parents": [ "161c866ca742049f5c916696e1503c697be30e87" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Thu Jul 14 14:08:16 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Jul 15 18:09:46 2016 -0700" }, "message": "Rename current register allocator implementation\n\nThis will allow a cleaner commit in an upcoming\nrefactoring of register allocation.\n\nTest: m test-art-host\n\nChange-Id: If420c97b088b3c934411ff83373e024003120746\n" }, { "commit": "f64a6ab5f69446303faadbf6a0ede00af435e25c", "tree": "a445bbe8fa31ad699b91eee3386e0ac2864f561a", "parents": [ "dedde3f10d7801ad862d1ca1de89135decff6a60" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Mon Jul 11 14:45:01 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jul 12 10:20:55 2016 -0700" }, "message": "Improve search for available spill slots in RA\n\nPreviously we always searched for two adjacent spill slots, even if\nwe only needed one. This small change fixes that.\n\nTest: m test-art-host\n\nChange-Id: I021d355e6602ffee687c8537a959232b1504dcf1\n" }, { "commit": "e90049140fdfb89080e5cc9b000b0c9be8c18bcd", "tree": "66b45c052b6778fabd7847a44af5e610808fa867", "parents": [ "a77ceae14a7be2494874d9256327efa8c522e234" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 16 16:50:52 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 01 13:26:24 2016 +0100" }, "message": "Create a typedef for HInstruction::GetInputs() return type.\n\nAnd some other cleanup after\n https://android-review.googlesource.com/230742\n\nTest: No new tests. ART test suite passed (tested on host).\nChange-Id: I4743bf17544d0234c6ccb46dd0c1b9aae5c93e17\n" }, { "commit": "372f10e5b0b34e2bb6e2b79aeba6c441e14afd1f", "tree": "1f29c2467c8909ef0e0147f37f176caa1bcd2ccc", "parents": [ "1b66fdf3f33c72dfdda4d31f6f17b6a0d8607402" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 17 16:30:10 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 02 19:04:20 2016 +0100" }, "message": "Refactor handling of input records.\n\nIntroduce HInstruction::GetInputRecords(), a new virtual\nfunction that returns an ArrayRef\u003c\u003e to all input records.\nImplement all other functions dealing with input records as\nwrappers around GetInputRecords(). Rewrite functions that\npreviously used multiple virtual calls to deal with input\nrecords, especially in loops, to prefetch the ArrayRef\u003c\u003e\nonly once for each instruction. Besides avoiding all the\nextra calls, this also allows the compiler (clang++) to\nperform additional optimizations.\n\nThis speeds up the Nexus 5 boot image compilation by ~0.5s\n(4% of \"Compile Dex File\", 2% of dex2oat time) on AOSP ToT.\n\nChange-Id: Id8ebe0fb9405e38d918972a11bd724146e4ca578\n" }, { "commit": "d7c2fdc939bb7efb3e7204d62e54c6a3f7d77f9b", "tree": "692eb754d2cf5fdb81809529f02a50f2e4747a62", "parents": [ "b2b55596e605bef315b615cb89e4515f360548f2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 10 14:35:34 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 12 08:58:12 2016 +0100" }, "message": "Fix another case of live_in at irreducible loop entry.\n\nGVN was implicitly extending the liveness of an instruction across\nan irreducible loop.\n\nFix this problem by clearing the value set at loop entries that contain\nan irreducible loop.\n\nbug:28252896\n\n(cherry picked from commit 77ce6430af2709432b22344ed656edd8ec80581b)\n\nChange-Id: Ie0121e83b2dfe47bcd184b90a69c0194d13fce54\n" }, { "commit": "32cc778aff36c5d99026d9bdef5f75a5b17cfe23", "tree": "9b6fffaab3b76314ad19d86267e358f0572a80db", "parents": [ "dba2b19c845f6bccb43a036fa8602197c3248ff2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 23 11:32:27 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 24 09:55:18 2016 +0000" }, "message": "Do a null check on the sibling in the register allocator.\n\nThere may be a lifetime hole between the intervals, which means there is\nno interval for the given position.\n\nLitle sister of https://android-review.googlesource.com/#/c/209336/.\n\nbug:27626705\nChange-Id: I8082aa5ae2dc37d8fa5d4c430b69e6defa495439\n" }, { "commit": "dba2b19c845f6bccb43a036fa8602197c3248ff2", "tree": "9ba73975794017d212148ab205b1fdc050eaef8d", "parents": [ "3920099f578fd8015777bc3c1c7392a08b1e08e7", "974bbdd24404830538f6ab1efe3062e4a411e3ae" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 23 14:52:28 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 23 14:52:29 2016 +0000" }, "message": "Merge \"Relax too strong DCHECK.\"" }, { "commit": "974bbdd24404830538f6ab1efe3062e4a411e3ae", "tree": "c9e2626c13db544634388d872ebd65bf94b7c1a2", "parents": [ "459898dc4470559ba1e1d578bc52a914d1f573f5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 22 15:12:07 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 22 15:13:04 2016 +0000" }, "message": "Relax too strong DCHECK.\n\nThere may be a lifetime hole in the interval, which means the interval\ndoes not cover the given position.\n\nbug:27617589\n\nChange-Id: Iabd2b3d82936bed498f87be1a01760210954f97e\n" }, { "commit": "f6a35de9eeefb20f6446f1b4815b4dcb0161d09c", "tree": "cf484acbd6889b92a7fe3e8615611129088c3894", "parents": [ "459898dc4470559ba1e1d578bc52a914d1f573f5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Mar 21 12:01:50 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Mar 21 16:50:08 2016 +0000" }, "message": "Optimizing: Fix register allocator validation memory usage.\n\nAlso attribute ArenaBitVector allocations to appropriate\npasses. This was used to track down the source of the\nexcessive memory alloactions.\n\nBug: 27690481\n\nChange-Id: Ib895984cb7c04e24cbc7abbd8322079bab8ab100\n" }, { "commit": "119a885ff58f158a4e3cd783c5604ae4252a08eb", "tree": "6fb6eefb81d4d053645a3b5e8475ee4e8b43d68c", "parents": [ "2a49bc4625155b80287c155b57354b9559d71bed" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Feb 06 17:01:15 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Feb 06 17:01:36 2016 +0000" }, "message": "Fix AllocateBlockedReg.\n\nMotivated by System.arraycopy(char) for x86, where only looking\nat use and not register use makes the allocator think it\u0027s out\nof registers.\n\nbug:27019403\nChange-Id: I0db5bc839a77e6394a07facbf19d00a165dc2ef7\n" }, { "commit": "ad4ed08d557ff24bd7c66d3f36687d2035367ad0", "tree": "8322b51a8551c7805427b19f058a68659374b710", "parents": [ "902838d865eaed9fa4df6414c706e5f6787d02ea" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 27 14:15:23 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 28 09:11:42 2016 +0000" }, "message": "Revert \"Revert \"Lift the spill at each irreducible loop block restriction.\"\"\n\nThis reverts commit 2818dbcd75ea9beadcba9d18e2f68523108d0cf5.\n\nChange-Id: I92b2b60b4f08f50cacfea4132f1c28cfbd628f1a\n" }, { "commit": "2818dbcd75ea9beadcba9d18e2f68523108d0cf5", "tree": "5e4a1f49fe8e59c105397b53da3a5a963a22a9ff", "parents": [ "79e9f43951c3cfa9ab3b0fea93e5bfdfa7aa5950" ], "author": { "name": "Bart Sears", "email": "bsears@google.com", "time": "Tue Jan 26 17:38:19 2016 +0000" }, "committer": { "name": "Bart Sears", "email": "bsears@google.com", "time": "Tue Jan 26 17:38:19 2016 +0000" }, "message": "Revert \"Lift the spill at each irreducible loop block restriction.\"\n\nThis reverts commit 79e9f43951c3cfa9ab3b0fea93e5bfdfa7aa5950.\n\nChange-Id: I0670618b4076e06bd3f6bf8c385abfd1b651393c\n" }, { "commit": "79e9f43951c3cfa9ab3b0fea93e5bfdfa7aa5950", "tree": "ff436caee8e272f520628237553b5a490384b362", "parents": [ "5d5dbeb0344fa57f34cee40f01f96829eae4b514" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 23 23:00:45 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 26 13:38:41 2016 +0000" }, "message": "Lift the spill at each irreducible loop block restriction.\n\nIt was not intended to have it this way anyway. This also\nrequired to fix GetSiblingAt, to take into account interval\nholes, and ConnectSplitSibling to re-materialize a constant\nor a method.\n\nChange-Id: Ia5534a93a5413cd0458a251c022d0b655369502b\n" }, { "commit": "04eb70f0282703a150e3e2c7e5b3f678fec25397", "tree": "dfcc1d1ab084af12fd5f8370c12ffd1e5f67d025", "parents": [ "8ae596fb0496d93b8d9bb5d5b162d7e6c32c39a2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 21 18:22:23 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 22 11:45:12 2016 +0000" }, "message": "With irreducible loops, we can have a null destination.\n\nbug:26684047\nChange-Id: I23d1c74caec4aaebc05362a588f6cfec2132bdc8\n" }, { "commit": "58282f4510961317b8d5a364a6f740a78926716f", "tree": "5d97c0db9fe01dd6e8df2357ef11f614abb853e8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 12:45:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 16:39:30 2016 +0000" }, "message": "ART: Remove Baseline compiler\n\nWe don\u0027t need Baseline any more and it hasn\u0027t been maintained for\na while anyway. Let\u0027s remove it.\n\nChange-Id: I442ed26855527be2df3c79935403a25b1ee55df6\n" }, { "commit": "947cb4f5582d1f57270b48d3c47ea95e7f9085b5", "tree": "6f6aed8f8cca3177b06521a8db6ca845d18623ad", "parents": [ "7b4199a5fa9f151fbf3af2a34f26d04215a1016c", "15bd22849ee6a1ffb3fb3630f686c2870bdf1bbc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 14 21:25:16 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 14 21:25:16 2016 +0000" }, "message": "Merge \"Implement irreducible loop support in optimizing.\"" }, { "commit": "15bd22849ee6a1ffb3fb3630f686c2870bdf1bbc", "tree": "a261601589163faa4538bcf1c9d156e8ec4a42b3", "parents": [ "5b7b5ddb515828c93f0c2aec67aa513c32d0de22" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 05 15:55:41 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 14 15:00:20 2016 +0000" }, "message": "Implement irreducible loop support in optimizing.\n\nSo we don\u0027t fallback to the interpreter in the presence of\nirreducible loops.\n\nImplications:\n- A loop pre-header does not necessarily dominate a loop header.\n- Non-constant redundant phis will be kept in loop headers, to\n satisfy our linear scan register allocation algorithm.\n- while-graph optimizations, such as gvn, licm, lse, and dce\n need to know when they are dealing with irreducible loops.\n\nChange-Id: I2cea8934ce0b40162d215353497c7f77d6c9137e\n" }, { "commit": "1af564e2d3b560fb9a076eb35ea20471aed0dc92", "tree": "1a369a546a6319fd866c241d5c92f3a241d314af", "parents": [ "922698ded1e80cad1ecce4c2172a88c76a216373" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 13 12:09:39 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 13 12:38:52 2016 +0000" }, "message": "Set side effects to HNullCheck and HBoundsCheck.\n\nBoth can trigger GC, as they will call NullPointerException or\nIndexOutOfBoundsException constructors.\n\nbug:26532563\nChange-Id: Id9e42f0450caaaf365630989e1b36e98add46c89\n" }, { "commit": "a3eca2d7300f35c66cf4b696d788a8b7ba74eb99", "tree": "18ea775d51bfc71d90407bd801e8b56fb5309868", "parents": [ "3da15f8b1097905e06a59149c3a4a9658cbb7d5e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 12 16:03:16 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 12 16:05:38 2016 +0000" }, "message": "Do not leave intermediate addresses across Java calls.\n\nbug:26472446\nChange-Id: Ie4a9b5fe6f1d61a76c71eceaa2299fe55512c612\n" }, { "commit": "d26a411adee1e71b3f09dd604ab9b23018037138", "tree": "7e9267d50fb0a9bcd6b14a97653c8e0baf91a575", "parents": [ "8a6463a7052ec69e7c0b94a65b26807f570e6359" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Nov 10 11:07:31 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Nov 10 18:28:21 2015 +0000" }, "message": "ART: Refactor iteration over normal/exceptional successors\n\nAdd helper methods on HBasicBlock which return ArrayRef with the\nsuitable sub-array of the `successors_` list.\n\nChange-Id: I66c83bb56f2984d7550bf77c48110af4087515a8\n" }, { "commit": "f652cecb984c104d44a0223c3c98400ef8ed8ce2", "tree": "ec0cc193eccdd11a79f42f957a856d2ba57699e1", "parents": [ "b8b44983f861cfeeca66c624dd0f2a3fa71b4992" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Aug 25 16:11:42 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Oct 22 18:51:13 2015 +0200" }, "message": "MIPS: Initial version of optimizing compiler for MIPS32\n\nChange-Id: I370388e8d5de52c7001552b513877ef5833aa621\n" }, { "commit": "359f77c44dafef7ebed027180422ee75eef1467c", "tree": "b4b7fd4f8bf646dcd106351aaf2f5c1e6d719911", "parents": [ "64d8d93aa9359b1126513dba92e27dbe184bfe3a", "ec7802a102d49ab5c17495118d4fe0bcc7287beb" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 08 15:47:08 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 08 15:47:08 2015 +0000" }, "message": "Merge \"Add DCHECKs to ArenaVector and ScopedArenaVector.\"" }, { "commit": "b95fb775cc4c08349d0d905adbc96ad85e50601d", "tree": "f8d0212508d5c21f792a1781983d8668d1491aa1", "parents": [ "b2e436ffcda1d7a87e7bf9133d8ed878388c73c2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 30 13:32:31 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 08 11:59:48 2015 +0100" }, "message": "Optimizing: Clean up after tagging arena allocations.\n\nChange-Id: Id6ee1fe44c4c57d373db7a39530f29a5ca9aee18\n" }, { "commit": "ec7802a102d49ab5c17495118d4fe0bcc7287beb", "tree": "08649609604b9c96bc48ca071c48b0af5abb1a3f", "parents": [ "b2e436ffcda1d7a87e7bf9133d8ed878388c73c2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 01 20:57:57 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 08 11:10:18 2015 +0100" }, "message": "Add DCHECKs to ArenaVector and ScopedArenaVector.\n\nImplement dchecked_vector\u003c\u003e template that DCHECK()s element\naccess and insert()/emplace()/erase() positions. Change the\nArenaVector\u003c\u003e and ScopedArenaVector\u003c\u003e aliases to use the new\ntemplate instead of std::vector\u003c\u003e. Remove DCHECK()s that\nhave now become unnecessary from the Optimizing compiler.\n\nChange-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc\n" }, { "commit": "5233f93ee336b3581ccdb993ff6342c52fec34b0", "tree": "225dc0ab491263ef56362a8d0fe2926266bd5047", "parents": [ "de8a3f4dce1e9ff0e3be16956b06bafc8cd4f397" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 19:01:15 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 19:46:03 2015 +0100" }, "message": "Optimizing: Tag even more arena allocations.\n\nTag previously \"Misc\" arena allocations with more specific\nallocation types. Move some native heap allocations to the\narena in BCE.\n\nBug: 23736311\nChange-Id: If8ef15a8b614dc3314bdfb35caa23862c9d4d25c\n" }, { "commit": "ec7e44f7afe0ff48d4d1ae54a12d375e0392d24c", "tree": "30ce5725c7258d6584a56f2c6382cee529df2cc2", "parents": [ "e92ed9d31bae7ccd48b60aa921e9dd2ca96ac9db", "2aaa4b5532d30c4e65d8892b556400bb61f9dc8c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Sep 25 13:59:08 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Sep 25 13:59:08 2015 +0000" }, "message": "Merge \"Optimizing: Tag more arena allocations.\"" }, { "commit": "2aaa4b5532d30c4e65d8892b556400bb61f9dc8c", "tree": "f4259c33171ec8efd945aeedab1e57feb7970f42", "parents": [ "3f4b39dec9ec6b8948ed18b9d65ba49db2465004" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 17 17:03:26 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Sep 25 12:18:02 2015 +0100" }, "message": "Optimizing: Tag more arena allocations.\n\nReplace GrowableArray with ArenaVector and tag arena\nallocations with new allocation types.\n\nAs part of this, make the register allocator a bit more\nefficient, doing bulk insert/erase. Some loops are now\nO(n) instead of O(n^2).\n\nChange-Id: Ifac0871ffb34b121cc0447801a2d07eefd308c14\n" }, { "commit": "fe57faa2e0349418dda38e77ef1c0ac29db75f4d", "tree": "38ba7a406f8a86a1152bd6c9f2d0a6c677423211", "parents": [ "9e30c0e177adabaaf94a66c91130a19a7632fc7c" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Sep 18 09:26:15 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Sep 21 07:23:45 2015 -0400" }, "message": "[optimizing] Add basic PackedSwitch support\n\nAdd HPackedSwitch, and generate it from the builder. Code generators\nconvert this to a series of compare/branch tests. Better implementation\nin the code generators as a real jump table will follow as separate CLs.\n\nChange-Id: If14736fa4d62809b6ae95280148c55682e856911\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "77a48ae01bbc5b05ca009cf09e2fcb53e4c8ff23", "tree": "780c7d6bdee784c2f8248979de348491cfb63b34", "parents": [ "659562aaf133c41b8d90ec9216c07646f0f14362" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Sep 15 12:34:04 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Sep 15 12:34:04 2015 +0000" }, "message": "Revert \"Revert \"ART: Register allocation and runtime support for try/catch\"\"\n\nThe original CL triggered b/24084144 which has been fixed\nby Ib72e12a018437c404e82f7ad414554c66a4c6f8c.\n\nThis reverts commit 659562aaf133c41b8d90ec9216c07646f0f14362.\n\nChange-Id: Id8980436172457d0fcb276349c4405f7c4110a55\n" }, { "commit": "659562aaf133c41b8d90ec9216c07646f0f14362", "tree": "be1beae390262bf2f5a17bfa44de93081a849d07", "parents": [ "b022fa1300e6d78639b3b910af0cf85c43df44bb" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Sep 14 21:26:33 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Sep 14 21:26:33 2015 +0000" }, "message": "Revert \"ART: Register allocation and runtime support for try/catch\"\n\nBreaks libcore test org.apache.harmony.security.tests.java.security.KeyStorePrivateKeyEntryTest#testGetCertificateChain. Need to investigate.\n\nThis reverts commit b022fa1300e6d78639b3b910af0cf85c43df44bb.\n\nChange-Id: Ib24d3a80064d963d273e557a93469c95f37b1f6f\n" }, { "commit": "b022fa1300e6d78639b3b910af0cf85c43df44bb", "tree": "780c7d6bdee784c2f8248979de348491cfb63b34", "parents": [ "e481c006e8b055a31d9c7cff27f4145e57e3c113" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Aug 20 17:47:48 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Sep 14 20:42:58 2015 +0100" }, "message": "ART: Register allocation and runtime support for try/catch\n\nThis patch completes a series of CLs that add support for try/catch\nin the Optimizing compiler. With it, Optimizing can compile all\nmethods containing try/catch, provided they don\u0027t contain catch loops.\nFuture work will focus on improving performance of the generated code.\n\nSsaLivenessAnalysis was updated to propagate liveness information of\ninstructions live at catch blocks, and to keep location information on\ninstructions which may be caught by catch phis.\n\nRegisterAllocator was extended to spill values used after catch, and\nto allocate spill slots for catch phis. Catch phis generated for the\nsame vreg share a spill slot as the raw value must be the same.\n\nLocation builders and slow paths were updated to reflect the fact that\nthrowing an exception may not lead to escaping the method.\n\nInstruction code generators are forbidden from using of implicit null\nchecks in try blocks as live registers need to be saved before handing\nover to the runtime.\n\nCodeGenerator emits a stack map for each catch block, storing locations\nof catch phis. CodeInfo and StackMapStream recognize this new type of\nstack map and store them separate from other stack maps to avoid dex_pc\nconflicts.\n\nAfter having found the target catch block to deliver an exception to,\nQuickExceptionHandler looks up the dex register maps at the throwing\ninstruction and the catch block and copies the values over to their\nrespective locations.\n\nThe runtime-support approach was selected because it allows for the\nbest performance in the normal control-flow path, since no propagation\nof catch phi values is necessary until the exception is thrown. In\naddition, it also greatly simplifies the register allocation phase.\n\nConstantHoisting was removed from LICMTest because it instantiated\n(now abstract) HConstant and was bogus anyway (constants are always in\nthe entry block).\n\nChange-Id: Ie31038ad8e3ee0c13a5bbbbaf5f0b3e532310e4e\n" }, { "commit": "6058455d486219994921b63a2d774dc9908415a2", "tree": "3d205227f3ff54cd3a50bc5c0e7cb3ad6c175b86", "parents": [ "637ee0b9c10ab7732a7ee7b8335f3fff4ac1549c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 03 13:35:12 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 08 18:09:49 2015 +0100" }, "message": "Optimizing: Tag basic block allocations with their source.\n\nReplace GrowableArray with ArenaVector in HBasicBlock and,\nto track the source of allocations, assign one new and two\nQuick\u0027s arena allocation types to these vectors. Rename\nkArenaAllocSuccessor to kArenaAllocSuccessors.\n\nBug: 23736311\nChange-Id: Ib52e51698890675bde61f007fe6039338cf1a025\n" }, { "commit": "145acc5361deb769eed998f057bc23abaef6e116", "tree": "3d66a0b44e1ac927156eec6e6488de5fd52b982b", "parents": [ "91e11c0c840193c6822e66846020b6647de243d5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 03 13:33:25 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 03 13:33:25 2015 +0000" }, "message": "Revert \"Optimizing: Tag basic block allocations with their source.\"\n\nReverting so that we can have more discussion about the STL API.\n\nThis reverts commit 91e11c0c840193c6822e66846020b6647de243d5.\n\nChange-Id: I187fe52f2c16b6e7c5c9d49c42921eb6c7063dba\n" }, { "commit": "91e11c0c840193c6822e66846020b6647de243d5", "tree": "0c5398ef59c464c1848afd0113c74b6aeb75cf42", "parents": [ "f9f6441c665b5ff9004d3ed55014f46d416fb1bb" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 02 17:03:22 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 03 13:09:37 2015 +0100" }, "message": "Optimizing: Tag basic block allocations with their source.\n\nReplace GrowableArray with ArenaVector in HBasicBlock and,\nto track the source of allocations, assign one new and two\nQuick\u0027s arena allocation types to these vectors. Rename\nkArenaAllocSuccessor to kArenaAllocSuccessors.\n\nBug: 23736311\nChange-Id: I984aef6e615ae2380a532f5c6726af21015f43f5\n" }, { "commit": "2e92bc2ba2446525a07f5172d1cd30ab49d26cd6", "tree": "18ea6a6719555fee1b9bc4eb8f40f8850dd36714", "parents": [ "cbddb90e515c30983094378e316e446b9edca5d6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 20 19:52:26 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 21 15:23:16 2015 +0100" }, "message": "Fix TrySplitNonPairOrUnalignedPairIntervalAt.\n\nWe need to both:\n1) Look at pair that don\u0027t start at an even register.\n2) Also remove the other half from the list of actives.\n\nChange-Id: Ia99fa9852c67b8633e8d17a258fe302add54b14a\n" }, { "commit": "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0", "tree": "887b7a75c8ce60f31ae3b43a2e8f41335e9ce760", "parents": [ "1def08ee2f1189ddcb73f72211afb223142d173f", "da2b254fe4c35986d85876c5819b1114e25140cb" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 14 10:54:56 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 14 10:54:56 2015 +0000" }, "message": "Merge \"Fix a bug in the register allocator when allocating pairs.\"" }, { "commit": "da2b254fe4c35986d85876c5819b1114e25140cb", "tree": "2ec2cb94bdf02fa66bfc8bbd79cb3810dbdcce16", "parents": [ "d2606b1b922573d45707931bc387cbf990771238" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 06 19:56:45 2015 -0700" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Aug 11 14:17:44 2015 -0700" }, "message": "Fix a bug in the register allocator when allocating pairs.\n\nbug:22913897\nChange-Id: I402d8a29a482f6cb98c8d1fcdcbf0eddf744e038\n" }, { "commit": "f29758111e71a7d14f3e52d78773561a5d59961f", "tree": "644efb1559c2a4ecd083128e86086d0e896ca761", "parents": [ "3ded7766981b3105c7686e0c9d75c378c42fa4a0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 07 18:13:03 2015 -0700" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 07 18:15:18 2015 -0700" }, "message": "Fix a bug in the register allocator around pair allocation.\n\nWe may get hints that do not work with the current implementation\nof register pairs, which forces the allocation of (low + 1)\nfor the high register. For example, if the hint is EBX, we will\nallocate ESP for the high register.\n\nbug:23043730\n\nChange-Id: I371ebb0c61568f09d12eb9ab815c0bf0ea02d49b\n" }, { "commit": "8158f28b6689314213eb4dbbe14166073be71f7e", "tree": "fced445e53f639b2db42cb5a0e96d5aa04750861", "parents": [ "33407564904d2186f536107e1ca8d88f2c760c83" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Aug 07 10:26:17 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Aug 07 10:26:17 2015 +0100" }, "message": "Ensure coherency of call kinds for LocationSummary.\n\nThe coherency is enforced with checks added in the `InvokeRuntime`\nhelper, that we now also use on x86 and x86_64.\n\nChange-Id: I8cb92b042f25dc3c5fd390e9c61a45b477d081f4\n" }, { "commit": "45b83aff85a8a8dfcae0da90d010fa2d7eb299a7", "tree": "ab9859f385b166831204d002878677d3cd30a031", "parents": [ "f7aa6c05a1c7d70182d43abaf3ff43b6d463eec0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 06 15:12:53 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 06 16:20:59 2015 +0100" }, "message": "Revert \"Revert \"Fix LSRA bug with explicit register temporaries\"\"\n\nThis reverts commit a5fc140ff315dda9bc0a8e59963ed547676cd941.\n\nChange-Id: Ic322484176e55d0c7cd7250d629b9e5046006a4f\n" }, { "commit": "a5fc140ff315dda9bc0a8e59963ed547676cd941", "tree": "fd82c469e06a21bd1274dccc2d98f0613e45c51f", "parents": [ "283b8541546e7673d33d104241623d07c91cf500" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jul 06 15:09:54 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jul 06 15:09:54 2015 +0000" }, "message": "Revert \"Fix LSRA bug with explicit register temporaries\"\n\nregister_allocator_test32 fails.\n\nThis reverts commit 283b8541546e7673d33d104241623d07c91cf500.\n\nChange-Id: I2a46f3c68de3e8273e402102065c13797045c481\n" }, { "commit": "283b8541546e7673d33d104241623d07c91cf500", "tree": "ef57722d3b0ea62c079b014c6ca3636fb4e5d54d", "parents": [ "51f38e3adf58ba4e35b5374fb8c4b87cb3112abd" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jul 03 08:26:41 2015 -0400" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 06 14:50:50 2015 +0100" }, "message": "Fix LSRA bug with explicit register temporaries\n\nA temporary with an explicit RegisterLocation, such as ESI on x86 didn\u0027t\nhave the register marked as allocated. This caused it to not be\nsaved/restored in the prologue/epilogue, causing problems in the caller\nroutine, which expected it to be saved. Found while implementing\nhttps://android-review.googlesource.com/#/c/157522/.\n\nChange-Id: I22ca2b24c2d21b1c6ab6cfb7dec26cb38034a891\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "4dda3376b71209fae07f5c3c8ac3eb4b54207aa8", "tree": "0d96a327d1b3a7e09eff178a66c0b5fb946cfc85", "parents": [ "71af6f7aab7491665fe2d6beb9af4c251a99ad56" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 01 18:31:49 2015 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 19 15:43:58 2015 +0100" }, "message": "MIPS: Initial version of optimizing compiler for MIPS64R6.\n\nBug: 21555893\nChange-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf\nSigned-off-by: Alexey Frunze \u003cAlexey.Frunze@imgtec.com\u003e\nSigned-off-by: Douglas Leung \u003cdouglas.leung@imgtec.com\u003e\n" }, { "commit": "94015b939060f5041d408d48717f22443e55b6ad", "tree": "3dfe8b3d8535508694dd451acdd1ff887dfa4662", "parents": [ "6a1c92f1e4a455d802ab0d0ac47504cdd7c12f0f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 18:21:04 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 08 18:20:41 2015 +0100" }, "message": "Revert \"Revert \"Use HCurrentMethod in HInvokeStaticOrDirect.\"\"\n\nFix was to special case baseline for x86, which does not have enough\nregisters to allocate the current method.\n\nThis reverts commit c345f141f11faad177aa9635a78088d00cf66086.\n\nChange-Id: I5997aa52f8d4df373ae5ff4d4150dac0c44c4c10\n" }, { "commit": "c345f141f11faad177aa9635a78088d00cf66086", "tree": "0a9fbb0f1f90dfe273d94659f077cc1e6b84966c", "parents": [ "38207af82afb6f99c687f64b15601ed20d82220a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 17:17:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 17:17:32 2015 +0000" }, "message": "Revert \"Use HCurrentMethod in HInvokeStaticOrDirect.\"\n\nFails on baseline/x86.\n\nThis reverts commit 38207af82afb6f99c687f64b15601ed20d82220a.\n\nChange-Id: Ib71018367eb7c6046965494a7e996c22af3de403\n" }, { "commit": "38207af82afb6f99c687f64b15601ed20d82220a", "tree": "f9360949b92e5b6b01c5828c03ac67d01adffe1d", "parents": [ "6a0d5e7fe6dc0c9d3dd941ab991203f2d5d1c354" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 01 15:46:22 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 14:39:06 2015 +0100" }, "message": "Use HCurrentMethod in HInvokeStaticOrDirect.\n\nChange-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66\n" }, { "commit": "8272688499c2232355db34d94057983fd436173d", "tree": "aabd5c474fe53eb6d73edc6c0d1d8a00b1256eb6", "parents": [ "a96bea54b7e3def5490d169f2bf92be2e68dd001" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 01 13:51:57 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 01 14:03:51 2015 +0100" }, "message": "Tweak one hint and one split in the linear scan.\n\n- Return a hinted register if it is available. Otherwise\n another move will be necessary.\n- Use SplitBetween instead of raw split when a register\n is not fully available. This will find the best split\n position.\n\nChange-Id: Ie464e536204ab556eb09345fe6426621eb86e5ac\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "d23eeef3492b53102eb8093524cf37e2b4c296db", "tree": "57d3e9ab2853d5b8092568bb3d29bc850c113315", "parents": [ "a15c78d3cc28f514a482ffd792a767e97fe53c95" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 22:31:29 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 29 14:15:04 2015 +0100" }, "message": "Support for inlining methods that call/throw.\n\nMostly fixes here and there to make it working.\n\nChange-Id: I1b535e895105d78b65634636d675b818551f783e\n" }, { "commit": "76b1e1799a713a19218de26b171b0aef48a59e98", "tree": "897d0d22d246367eb09d8b825b43c384074083f4", "parents": [ "382f5c24eb663ca8fa39a94a038349138a00272a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 27 17:18:33 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 28 10:44:36 2015 +0100" }, "message": "Add a HCurrentMethod node.\n\nThis enables register allocation for the current method, so\nthat users of it don\u0027t always load it from the stack.\n\nCurrently only used by HLoadClass. Will make follow-up\nCLs for the other users.\n\nChange-Id: If73324d85643102faba47fabbbd2755eb258c59c\n" }, { "commit": "8826f67ad53099021f6442364348fa66729288d7", "tree": "3f937444d251efa09174ddb586c0eed6918907f6", "parents": [ "ef4366a159ecdd357c98e577583bbe224d065128" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Apr 17 09:15:11 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 10:22:45 2015 +0100" }, "message": "Callee/caller save logic in register allocator.\n\nPrevent intervals that do not span a \u0027will-call\u0027 safepoint\nto allocate a callee-save register when caller-saves\nare available.\n\nChange-Id: I6e613ab54b087f433bbc433aa62847fbca423377\n" }, { "commit": "0a23d74dc2751440822960eab218be4cb8843647", "tree": "39d69de5d812826c4065d0acd38a58cd983f21f0", "parents": [ "cdeb0b5fede4c06488f43a212591e661d946bc78" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 07 11:57:35 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 11 14:17:22 2015 +0100" }, "message": "Add a parent environment to HEnvironment.\n\nThis code has no functionality change. It adds a placeholder\nfor chaining inlined frames.\n\nChange-Id: I5ec57335af76ee406052345b947aad98a6a4423a\n" }, { "commit": "fbda5f3e1378f07ae202f62da625ee43a063a052", "tree": "4c6b9dbadbdf409a878da05bd3d765f9cb55653a", "parents": [ "008b17ae313d033537a3792faf937134315f03bc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 29 14:16:00 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 05 10:24:17 2015 +0100" }, "message": "Find better split positions in the register allocator.\n\nIn a standard if/else control flow graph, this avoids\ndoing a move in one branch if the other branch decided\nto move an interval.\n\nThis also needs a new register hint kind, which is what\nwas the location of the interval at the predecessor block.\n\nChange-Id: I18b78264587b4d693540fbb5e014d12df2add3e2\n" }, { "commit": "579026039080252878106118645ed70706f4838e", "tree": "cfedba53d8e8b04e81b855560e388f3f691ee837", "parents": [ "2d01066db24c19f9384f50ff71806cbb4835c7f9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Apr 21 14:28:41 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 29 18:02:36 2015 +0100" }, "message": "Add synthesize uses at back edge.\n\nThis reduces the cost of linearizing the graph (hence removing\nthe notion of back edge). Since linear scan allocates/spills registers\nbased on next use, adding a use at a back edge ensures we do count\nfor loop uses.\n\nChange-Id: Idaa882cb120edbdd08ca6bff142d326a8245bd14\n" }, { "commit": "4ed947a58de87d19d0609be773207c905ccb0f7f", "tree": "27770da4f79f5764a2700135671bcfff8f0bdddf", "parents": [ "a0ee862288b702468f8c2b6d0ad0f1c61be0b483" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 27 16:58:06 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 27 17:50:50 2015 +0100" }, "message": "Dissociate uses with environment uses.\n\nThey are most of the times in the way when iterating. They\nalso complicate the logic of (future) back edge uses.\n\nChange-Id: I152595d9913073fe901b267ca623fa0fe7432484\n" }, { "commit": "8cbab3c4de3328b576454ce702d7748f56c44346", "tree": "8d95b5f6d451983350839a2b294b4bc869bd852a", "parents": [ "b4186df6c48a88ad8028fcf9e1dac5ce6c391de2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 23 15:14:36 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 23 18:27:05 2015 +0100" }, "message": "Linear scan: split at better positions.\n\n- Split at block entry to piggy back on control flow resolution.\n- Split at the loop header, if the split position is within a loop.\n\nChange-Id: I718299a58c02ee02a1b22bda589607c69a35f0e8\n" }, { "commit": "769f2d32e4b04758e4dd6ce967f779cbfa74dbcb", "tree": "b0c764ec60cf2f6d7e06babad59e8d8bb32dd98d", "parents": [ "3d052ba48f84901e89b5ea94c133093dc80bad06", "1ba1981ee9d28f87f594b157566d09e973fa5bce" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Apr 21 10:19:21 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 21 10:19:21 2015 +0000" }, "message": "Merge \"Linear scan: Use FirstUse instead of FirstRegisterUse.\"" }, { "commit": "1ba1981ee9d28f87f594b157566d09e973fa5bce", "tree": "f131757efaab85fb2a1efbac786c968a1f4a0283", "parents": [ "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Apr 21 09:12:40 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Apr 21 10:48:57 2015 +0100" }, "message": "Linear scan: Use FirstUse instead of FirstRegisterUse.\n\nThis is in preparation for introducing synthesized used at back edges.\n\nChange-Id: Ie28d6725d2dde982cf2137f2110daabcbab9f789\n" }, { "commit": "3fc992f9dfe8f49ff350132323cc635f102b7b62", "tree": "d5fdfaed3d79b435dc0b674d60565f1719b2a416", "parents": [ "81b13f6b5244b664000d4bcad16920aadf3b7e29" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 16 18:31:55 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Apr 17 17:13:57 2015 +0100" }, "message": "ART: Improve range search caching in LiveInterval\n\nRegister allocator spends too long in LiveInterval queries. This patch\nbuilds on previously introduced caching of range search results to\nfurther speed up LiveInterval\u0027s Covers and FindIntersectionWith.\nOnly calls which are guaranteed to query the current-\u003eGetStart()\nposition are cached. Other calls are replaced with CoversSlow which\nsearches through the entire list of ranges.\n\nChange-Id: I84d92b526e174caa70d6477497a06afd85016c4a\n" }, { "commit": "241a486267bdb59b32fe4c8db370eb936068fb39", "tree": "ea8edc6b55285340ae58bc00f283e8fcaaff3c22", "parents": [ "f90b8548e91392dfc24e8b0f7d3000f4f121c19d" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 16 17:59:03 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 16 18:13:01 2015 +0100" }, "message": "ART: Replace expensive calls to Covers in reg alloc\n\nLiveInterval::Covers is implemented as a linear-time search over\nliveness ranges and can therefore be rather expensive and should be\navoided unless necessary. This patch replaces calls to Covers when\nsearching for a sibling with the cheaper IsDefinedAt call.\n\nChange-Id: I93fc73529c15a518335f4cbdc3a0def52d9501e5\n" }, { "commit": "43af728a3ccecb5f0eacef85f44d70df3d4c40f9", "tree": "3273730f5995659ecb8cdba626fa4fa10e0986ef", "parents": [ "3e6f1c41220c84f31479a88aa37882307244110b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 16 13:01:01 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 16 13:01:01 2015 +0100" }, "message": "Split safepoint positions to avoid calling Covers.\n\nThis is also in preparation for caller/callee save based\nregister allocation.\n\nChange-Id: I63954bdae5ea7870568fd93b4d11e1c9dcd6de6f\n" }, { "commit": "a76a08fed88bd081bcc4d240f1ba3472a2acbbab", "tree": "cd016bb007c3757ab2a6df28bc1a65d6a8e78e44", "parents": [ "acf9b7b7616a9b104e6f2146051d8e14d9cb9030", "9021825d1e73998b99c81e89c73796f6f2845471" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 14:10:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 15 14:10:29 2015 +0000" }, "message": "Merge \"Type MoveOperands.\"" }, { "commit": "0d9f17de8f21a10702de1510b73e89d07b3b9bbf", "tree": "3d58a2a165ee2bc5af0e813b1ffa893fba72ed6d", "parents": [ "9bb3e8e10d7d9230a323511094a9e260062a1473" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 14:17:44 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 14:17:44 2015 +0100" }, "message": "Move the linear order to the HGraph.\n\nBug found by Zheng Xu: SsaLivenessAnalysis being a stack allocated\nobject, we should not refer to it in later phases of the compiler.\nSpecifically, the code generator was using the linear order, which\nwas stored in the liveness analysis object.\n\nChange-Id: I574641f522b7b86fc43f3914166108efc72edb3b\n" }, { "commit": "9021825d1e73998b99c81e89c73796f6f2845471", "tree": "13e1038931cbb8bf8b8d0f4e3f51553ba1bfa983", "parents": [ "858d28ca2e73a785977f53141e775a7d4841b89d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 11:56:51 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 12:53:42 2015 +0100" }, "message": "Type MoveOperands.\n\nThe ParallelMoveResolver implementation needs to know if a move\nis for 64bits or not, to handle swaps correctly.\n\nBug found, and test case courtesy of Serguei I. Katkov.\n\nChange-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506\n" }, { "commit": "5588e588144fffc978845a2c9c915a0044565a03", "tree": "b4346bb9e3a6fb93ed9a76f7caa1b9f72e4c9746", "parents": [ "6fea0097be6aefb0a1faf9eaf24cfbadda0959a5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Apr 14 14:10:59 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 10:16:07 2015 +0100" }, "message": "Refactor safepoints in register allocator.\n\nThis is in preparation for adding logic around callee/caller\nsaved in the register allocator.\n\nChange-Id: I4204169f0a6a01074880538833144be7b0810882\n" }, { "commit": "5aab7cb5368b2ae4f513e8d58208b1eac990aa15", "tree": "a8f5f64cbbc7dbaa4915a5b24f0240b12bdc480d", "parents": [ "6b63e92f00220a008ef8bbc77912129a709771f8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 31 23:06:28 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 31 23:06:28 2015 +0100" }, "message": "Fix lint error.\n\nChange-Id: I39dda83acd755b2c95453b3b0f7774bc9d18546e\n" }, { "commit": "d8126bef62df7f40f2e6abc74004f52e664daf45", "tree": "8e3d3eee847f8376541ddabc5274bd84bd13311d", "parents": [ "ef3456f872539df65c4c88ca346713f74366d803" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 10:22:41 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 31 20:40:19 2015 +0100" }, "message": "Fix locations at environment uses.\n\nWe were too agressive in not recording environment uses\nwhen the instruction was not of type object. We have to\nrecord the use to the use list of an interval, but it should\nnot affect the live ranges of that interval.\n\nChange-Id: Id16fb7cc06f14083766d408a345837793583b6ea\n" }, { "commit": "acb4ea0a7f7a0b75cf6eddd619a3e6002b46347e", "tree": "cc60040e10610964e5d69b4b4f4be9e3823a157e", "parents": [ "5bb214b6cd25809de2a4d62607ce69cd16587678", "f01d34445953e6b9c9b13de1dd32a5c0ee5abab5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 30 14:53:42 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Mar 30 14:53:43 2015 +0000" }, "message": "Merge \"Implement a proper solution for temps.\"" }, { "commit": "5b168deeae2c5a8a566ce5c140741f0e2227af21", "tree": "4a572dfc6932d1f478eae594801c59af11628ef8", "parents": [ "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 10:27:22 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 30 12:45:58 2015 +0100" }, "message": "Fix user-build on fugu.\n\nCalling Delete on an array shifts the elements, so when iterating\nover inactives and removing entries we need to decrement for\nthe found interval, but also its potential other half. The code\nused to not decrement for the other half\n\nChange-Id: Idcb1533643c11a37ed4f459fe88aaef208a4bfd6\n" }, { "commit": "f01d34445953e6b9c9b13de1dd32a5c0ee5abab5", "tree": "86f4aaf006f125fdee6e83d494df381b0c38c658", "parents": [ "7d8c6776d7bdcc04411154aa215ba5909939192a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 17:15:49 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 17:22:37 2015 +0000" }, "message": "Implement a proper solution for temps.\n\nWe used to play some trickery when updating locations of temps. This\nchange creates a proper use of the temp, and use it for updating\nits location.\n\nChange-Id: I53e9447b87a55137a3a79841db21ad3864854825\n" }, { "commit": "234d69d075d1608f80adb647f7935077b62b6376", "tree": "f6b68ff38722dc91bd0de2387609ee0ce950e0ce", "parents": [ "31df246d330c45f5691e226d176d0c59450f8435" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 09 10:28:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 11 14:23:38 2015 +0000" }, "message": "Revert \"Revert \"[optimizing] Enable x86 long support.\"\"\n\nThis reverts commit 154552e666347d41d95d7619c6ee56249ff4feca.\n\nChange-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13\n" }, { "commit": "0e242b5cad3c0b68b72f28c1e5fd3fdd4c05bfd8", "tree": "1446f5a1ec95cf1c641228fd7dc2fecb67962723", "parents": [ "7e5b740cc387645c6b2e0dc8604b1e074c398b4d", "154552e666347d41d95d7619c6ee56249ff4feca" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:31 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 06 16:10:32 2015 +0000" }, "message": "Merge \"Revert \"[optimizing] Enable x86 long support.\"\"" }, { "commit": "154552e666347d41d95d7619c6ee56249ff4feca", "tree": "b8bdb820be33317f23ef1d3e43d13b2b6bfb3ba5", "parents": [ "b4ba354cf8d22b261205494875cc014f18587b50" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:14 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:14 2015 +0000" }, "message": "Revert \"[optimizing] Enable x86 long support.\"\n\nFew libcore failures.\n\nThis reverts commit b4ba354cf8d22b261205494875cc014f18587b50.\n\nChange-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63\n" }, { "commit": "b265262780ef7384bdcd1413cde2a59f7594cec9", "tree": "ded0752013a32e0a071ca508f2fd23e5287f328e", "parents": [ "6626f89db7158d864c2f93d0e7682e6e6fa4b2c2", "b4ba354cf8d22b261205494875cc014f18587b50" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 11:42:25 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 06 11:42:26 2015 +0000" }, "message": "Merge \"[optimizing] Enable x86 long support.\"" }, { "commit": "b4ba354cf8d22b261205494875cc014f18587b50", "tree": "b6ce1e89f56f4d5adf238188df5b02fd7e2c23ac", "parents": [ "af8db2ea18135588b267fe9a0b2f7af734b906cc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 05 11:28:58 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 11:37:33 2015 +0000" }, "message": "[optimizing] Enable x86 long support.\n\nChange-Id: I9006972a65a1f191c45691104a960366747f9d16\n" }, { "commit": "df45205204125727fa71b17b3f6bb3d8eb9bc20c", "tree": "224b4ba87f27dfca80d119e84b5ffd2866097657", "parents": [ "ea19b3696f90e07c72acb383f84305ace9b16097" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Mar 05 15:34:41 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Mar 05 15:47:58 2015 +0000" }, "message": "ART: Fix test breakage\n\nRecent commit changed the direction of iteration over safepoints in\nthe register allocator but contained a bug that skipped some of them\nat the boundaries of interval siblings. This patch fixes the bug.\n\nChange-Id: Ia7d4892536b5198e01c9bc3034f448227794ff72\n" }, { "commit": "9a9ab61ca425298f161872ed8efcf0a89b158ab2", "tree": "2b1ddc995cba6ab9fa9fce2b04463dd9b504307e", "parents": [ "af8db2ea18135588b267fe9a0b2f7af734b906cc" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 03 10:44:24 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Mar 05 14:27:31 2015 +0000" }, "message": "ART: Optimize iteration of safepoints\n\nThe LiveInterval::Covers method is optimized for multiple calls with\nnon-decreasing positions. This patch reverts the order of iteration\nover safepoints in RegisterAllocator::ConnectSiblings to capitalize\non this effect.\n\nChange-Id: Ieb70eb9d5c0a06ee79379aab6c87cb3290c15bf7\n" }, { "commit": "776b3184ee04092b11edc781cdb81e8ed60601e3", "tree": "98458c7087866b988468f5d356550ff14f2ee3af", "parents": [ "1382e569b31f4fab61fcfca5aa93275a2a3cb757" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 23 14:14:57 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 23 14:56:07 2015 +0000" }, "message": "Each primitive kind now spills to different locations.\n\nHaving different slots depending on the types greatly simplifies\nthe parallel move resolver. It also avoids doing FPU \u003c-\u003e Core\nregister swaps, and force backends to implement such a swap.\n\nChange-Id: Ide9f0452e7ccf9efb8adddbcc246d44b937b253c\n" }, { "commit": "c0572a451944f78397619dec34a38c36c11e9d2a", "tree": "2cc6f3c6f5ad45b4b85fb62627e797fe7e7734e1", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 14:35:25 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 17:37:57 2015 +0000" }, "message": "Optimize leaf methods.\n\nAvoid suspend checks and stack changes when not needed.\n\nChange-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628\n" }, { "commit": "829280cc90b7a84db42864589b4bafb4c94a79d9", "tree": "8c6f0235011e046bc711ebf795678f6d1a2fedda", "parents": [ "69d69ea40fe64ff2e70daffc365a2fffe5964fcc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 28 10:20:37 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 04 09:11:40 2015 +0000" }, "message": "Finally implement Location::kNoOutputOverlap.\n\nThe [i, i + 1) interval scheme we chose for representing\nlifetime positions is not optimal for doing this optimization.\nIt however doesn\u0027t prevent recognizing a non-split interval\nduring the TryAllocateFreeReg phase, and try to re-use\nits inputs\u0027 registers.\n\nChange-Id: I80a2823b0048d3310becfc5f5fb7b1230dfd8201\n" }, { "commit": "4c204bafbc8d596894f8cb8ec696f5be1c6f12d8", "tree": "3608d188815a8a80e86f98611edcfe3bbaad8b17", "parents": [ "08029544d72bd9bec162956978afcb59204ea97b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 03 15:12:35 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 03 17:13:17 2015 +0000" }, "message": "Use a different block order when not compiling baseline.\n\nUse the linearized order instead, as it puts blocks logically\nnext to each other in a better way. Also, it does not contain\ndead blocks.\n\nChange-Id: Ie65b56041a093c8155e6c1e06351cb36a4053505\n" }, { "commit": "7c8d009552545e6f1fd6036721e4e42e3fd14697", "tree": "f7290aba6a1dcb008af1388f582d422fe1c07ff6", "parents": [ "763abfd0d803f8169e97d3da944043c2464aac0a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Jan 26 11:21:33 2015 -0500" }, "committer": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 28 00:48:50 2015 +0000" }, "message": "[optimizing compiler] Support x86 hard float ABI\n\nAdd support for the new ABI passing FP parameters in XMM0-XMM3. This\nallows us to optimize for x86 methods that don\u0027t use \u0027long\u0027.\n\nChange-Id: Ic79a24767173451e7d7095ccc2a00b307593a868\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "6c2dff8ff8e1440fa4d9e1b2ba2a44d036882801", "tree": "da2d48b3d84733ac6b29194cb2f624693a643d48", "parents": [ "22c9285142169691eb2a9e2d4a49751fc7e57c2a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 14:56:54 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 15:19:06 2015 +0000" }, "message": "Revert \"Revert \"Fully support pairs in the register allocator.\"\"\n\nThis reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f.\n\nChange-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5\n" }, { "commit": "c399fdc442db82dfda66e6c25518872ab0f1d24f", "tree": "6f0841ad5e8e80b09e34e084ae8eac336bce73a2", "parents": [ "41aedbb684ccef76ff8373f39aba606ce4cb3194" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "message": "Revert \"Fully support pairs in the register allocator.\"\n\nLibcore tests fail.\n\nThis reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194.\n\nChange-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c\n" }, { "commit": "41aedbb684ccef76ff8373f39aba606ce4cb3194", "tree": "94929237a0fe9b24dda7409d9433f07e82af4461", "parents": [ "97c89e4c081dcf4bacbde70b6609e366c9da417e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 10:49:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 11:27:57 2015 +0000" }, "message": "Fully support pairs in the register allocator.\n\nEnabled on ARM for longs and doubles.\n\nChange-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b\n" }, { "commit": "42d1f5f006c8bdbcbf855c53036cd50f9c69753e", "tree": "fb885c3df20797b55f19e5ceccf72dac1c13017b", "parents": [ "36740379b9b1c81b7eb06ea9c9df411d0a9a765e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 09:14:18 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 11:22:08 2015 +0000" }, "message": "Do not use register pair in a parallel move.\n\nThe ParallelMoveResolver does not work with pairs. Instead,\ndecompose the pair into two individual moves.\n\nChange-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f\n" }, { "commit": "6a5f5b25b3866966175859bc20216c5519d8b029", "tree": "b8d60df229a56e3931eaa0486f4451fe9818786d", "parents": [ "ddcaf45db2874ffc37d2a8820e815db19a54c517", "dd8f887e81b894bc8075d8bacdb223747b6a8018" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 08:41:30 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jan 16 08:41:31 2015 +0000" }, "message": "Merge \"Fix a bug in the register allocator.\"" }, { "commit": "dd8f887e81b894bc8075d8bacdb223747b6a8018", "tree": "2358f04f707177fc5b1a8463973ddd5f295d6e72", "parents": [ "63991dd7c9bd68f23121e420c005628d7307cba3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 15 15:37:37 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 08:37:59 2015 +0000" }, "message": "Fix a bug in the register allocator.\n\nWhen allocating a register blocked by existing intervals,\nwe need to split inactive intervals at the end of their\nlifetime hole, and not at the next intersection. Otherwise,\nthe allocation for following intervals will not see\nthat a register is being used by the split interval.\n\nChange-Id: I40cc79dde541c07392a7cf4c6f0b291dd1ce1819\n" }, { "commit": "71fb52fee246b7d511f520febbd73dc7a9bbca79", "tree": "444d91e910433aaf887bbdada28dfaa3160bebc2", "parents": [ "420457e6040184a6e1639a4c84fcc8e237bd8a3d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 29 17:43:08 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 10:21:11 2015 -0800" }, "message": "ART: Optimizing compiler intrinsics\n\nAdd intrinsics infrastructure to the optimizing compiler.\n\nAdd almost all intrinsics supported by Quick to the x86-64 backend.\nFurther intrinsics require more assembler support.\n\nChange-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807\n" }, { "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd", "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 13 09:20:58 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 15 11:21:37 2015 -0500" }, "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine. This fails for X86,\nwhere a double in an XMM register takes up 8 bytes. Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce", "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518", "parents": [ "893e8881e31180721512c1b9e5ffacb03aad2e45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 07 16:01:24 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 13:57:51 2015 +0000" }, "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n" }, { "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c", "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955", "parents": [ "776b880f66edb21cb3b4225877e494ec7a9ec1a2" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 10:36:50 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 14:36:14 2014 +0000" }, "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7" }, { "commit": "5976857e65d3d0e7be0c4e3183e9483c85a76bb8", "tree": "33dd2712eaf12ce49db7bfe2d0737122c21e4ed4", "parents": [ "7933e185ebd4efab7f7e0749bfa193f08152c614" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 09:50:04 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 11:25:41 2014 +0000" }, "message": "Fix insertion of parallel move when connecting siblings.\n\nAlso add a check that ensures parallel moves have been inserted\ncorrectly.\n\nThis fixes tests:\norg.apache.harmony.tests.java.util.BitSetTest#test_nextSetBitI\norg.apache.harmony.tests.java.util.BitSetTest#test_31036_set\n\nOn host/x64.\n\nChange-Id: I59d29aca393b5344bac933e2813ab409fea9d9b5" }, { "commit": "eea79dd779ba199658ada7264f8f96d776e53f19", "tree": "f7317c36141deb11bf7cdcc7afd7b230491e82d5", "parents": [ "9ce56af31bef386944b7e76ab46897b3573a80d1", "46fbaab1bf2981f2768b046abf43e368663daacd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 28 11:26:24 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Nov 28 11:26:25 2014 +0000" }, "message": "Merge \"Fix a bug in the linear scan register allocator.\"" }, { "commit": "9ce56af31bef386944b7e76ab46897b3573a80d1", "tree": "69024d8c6b23e6c60b25ee6511c67f5e5332b5a4", "parents": [ "db5453bbda97e94c00af714a7ec8e59d3a4ea843", "acd033994aced8246c2fd8e931340dbf82d06d1a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 28 11:07:27 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Nov 28 11:07:28 2014 +0000" }, "message": "Merge \"Fix bogus assumption for live registers at safe point.\"" }, { "commit": "199f336af1fc8212646fda67675df0361ece33d6", "tree": "e8709a668b285246ab7d7f4c3f8f2553fd5f39e2", "parents": [ "924632d2626b17b903bf7b851099f6d575ac534b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 17:15:16 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 17:15:16 2014 +0000" }, "message": "Wrap long lines in the optimizing compiler.\n\nChange-Id: I5dee0c65e6652de574ae952b1f1dfc7355859e45\n" }, { "commit": "5368c219a462defc90c4b896b34eb7506ba5c142", "tree": "6374d21b8ac88f3a0f001a7fbda4a1769572c879", "parents": [ "d7fa3a7d26105dd112acf955a0c7a880a6027180" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 15:03:41 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 15:03:41 2014 +0000" }, "message": "Fix neg-float \u0026 neg-double for null values in opt. compiler.\n\n- Implement float and double negation as an exclusive or\n with a bit sign mask in x86 and x86-64 code generators.\n- Enable requests of temporary FPU (double) registers during\n register allocation.\n- Update test cases in test/415-optimizing-arith-neg.\n\nChange-Id: I9572c24b27c645ba698825e60cd5b3956b4895fa\n" } ], "next": "46fbaab1bf2981f2768b046abf43e368663daacd" }