)]}' { "log": [ { "commit": "3c89d4234589816fb7dafb5215543f2cf023ce6c", "tree": "a9f6429ffd6625203bdba9c01520b6a5e64ac539", "parents": [ "1fed1dc7b1ea75b0465c0b2b3457718aab5a0f34" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Feb 17 11:30:23 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Feb 17 11:32:59 2017 +0000" }, "message": "x86/string compression: Use TESTB instead of TESTL in String.charAt().\n\nAnd fix disassembly of the now unused TESTL.\n\nTest: testrunner.py --host with string compression enabled.\nTest: Manual inspection of dump-oat output.\nBug: 35433135\nBug: 31040547\nChange-Id: I36c955bc1f2243954ecc315266a2f3fce5d87693\n" }, { "commit": "68555e952eea58023fa403951b1491496acf0f4b", "tree": "304d10e4d1b11698d73e0b5fb3d9aa69daccca9d", "parents": [ "5abcfe6254acce99bf25a151b19ffe5c9b50494f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 13 14:28:45 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 13 14:28:45 2017 -0800" }, "message": "Added a few integral SIMD extensions for x86/x86_64 (SSE).\n\nRationale:\nART vectorizer needs SIMD for integer operations too.\n\nTest: assembler_x86[_64]_test\nBug: 34083438\nChange-Id: Id6fec558c617d38cb643839eafcd10e59dcd6e0a\n" }, { "commit": "bda1d606f2d31086874b68edd9254e3817d8049c", "tree": "db07417935fe72e99c3da60152e13f0620c7d8d7", "parents": [ "d14d515df39cd963179088b8721768f9645243aa" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 29 17:43:45 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 08 10:13:47 2016 -0700" }, "message": "ART: Detach libart-disassembler from libart\n\nSome more intrusive changes than I would have liked, as long as\nART logging is different from libbase logging.\n\nFix up some includes.\n\nBug: 15436106\nBug: 31338270\nTest: m test-art-host\nChange-Id: I9fbe4b85b2d74e079a4981f3aec9af63b163a461\n" }, { "commit": "372f3a374681ef11f003460e14249adb7bc8313d", "tree": "b6d2bd95975a0ce1096dc2aa761f8e6b30e42b18", "parents": [ "9c07ab332b8ebbcb1586c311bfcb75e19b8a35b4" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 10:49:06 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 16:46:56 2016 -0700" }, "message": "ART: Add thread offset printing hook to disassembler\n\nTo prepare separation of disassembler from libart, add a function\nhook to the disassembler options for thread offset name printing.\n\nBug: 15436106\nChange-Id: I9e9b7e565ae923952c64026f675ac527b560f51b\n" }, { "commit": "ba65cc4a71273904294245cb37ce70e5bce797e3", "tree": "d53a7a816ec4c8e5bdbf80729ac945787b27bf2c", "parents": [ "1a827a05afbffd5bee241f245f9aa3c40b4dbae4", "542451cc546779f5c67840e105c51205a1b0a8fd" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Aug 02 03:47:35 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 02 03:47:35 2016 +0000" }, "message": "Merge \"ART: Convert pointer size to enum\"" }, { "commit": "542451cc546779f5c67840e105c51205a1b0a8fd", "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a", "parents": [ "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 26 09:02:02 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 18:54:48 2016 -0700" }, "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n" }, { "commit": "33dd909468e377aaa8f0ec27fc4b3cb4d8481119", "tree": "fc6c11800d7fa7ace2f44d0bf863f23b54084a18", "parents": [ "e304fc28c4a7d57532498239f9b52d2d5b8974d5" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Aug 01 15:55:36 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Aug 01 16:11:10 2016 -0700" }, "message": "Fixed bug in disassembly of roundss/roundsd\n\nRationale:\nThese instructions should be marked as load, so that, using\nIntel syntax, destination (xmm0) appears at left hand side, as in\n roundss xmm0, xmm1\nand not the other way around. First I suspected a bug in the\nencoding (hence the test) and even the register allocator, but\nsince the code behaved correctly, only disassembly was really wrong.\n\nTest: disassembler_x86_test (but nothing for actual disassembly)\n\nBUG\u003d26327751\n\nChange-Id: I060ef57f4d5a64cdc04b97ae8a799d1c0d22da05\n" }, { "commit": "161c866ca742049f5c916696e1503c697be30e87", "tree": "b3e5c572c840c04e0651cd923b0188427e136f8f", "parents": [ "edec0eb18d9a45d994acec9e8e509a1dc05bd5b3", "4414822df8483d499fbac02563ebe8c7fc000563" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Jul 15 16:40:28 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 15 16:40:28 2016 +0000" }, "message": "Merge \"ART: disassembler_x86 doesn\u0027t recognize NOPs\"" }, { "commit": "3f67e692860d281858485d48a4f1f81b907f1444", "tree": "a14d3bdc1416dc3db74983d34a408a8b48cbce9c", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 15 14:35:12 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 20 20:14:00 2016 -0800" }, "message": "Implemented BitCount as an intrinsic. With unit test.\n\nRationale:\nRecognizing this important operation as an intrinsic has\nvarious advantages:\n(1) having the no-side-effects/no-throw allows for\n much more GVN/LICM/BCE.\n(2) Some architectures, like x86_64, provide direct\n support for this operation.\n\nPerformance improvements on X86_64:\nCheckersEvalBench (32-bit bitboard): 27,210KNS -\u003e 36,798KNS \u003d + 35%\nReversiEvalBench (64-bit bitboard): 52,562KNS -\u003e 89,086KNS \u003d + 69%\n\nChange-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f\n" }, { "commit": "4414822df8483d499fbac02563ebe8c7fc000563", "tree": "bb28eecb8be4603c0ce6e9cd28d93c4983689c46", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Serdjuk, Nikolay Y", "email": "nikolay.y.serdjuk@intel.com", "time": "Mon Sep 14 18:05:33 2015 +0600" }, "committer": { "name": "Nikolay Y Serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Thu Jan 21 03:33:37 2016 +0000" }, "message": "ART: disassembler_x86 doesn\u0027t recognize NOPs\n\nThere are some variations of NOPs which are possible on x86.\n\nChange-Id: I6aab3bc98682e521532cc746f3a371d9c5d98ee8\n" }, { "commit": "bcee092d7b0cbb7181d428115ad98d25ce844061", "tree": "dab00e7f7dc19b002948020a8c2cbde665203c0e", "parents": [ "b505997b2176bd29a108cb6c33d06d4ef29ba001" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "message": "Add X86 bsf and rotate instructions\n\nThese are for use in new intrinsics. Bsf (Bit Scan Forward) is used in\n{Long,Integer}NumberOfTrailingZeros and the rotates are used in\n{Long,Integer}Rotate{Left,Right}.\n\nChange-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "8ae3ffb29489a127f2a6242c33845dac8d50e508", "tree": "cb5cc72e4a699a8ef6b044d530539c13b02604b7", "parents": [ "f67ab129d868b8355a8403a9627f96ac1e41a796" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Aug 12 21:16:41 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 12:58:40 2015 -0400" }, "message": "Add \u0027bsr\u0027 instruction to x86 and x86_64\n\nAdd support for \u0027bsr\u0027 instruction. Add tests.\n\nChange-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b9c4bbee9364a9351376fd1fec9604e7c84778d8", "tree": "2e0fb139b709cb0bb10f4a15067c9b302eeb0dce", "parents": [ "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jul 01 14:26:52 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 11:07:57 2015 -0400" }, "message": "Add rep movsw to x86 and x86_64 instructions.\n\nAdd \u0027REP MOVSW\u0027 as a supported instruction for x86 32 and 64 bit.\n\nAdded tests.\n\nChange-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "124b392d35595f5a8e31e6a9dbefcff5b3ef5760", "tree": "ee2e8c02bde328814d045c98067874ad3a302136", "parents": [ "5d2ed003020feee437683b84e4ea6b8c6a5753e0" ], "author": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Thu Jul 30 13:40:13 2015 -0700" }, "committer": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Thu Jul 30 13:58:52 2015 -0700" }, "message": "Added disassembler support for repe_cmpsw instruction in x86, x86_64\n\nAlso included support for repe_cmpsl instruction. This is a follow up to\ncommit 71311f868e2 which added support for repe_cmpsw in the x86 and\nx86_64 assemblers.\n\nChange-Id: I2beac05a57341539acf96cdf77062facd031a864\n" }, { "commit": "e0705f51fdc71e9670a29f8c3a47168f50724b35", "tree": "4a9a2d808441843bed332b0bdad3aec0a7aa4cee", "parents": [ "64db01714f91bf255a79c0a88813641c240c9857" ], "author": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Mon Apr 27 17:52:57 2015 +0600" }, "committer": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Wed Apr 29 12:17:35 2015 +0600" }, "message": "Fix for incorrect encode and parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F 3A 15\nwas incorrectly encoded in compiler table and incorrectly\nparsed by disassembler.\n\nChange-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164\nSigned-off-by: nikolay serdjuk \u003cnikolay.y.serdjuk@intel.com\u003e\n" }, { "commit": "bd4e6a828fc4aefea7d34a1bbedb81c560c60b6b", "tree": "980f9eaa46f3368927e70c0122c9542b92e3368e", "parents": [ "a68a7cf8f3a6fef22d71a14350176115cb13857f" ], "author": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Fri Mar 27 16:32:27 2015 +0600" }, "committer": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Tue Apr 07 11:42:00 2015 +0600" }, "message": "Fix for incorrect parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F C5 has form:\nPEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and\nxmm is encoded in the R/M part of ModR/M byte. Since the order\nis opposite to the PEXTRB and PEXTRD, we have to set \u0027load\u0027 to\ntrue and \u0027store\u0027 leave as false.\n\nChange-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d\n" }, { "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c", "tree": "01b21964ce0516bda835faa15b260ac290714fe0", "parents": [ "dcff612c3a6e1427749771c4559f198fa480f709" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 22:16:59 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 08:45:38 2015 -0400" }, "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures. Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "031b00dc87cca699f02ce4206a9ecd99d59090dd", "tree": "931769ccc85050469f5e5cb502021d8d35d5ae30", "parents": [ "94fc0e7be35ab1dd42c6336071ea53dfc565faee" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jan 26 19:30:23 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 27 08:44:15 2015 -0800" }, "message": "ART: Fix x86 disassembler\n\nIndex 4 in SIB is valid when given Rex.x, where it denotes r12 and\nnot the invalid rsp.\n\nBug: 19149560\nChange-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850\n" }, { "commit": "6a0b920512b72542b3f1a3d232fba7ded45ea455", "tree": "9fb25c9217e0a0c671faf507e4990b3205bbeade", "parents": [ "f610c0597e001cb1043aa4074afe25ae79a800e3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 16 14:54:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 16 14:54:18 2014 +0000" }, "message": "Fix crash in x86 disassembler.\n\nProbably a typo from last refactoring.\n\nChange-Id: I086a87120ca0f0dfddbe803573b0e0f79cc6d945\n" }, { "commit": "8683038c1f59bea790d8c7691e40eed7f6250e4a", "tree": "63f168876ecb6b8416082cbc141da1d478a66988", "parents": [ "29045735a55726235e5c2c5156809cdcac61d4d7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Dec 12 21:41:29 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 15 10:27:32 2014 -0800" }, "message": "ART: Do not inline elf writer debug symbols\n\nUsing Clang, this pushes the frame size of the caller across our\nlimit. Thus forbid inlining. The function is only called once per\ncompile, impact is insignificant.\n\nBug: 18738594\nChange-Id: I19c3f1168a5104ab508a8dbf9f2a8c035cb97e3c\n" }, { "commit": "e5eb7060dbacfd7c768692a8fcc4a6017d0bd1cc", "tree": "059f7f8b927e4e5fdbef2ed1f78c2a31c36699ab", "parents": [ "d1512fed4e43bba77fb21fd1b6322c22ef7c5881" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Dec 12 18:44:19 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 15 08:15:57 2014 -0800" }, "message": "ART: Break up x86 disassembler main function\n\nThe function leads to large stack frames with Clang. Break out\nsome parts and use four char* variables for opcode.\n\nBug: 18733806\nChange-Id: I8bf6da6c763175d7081c4231fa5d3b6809316220\n" }, { "commit": "677c12fe1939cad5795e7c9f4738941508c4d56f", "tree": "362b74f16c2d73d5dd66268a206ee3b4fcbe22b6", "parents": [ "abe07109e4128ea2adc26c0cb4312539bbe2913d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 07 16:58:38 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 07 16:58:38 2014 -0800" }, "message": "Tidy x86 disassembler\n\nChange-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e\n" }, { "commit": "2c4257be8191c5eefde744e8965fcefc80a0a97d", "tree": "9db3e1f1c60f2df29638ba3ce9d5d5bb8b26ca2c", "parents": [ "98c271d517bc4d25fc6879b4b8e35ea93885d9e2" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 24 14:20:06 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 24 14:23:42 2014 -0700" }, "message": "Tidy logging code not using UNIMPLEMENTED.\n\nChange-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe\n" }, { "commit": "cf7f19135f0e273f7b0136315633c2abfc715343", "tree": "ffa4d9efd9c45f4b6789acc1f534bb9327052b7e", "parents": [ "aea6888b056be21adf762e066c7f33b8939b8a06" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:06:39 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:21:57 2014 -0700" }, "message": "C++11 related clean-up of DISALLOW_..\n\nMove DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations\nwith no definitions this prompts better warning messages so deal with these\nby correcting the code.\nAdd a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object.\nMake X86 assembly operand types ValueObjects to fix compilation errors.\nTidy the use of iostream and ostream.\nAvoid making cutils a dependency via mutex-inl.h for tests that link against\nlibart. Push tracing dependencies into appropriate files and mutex.cc.\nx86 32-bit host symbols size is increased for libarttest, avoid copying this\nin run-test 115 by using symlinks and remove this test\u0027s higher than normal\nulimit.\nFix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it\nreturns NULL when the heap is under construction by Runtime.\n\nChange-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b\n" }, { "commit": "c7dd295a4e0cc1d15c0c96088e55a85389bade74", "tree": "0c08a2236bc9ba5d9a4dc75d4dd0ed2d76f8f1c6", "parents": [ "94e5af8602150efa95bde35cc9be9891ddf30135" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 21 23:31:19 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 12:06:23 2014 -0700" }, "message": "Tidy up logging.\n\nMove gVerboseMethods to CompilerOptions. Now \"--verbose-methods\u003d\" option to\ndex2oat rather than runtime argument \"-verbose-methods:\".\nMove ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc\nexcept for a forward declaration.\nRemove ConstDumpable as Dump methods are all const (and make this so if not\ncurrently true).\nMake LogSeverity an enum and improve compile time assertions and type checking.\nRemove log_severity.h that\u0027s only used in logging.h.\nWith system headers gone from logging.h, go add to .cc files missing system\nheader includes.\nAlso, make operator new in ValueObject private for compile time instantiation\nchecking.\n\nChange-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641\n" }, { "commit": "fc787ecd91127b2c8458afd94e5148e2ae51a1f5", "tree": "ef48c0f511ee9bf4ed85607cc4d530bace7e6cae", "parents": [ "8fa8c904f7c783204a1dc9438429391d256658da" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 21:56:44 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 22:22:46 2014 -0700" }, "message": "Enable -Wimplicit-fallthrough.\n\nFalling through switch cases on a clang build must now annotate the fallthrough\nwith the FALLTHROUGH_INTENDED macro.\nBug: 17731372\n\nChange-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324\n" }, { "commit": "c8ccf68b805c92674545f63e0341ba47e8d9701c", "tree": "fb360323538cb242ebf7c5c0aca27d3a0bce0abb", "parents": [ "fcabfbe577c0fd40910b565beb681bd4b66f6c5d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 29 20:07:43 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 29 20:13:48 2014 -0700" }, "message": "ART: Fix some -Wpedantic errors\n\nRemove extra semicolons.\n\nDollar signs in C++ identifiers are an extension.\n\nNamed variadic macros are an extension.\n\nBinary literals are a C++14 feature.\n\nEnum re-declarations are not allowed.\n\nOverflow.\n\nChange-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a\n" }, { "commit": "2cbaccb67e22c0b313a9785bfc65bcb4b25d0676", "tree": "daeb766e19880b651fd9c4a719c9a07dd7d4bd0e", "parents": [ "bace0378d720a1d2938ec7f6be17e2814671d20a" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Sun Sep 14 20:34:17 2014 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Tue Sep 16 12:50:08 2014 -0700" }, "message": "Avoid printing absolute addresses in oatdump\n\n- Added printing of OatClass offsets.\n- Added printing of OatMethod offsets.\n- Added bounds checks for code size size, code size, mapping table, gc map, vmap table.\n- Added sanity check of 100k for code size.\n- Added partial disassembly of questionable code.\n- Added --no-disassemble to disable disassembly.\n- Added --no-dump:vmap to disable vmap dumping.\n- Reordered OatMethod info to be in file order.\n\nBug: 15567083\n\n(cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f)\n\nChange-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8\n" }, { "commit": "b3a84e2f308b3ed7d17b8e96fc7adfcac36ebe77", "tree": "381fb72a42defc934f01cddab40a63299c0ba592", "parents": [ "2a09504334a3a3b4c47100197df0827cc6740433" ], "author": { "name": "Lupusoru, Razvan A", "email": "razvan.a.lupusoru@intel.com", "time": "Mon Jul 28 14:11:01 2014 -0700" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Sep 03 10:05:40 2014 -0700" }, "message": "ART: Vectorization opcode implementation fixes\n\nThis patch fixes the implementation of the x86 vectorization opcodes.\n\nChange-Id: I0028d54a9fa6edce791b7e3a053002d076798748\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\nSigned-off-by: Philbert Lin \u003cphilbert.lin@intel.com\u003e\n" }, { "commit": "b5bce7cc9f1130ab4932ba8e6917c362bf871f24", "tree": "45d3b064227213da49d047c3c718e23f33b47cad", "parents": [ "3b6711faf7b0b10eaa6c48ba854160bcecd00166" ], "author": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Fri Jul 25 12:32:18 2014 -0700" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Tue Aug 26 11:38:04 2014 -0700" }, "message": "ART: Add non-temporal store support\n\nAdded non-temporal store support as a hint from the ME.\nAdded the implementation of the memory barrier\nextended instruction that supports non-temporal stores\nby explicitly serializing all previous store-to-memory instructions.\n\nChange-Id: I8205a92083f9725253d8ce893671a133a0b6849d\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "f40f890ae3acd7b3275355ec90e2814bba8d4fd6", "tree": "2c25813aefc9fd579a6527ccb8145fba10f5d768", "parents": [ "6324ca4706de44b75e5b8ba55473766809c4f132" ], "author": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Thu Aug 14 14:10:32 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Aug 14 15:21:12 2014 -0700" }, "message": "Implement inlined shift long for 32bit\n\nAdded support for x86 inlined shift long for 32bit\n\nChange-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\n" }, { "commit": "ec95f72490de0a7f86c35de3d00b50bb80d036a1", "tree": "d6576fb0ada8810d721f3e989e03e861e4dac03f", "parents": [ "f90283f61d6ca37abf3a9fb8447d05e79caf0160" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 23 12:10:07 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 30 07:41:43 2014 +0000" }, "message": "ART: Correct disassembling of 64bit immediates on x86_64\n\nThe patch fixes an issue with disassembling \u0027movsxd\u0027 and \u0027movabsq\u0027\ninstructions altered with 64bit immediates: not only a REX.W prefix\nmay be prepended to these instructions.\n\nChange-Id: Ida7c7b368327a6b5cae1ff12ec00ceb0769c0a3d\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "79bb184ec0a661bf1276eef555dd5e20828bc528", "tree": "ccac7bc93ddca873940467ce8be7472a8b8915f5", "parents": [ "62f28f943e2da2873c7a09096c292f01a21c6478" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Jul 01 18:28:43 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 09 10:59:33 2014 +0000" }, "message": "ART: Correct disassembling of regs from opcodes\n\nRegisters, which are part of opcode might have 1-byte size\nor 2-byte size depending on the instruction and 66h prefix.\nThis patch makes the decoding of such instruction correct.\n\nExamples:\n - \u0027664155\u0027 should be decoded as \u0027push r13w\u0027\n (66h + REX.B)\n\n - \u002741B320\u0027 should be decoded as \u0027mov r11l, 0x20\u0027\n (byte-operand + REX.B)\n\nChange-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "2cfe30bd592cb6ae63bb4c28ccaf4b069d6ab565", "tree": "3eb01d4c9f9a36985f70450822c0bb3f4065db02", "parents": [ "7b68fb3b9b421d4b20c1993704986d637f1cab91", "60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jul 09 07:44:21 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 08 22:56:31 2014 +0000" }, "message": "Merge \"X86 Backend support for vectorized float and byte 16x16 operations\"" }, { "commit": "60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43", "tree": "496acee66205218843ed6bddc300ae3653794e75", "parents": [ "cecec712e1e05aab1fe3469077016320b7bf9583" ], "author": { "name": "Udayan Banerji", "email": "udayan.banerji@intel.com", "time": "Tue Jul 08 19:59:43 2014 -0700" }, "committer": { "name": "Udayan Banerji", "email": "udayan.banerji@intel.com", "time": "Tue Jul 08 19:59:43 2014 -0700" }, "message": "X86 Backend support for vectorized float and byte 16x16 operations\n\nAdd support for reserving vector registers for the duration of vector loop.\nAdd support for 16x16 multiplication, shifts, and add reduce.\n\nChanged the vectorization implementation to be able to use the dataflow\nelements for SSA recreation and fixed a few implementation details.\n\nChange-Id: I2f358f05f574fc4ab299d9497517b9906f234b98\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Olivier Come \u003colivier.come@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\n" }, { "commit": "94f3eb0c757d0a6a145e24ef95ef7d35c091bb01", "tree": "9f9c49f151d8065633d916921071adcb1bb1f087", "parents": [ "6e524ddc060f10a493dc63fa5b6dde0deef22219" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Tue Jun 24 13:23:17 2014 +0700" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Wed Jul 09 12:10:52 2014 +0700" }, "message": "x86_64: Clean-up after cmp-long fix\n\nThe patch adresses the coments from review done by Ian Rogers.\nClean-up of assembler.\n\nChange-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "ae2efea4582df773f80be274bdc754f732b07df3", "tree": "dab448db22bc5c01e0010cd6f78fc8017ff8f89c", "parents": [ "0da09a026fb6c612e659dc782312987b4515f472", "fb0fecffb31398adb6f74f58482f2c4aac95b9bf" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Jul 07 18:18:03 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 07 17:50:18 2014 +0000" }, "message": "Merge \"ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation\"" }, { "commit": "e443a8063518fb1c5229afa3081b9fd1f6d33b16", "tree": "a4e64dea6743e787e77369241ec14f3969c43c0d", "parents": [ "ca8ff32bbb1f034b3b1f25de1fe20a9015bc87ec" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Mon Jun 30 15:44:12 2014 +0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 03 16:23:28 2014 -0700" }, "message": "ART: FF-opcodes are target-specific\n\nSome of the FF-opcodes\u0027 (i.e., push, call, jmp) register names\ndepend on the the target (32-bit vs 64-bit). This patch makes\nsuch opcodes target-specific.\n\nChange-Id: I4fa0b7ee5310e14f4022850ac2160c21be5d1c99\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "5192cbb12856b12620dc346758605baaa1469ced", "tree": "46f8727c0009978e1c15f94ea353a9fc92d2fe42", "parents": [ "7a59a24987beb52877b72b4e3f841e406413bb6d" ], "author": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Tue Jul 01 13:48:17 2014 -0400" }, "committer": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Wed Jul 02 06:40:12 2014 -0400" }, "message": "Load 64 bit constant into GPR by single instruction for 64bit mode\n\nThis patch load 64 bit constant into a register by a single movabsq\ninstruction on 64 bit bit instead of previous mov, shift, add\ninstruction sequences.\n\nChange-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\n" }, { "commit": "d48b8a2bc111d30ebafdd2c661e9c0789f5c66a7", "tree": "86c281284fa1a594e9ed6ee9da349cee8c8a84fb", "parents": [ "6f9dbb8d4aa72c9b24ea45358751123b6e4c7488" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Jun 24 16:40:19 2014 +0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 01 16:15:05 2014 -0700" }, "message": "ART: FPU instructions support in disassembler\n\nThis patch extends the disassembler with new FPU instructions:\n - fstsw\n - fucompp\n - fprem\n\nChange-Id: I9458510bc17f2b3b286edec102552f64be05147e\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "fb0fecffb31398adb6f74f58482f2c4aac95b9bf", "tree": "10ce833ce3912adbfbbb7b2514d483a1ae2b14bb", "parents": [ "e7248f2f1835ed194296d4f989c56251d03b834b" ], "author": { "name": "Olivier Come", "email": "olivier.come@intel.com", "time": "Fri Jun 20 11:46:16 2014 +0200" }, "committer": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Wed Jun 25 11:58:01 2014 -0700" }, "message": "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation\n\nThe patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation\n for X86.\n\nChange-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6\nSigned-off-by: Olivier Come \u003colivier.come@intel.com\u003e\n" }, { "commit": "a33720c7370d1c9e0d6569d7126bb06f2083c614", "tree": "925f6b2e03efb37148b3d52f24653656f2f84f4f", "parents": [ "b493c2983016a78de498c3a3aef302b1353dca99" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 18 21:02:29 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sat Jun 21 22:28:48 2014 -0700" }, "message": "X86 Dis: Add missing mov byte; Add size suffixes\n\nYet another instruction not disassembled properly.\nAdd \u0027b\u0027, \u0027w\u0027, \u0027q\u0027 to opcodes to diffferentiate between various versions\nand make it more understandable.\n\nChange-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e", "tree": "bf29fe047b99ff3e387c1eff5c2ea2215bdfda16", "parents": [ "6473c0ab5fe81761c34515c5049d8baf8ee1d35e" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jun 06 15:19:45 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sun Jun 08 22:27:11 2014 -0700" }, "message": "Add Move with Sign Extend Double to disassembler\n\nI noticed another missing instruction.\n\nChange-Id: I71170496b014ac2609116eff2aeb13a13e71e263\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "88649c790cb437c130dcb6e428cddeb1ae62601c", "tree": "4952aa31790fd3016bba3c53808a2a38245aab3b", "parents": [ "32640daf36acda331719766956b25661647e2461" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 04 21:20:00 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jun 05 08:29:31 2014 -0400" }, "message": "Fix X86 disassambler printing of XMM, MM registers\n\nPrinting of uint8_t is done as a char, rather than an integer.\n\nChange-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "122113a8a233f824c014a8fe9d90626218c4dcca", "tree": "ba2b357fe6b2334b83f0da97118ba91fcaee1af6", "parents": [ "57795db7d44bcd6d106481fa192691400b2358c8" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Fri May 30 17:56:23 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jun 04 12:21:28 2014 +0700" }, "message": "ART: x86_64 disassembler improvements\n\nThis patch\n (a) enables full support of 64bit extended regs r8-r15,\n including 8bit r8l-r15l, 16bit r8w-r15w and also\n 32bit r8d-r15d\n (b) fixes an issue with decoding reg from ModRM byte\n (REX.B should be used)\n (c) fixes an issue with decoding regs from SIB byte\n (regs that contain addr are target-specific)\n\nChange-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "67d18be2a5bddbd8ee9ef144b34ccaeba08a1db2", "tree": "77a7d6e731f63ec95005e52261585d1b93324929", "parents": [ "b413cd79c46b7c48ac763cb8152a55a4ed60fe9f" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri May 30 15:05:09 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri May 30 13:04:11 2014 -0700" }, "message": "Support disassembly of 16-bit immediates\n\nChange-Id: I66f5ce93077241204311e52c547599f5287bae04\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "fe94578b63380f464c3abd5c156b7b31d068db6c", "tree": "d5b400472581859591e9f6794fb07b3ba9cb47c0", "parents": [ "8c895b3385ed96a0b040c35222c0338058895d49" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu May 22 09:52:36 2014 -0400" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat May 24 07:33:52 2014 -0700" }, "message": "Implement all vector instructions for X86\n\nAdd X86 code generation for the vector operations. Added support for\nX86 disassembler for the new instructions.\n\nChange-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "e8861b30ac8b2b1ca49386f9c9218f1d6fedc511", "tree": "70ec1c5dc2b917211b9bf0428f2806694f725744", "parents": [ "3f4dcdf6c99f90a2301304d26ce29dc637b4be7f" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Fri Apr 18 17:06:15 2014 +0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Apr 25 10:42:13 2014 -0700" }, "message": "ART: Enables x86_64 disassembly\n\nThis patch\n (a) cuts a REX prefix from the instruction and\n (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes.\n\nChange-Id: I2674678224ca27746b33d4006ed38d497972309f\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "fba52f1b4bf753790c1d98265c4b0fabb54c7536", "tree": "a9feb49c87ae2ec5cde2dd45913840e1f9977ade", "parents": [ "9623c6668962559e818d1e7f05a58dcb96c71fa9" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Apr 15 15:41:47 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Thu Apr 17 13:17:30 2014 +0700" }, "message": "ART: Fixes an issue with REX prefix for instructions with no ModRM byte\n\nThere are instructions (such as push, pop, mov) in the x86 ISA\nthat encode first operands in their opcodes (opcode + reg).\nIn order to enable an extended 64bit registers (R9-R15) a special\nprefix REX.B should be emitted before such instructions.\n\nThis patch fixes the issue when REX.R prefix was emitted before\ninstructions with no MorRM byte. So, the REX-prefix was simply\nignored by CPU for those instructions whose operands are encoded\nin their opcodes.\n\nThis patch makes the jni_compiler_test passed with JNI compiler\nenabled for x86_64 target.\n\nChange-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "dd7624d2b9e599d57762d12031b10b89defc9807", "tree": "c972296737f992a84b1552561f823991d28403f0", "parents": [ "8464a64a50190c06e95015a932eda9511fa6473d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 17:43:00 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Apr 01 08:24:16 2014 -0700" }, "message": "Allow mixing of thread offsets between 32 and 64bit architectures.\n\nBegin a more full implementation x86-64 REX prefixes.\nDoesn\u0027t implement 64bit thread offset support for the JNI compiler.\n\nChange-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147\n" }, { "commit": "99ad7230ccaace93bf323dea9790f35fe991a4a2", "tree": "095705c674703953bf4c50f6a30a105420b770b5", "parents": [ "a9e3d2ccfdbf7f4c7b1508bcb2b774037399b1d4" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Feb 25 17:41:08 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Mar 26 16:20:09 2014 -0700" }, "message": "Relaxed memory barriers for x86\n\nX86 provides stronger memory guarantees and thus the memory barriers can be\noptimized. This patch ensures that all memory barriers for x86 are treated\nas scheduling barriers. And in cases where a barrier is needed (StoreLoad case),\nan mfence is used.\n\nChange-Id: I13d02bf3f152083ba9f358052aedb583b0d48640\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "38e12034f1ef2b32e98b6e49cb36b7cc37a7f1be", "tree": "9a879d4034bce742c8b5ef0680c2da2d8da5139d", "parents": [ "fb5b21d1d598b6b42e5d5ca1dac4a040832558fb" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:06:14 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:16:04 2014 -0700" }, "message": "x86-64 disassembler support.\n\nChange-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0\n" }, { "commit": "4028a6c83a339036864999fdfd2855b012a9f1a7", "tree": "c86f355cb39adc7a14469f0a4e5727623fbda443", "parents": [ "0b2b3dbaa3db62c0af0d2f23f6aa1c539afe7443" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Feb 19 20:06:20 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 20 15:46:42 2014 -0800" }, "message": "Inline x86 String.indexOf\n\nTake advantage of the presence of a constant search char or start index\nto tune the generated code.\n\nChange-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "614c2b4e219631e8c190fd9fd5d4d9cd343434e1", "tree": "8236046426615c78eb6b2f6c2ca29b63d5665d97", "parents": [ "6b3697fec487b355d107b693c965919bf5fff906" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Jan 28 17:05:21 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Feb 11 18:10:33 2014 -0800" }, "message": "Support to generate inline long to FP bytecodes for x86\n\nlong-to-float and long-to-double are now generated inline instead of calling\na helper routine. The conversion is done by using x87.\n\nChange-Id: I196e526afec1be212898baceca8527549c3655b6\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "2c498d1f28e62e81fbdb477ff93ca7454e7493d7", "tree": "94654433a4dae83ab75d432304dcc0358aefeb1c", "parents": [ "1dcff62155e8477eb114c8a86eb1beb0797ffc11" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Jan 29 16:02:57 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Feb 05 22:42:21 2014 -0800" }, "message": "Specializing x86 range argument copying\n\nThe ARM implementation of range argument copying was specialized in some cases.\nFor all other architectures, it would fall back to generating memcpy. This patch\nupdates the x86 implementation so it does not call memcpy and instead generates\nloads and stores, favoring movement of 128-bit chunks.\n\nChange-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "7ea5dafc81b2bba7cabad26130bb75dc8f709803", "tree": "dfd021549d31697d4c142699e38fb8fa00e64c58", "parents": [ "6e65720d99bd3387b72d528a46291f1ed8184ede", "4708dcd68eebf1173aef1097dad8ab13466059aa" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jan 28 00:29:31 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 28 00:29:31 2014 +0000" }, "message": "Merge \"Improve x86 long multiply and shifts\"" }, { "commit": "d3266bcc340d653e178e3ab9d74512c8db122eee", "tree": "1a3cf8b8e828994c57c533157bc1f84e50c24a14", "parents": [ "26a302b2bb07d754b958a4013116946fbbd78c62" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jan 24 12:55:31 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jan 24 14:38:53 2014 -0800" }, "message": "Reduce x86 sequence for GP pair to XMM\n\nAdded support for punpckldq which is useful for interleaving\n32-bit values from two xmm registers.\n\nThis new instruction is now used for transfers from GP pairs\nto XMM in order to reduce path length.\n\nChange-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "4708dcd68eebf1173aef1097dad8ab13466059aa", "tree": "92614e1fe36cccda1d2fd7c662c43482ec8bcc85", "parents": [ "a278ac31a1beeebd093ec64026d27a02fdc28807" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 22 09:05:18 2014 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 24 11:49:06 2014 -0800" }, "message": "Improve x86 long multiply and shifts\n\nGenerate inline code for long shifts by constants and do long\nmultiplication inline. Convert multiplication by a constant to a\nshift when we can. Fix some x86 assembler problems and add the new\ninstructions that were needed (64 bit shifts).\n\nChange-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2bf31e67694da24a19fc1f328285cebb1a4b9964", "tree": "e24b7ec3569ea26e91f1a10179b7d1912f594d7e", "parents": [ "3f5b42f1d31c877abca2571a51dd0a5055a9b94c" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 23 12:13:40 2014 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 24 10:01:41 2014 -0800" }, "message": "Improve x86 long divide\n\nImplement inline division for literal and variable divisors. Use the\ngeneral case for dividing by a literal by using a double length multiply\nby the appropriate constant with fixups. This is the Hacker\u0027s Delight\nalgorithm.\n\nChange-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "bd288c2c1206bc99fafebfb9120a83f13cf9723b", "tree": "a9f154c4338b888de313517e95ae6a7ee22e7f1f", "parents": [ "51f46ad5edd888b58d706569342c1a0f51e6ae15" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Dec 20 17:27:23 2013 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Jan 08 11:28:46 2014 -0800" }, "message": "Add conditional move support to x86 and allow GenMinMax to use it\n\nX86 supports conditional moves which is useful for reducing branchiness.\nThis patch adds support to the x86 backend to generate conditional reg\nto reg operations. Both encoder and decoder support was added for cmov.\n\nThe x86 version of GenMinMax used for generating inlined version Math.min/max\nhas been updated to make use of the conditional move support.\n\nChange-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "d19b55a05b52b7f7da9f894eba63ed03e2a62283", "tree": "06c50a4d0121eae129e8dc920166e2e3953e3468", "parents": [ "f723f0cdc693f81581c0781fa472b1c85a8b42d6" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 12 09:55:34 2013 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 12 13:05:18 2013 -0800" }, "message": "Disassemble more x86 instructions\n\nBy using oatdump on the core.oat, I found a couple more instructions\nthat didn\u0027t disassemble properly. These included another form of imul\nand some FP instructions used by the JNI code.\n\nNow the only unknown opcodes I could find seem to be literal data at\nthe end of the method.\n\nChange-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "f723f0cdc693f81581c0781fa472b1c85a8b42d6", "tree": "5d7b37796a71156d805340d88c0bd7f0078bd153", "parents": [ "8755359a35a4aa915fe3753633015263c7e97b74" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 11 17:50:58 2013 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 11 17:50:58 2013 -0800" }, "message": "Add missing x86 imul opcode to disassembler\n\nWhen playing with ART, I noticed that an integer multiply didn\u0027t\ndisassemble properly. This patch adds the instruction.\n\nChange-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "70b797d998f2a28e39f7d6ffc8a07c9cbc47da14", "tree": "e5607068be133899ff9111e33327e0c2aa525cd1", "parents": [ "057c74a3a2d50d1247d4e6472763ca6f59060762" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 03 15:25:24 2013 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 03 18:32:29 2013 +0000" }, "message": "Unsafe.compareAndSwapLong() intrinsic for x86.\n\nChange-Id: Idbc5371a62dfdd84485a657d4548990519200205\n" }, { "commit": "a8b4caf7526b6b66a8ae0826bd52c39c66e3c714", "tree": "3393e7eeea6ae173caa59edd18b7c2c4c014650a", "parents": [ "17088bbded68e35da8050a40206dfd3cbba9e6d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 24 15:08:57 2013 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 28 18:30:48 2013 +0000" }, "message": "Add byte swap instructions for ARM and x86.\n\nChange-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d\n" }, { "commit": "02ed4c04468ca5f5540c5b704ac3e2f30eb9e8f4", "tree": "fd568452f4ae81868087e9a5f6c04a9051d0ef83", "parents": [ "28c2300d9a85f4e7288fb5d94280332f923b4df3" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Sep 06 13:10:04 2013 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Sep 09 08:33:36 2013 -0700" }, "message": "Move disassembler out of runtime.\n\nBug: 9877500.\nChange-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29\n" }, { "commit": "7934ac288acfb2552bb0b06ec1f61e5820d924a4", "tree": "43f3acd8af7fd34d4ae7b64f6e06bb8429d74bb8", "parents": [ "fb331d7ca004f39608fcfdae49d38df90c702ea9" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 26 10:54:15 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 26 11:55:10 2013 -0700" }, "message": "Fix cpplint whitespace/comments issues\n\nChange-Id: Iae286862c85fb8fd8901eae1204cd6d271d69496\n" }, { "commit": "1895ea386ca78573302483f589ebabd8ce1480e7", "tree": "d8c2d27ac746f29c8248fe17fd6b8e9872556fc4", "parents": [ "3e3d591f781b771de89f3b989830da2b6ac6fac8" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Thu Jul 18 13:28:37 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Thu Jul 18 14:38:27 2013 -0700" }, "message": "Fix cpplint readability/fn_size issues\n\nChange-Id: I1efdb07a948a2af49db1a9d21ccab16dacc03a54\n" }, { "commit": "7940e44f4517de5e2634a7e07d58d0fb26160513", "tree": "ac90242d96229a6942f6e24ab137bc1f8f2e0025", "parents": [ "5cd9e3b122f276f610980cbaf0d2ad6ed4cd9088" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 12 13:46:57 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 12 17:49:01 2013 -0700" }, "message": "Create separate Android.mk for main build targets\n\nThe runtime, compiler, dex2oat, and oatdump now are in seperate trees\nto prevent dependency creep. They can now be individually built\nwithout rebuilding the rest of the art projects. dalvikvm and jdwpspy\nwere already this way. Builds in the art directory should behave as\nbefore, building everything including tests.\n\nChange-Id: Ic6b1151e5ed0f823c3dd301afd2b13eb2d8feb81\n" }, { "commit": "5e588b3c9af58ef54dcdd2cf129472dbe923a5bf", "tree": "eee70f1d6111554feff40ebb4f0cadf8dd4e1a3a", "parents": [ "3afa4c1bae71f3d3cd7004b9b215facbdff22e63" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 21 15:05:09 2013 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 21 15:09:17 2013 -0800" }, "message": "Output Intel group 0 prefixes.\n\nChange-Id: If1908f8fd4d0c5e1f019732e8945af501fe62e8c\n" }, { "commit": "e222ee0b794f941af4fb1b32fb8224e32942ea7b", "tree": "0b9f5fe6398663c9d871881cf7de28eca8bdfc6f", "parents": [ "1aa246dec5abe212f699de1413a0c4a191ca364a" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Dec 13 14:41:43 2012 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Dec 13 15:24:45 2012 -0800" }, "message": "Move stringpiece.h and stringprintf.h to base/.\n\nChange-Id: I7f71b4a12f99c5f81771146c66629ae5a947b229\n" }, { "commit": "07ed66b5ae659c452cbe1ab20c3dbf1d6f546461", "tree": "2350745da33df6fcb9fb0c9059e55ea5d5ea8f67", "parents": [ "76b6167407c2b6f5d40ad895b2793a6b037f54b2" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Dec 12 18:34:25 2012 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Dec 12 18:35:05 2012 -0800" }, "message": "Move logging.h into base/logging.h.\n\nChange-Id: Id68f85f7c3a71b156cb40dec63f94d4fb827f279\n" }, { "commit": "2bcb4a496b7aa00d996df3a070524f7568fb35a1", "tree": "8422ab8d65b7422008094b2eaadec0dad87b2df3", "parents": [ "efc6369224b036a1fb77849f7ae65b3492c832c0" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Nov 08 10:39:18 2012 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 16 14:01:34 2012 -0800" }, "message": "Add \"kind\" argument to Get/SetVReg.\n\nIn order to determine where a register is promoted its necessary to know\nthe kind of use of the register.\nExtend notion of precise-ness to numeric verifier register types.\nDump verifier output in oatdump.\nDump vregs with their location or constant value.\nIntroduce indenting ostream utility.\n\nChange-Id: Ia3d29497877976bc24465484743bca08236e1768\n" }, { "commit": "b23a7729cf7855fa05345d03a4d84111d5ec7172", "tree": "5313e076b19387db3cbcac95225d3f098f19451d", "parents": [ "137e88f798857321f4007631fdf052d2830ec2c4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 09 16:54:26 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 09 16:54:26 2012 -0700" }, "message": "Dump maps inline in disassembled code.\n\nIn pursuit of Bug: 7250540, dump mapping and GC map tables inline such\nas:\n\n0x607333a8: f8dfe11c ldr.w lr, [pc, #284] ; 0x6076416d\n0x607333ac: 1c05 mov r5, r0\n0x607333ae: f8df0144 ldr.w r0, [pc, #324] ; 0x6003ba08\n0x607333b2: 9a0b ldr r2, [sp, #44]\n0x607333b4: f04f0b2f orr r11, pc, ThumbExpand(47)\n0x607333b8: 1c29 mov r1, r5\n0x607333ba: 465b mov r3, r11\n0x607333bc: 2900 cmp r1, #0\n0x607333be: f0008070 beq.w +224 (0x607334a2)\n0x607333c2: 47f0 blx lr\nsuspend point dex PC: 44\nGC map objects: v2 (r7), v3 (r5), v6 ([sp + #84]), v7 (r6)\n...\n\nAs GC map and mapping tables are inline, don\u0027t dump them.\nAlso dump dex instructions before code.\n\nChange-Id: I9f0c04182a4cda6844027eae22e8151f2827dc99\n" }, { "commit": "77ae36b35d47393335bf5399cab9c91ccf08e88f", "tree": "736bfd865e7bfd7caf6c8bc282fa9d04d16232f7", "parents": [ "e37543ed52379bcf08f57ebb3510846294a7102c" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Aug 07 14:18:16 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Aug 07 16:24:08 2012 -0700" }, "message": "Fix and enable inlining of some intrinsics on x86.\n\nInlined min/max int, String isEmpty/length, and abs int/long.\n\nChange-Id: I24aa1b403ee5c8437d63c58dbe1504494ce106ef\n" }, { "commit": "8302576126efae240eb21c7545cda7982437bd26", "tree": "c49a698c034951cc6f3799472dabefb5ccdaaf7f", "parents": [ "937b73eea7a473395f3572e0db1fdc9c6a094db5" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 11:08:56 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 11:08:56 2012 -0700" }, "message": "Added thin-lock fast path for monitor-enter/exit on x86.\n\nChange-Id: Iba187ae1acde6e341ae510d4b47f59e6984fc354\n" }, { "commit": "854029c13351fd3a8f7794eb6c2c73af0fde8ac8", "tree": "3f2968be0023fa1d22303e74a989a1961ea402c9", "parents": [ "22fc28eb95191a1957025b219452c09c7fbb6bd0" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jul 23 17:31:30 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Jul 24 16:33:07 2012 -0700" }, "message": "Fixes to x86 register promotion and load hoisting.\n\nFixed a check to ensure that the mvzxb source register can be byte\naccessed, not the destination reg.\n\nDisabled branch fusion for x86 since code generation for that is\nunimplemented.\n\nChanged regId mask for x86 to allow proper masking of double registers.\n\nAlso added more output to the disassembler.\n\nChange-Id: Idc0a949755ec9ae7b6d5dba38caa5ac01fcc5713\n" }, { "commit": "703f2cd1f4d1eb5ab5c9792ca2de9ffb39378203", "tree": "652ceef30d52a13854c14bb0a6f586e96421f625", "parents": [ "e6e0651c7f0480e18d648200f8958c3463e82a2f" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jul 13 17:25:52 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jul 20 17:21:18 2012 -0700" }, "message": "Numerous fixes to enable PromoteRegs, though it\u0027s still broken.\n\n- Fixed ThrowNullPointerFromCode launchpad to load the array length\n directly into the necessary arg reg without clobbering the array\n pointer, since that value may be live afterwards.\n\n- genArrayPut use a temporary reg for bytes if the source reg is \u003e\u003d 4,\n since x86 can\u0027t express this.\n\n- Fixed the order that core regs are spilled and unspilled.\n\n- Correctly emit instructions when base \u003d\u003d rBP and disp \u003d\u003d 0.\n\n- Added checks to the compiler to ensure that byte opcodes aren\u0027t used\n on registers that can\u0027t be byte accessed.\n\n- Fixed generation of a number of ops which use byte opcodes, including\n floating point comparison, int-to-byte, and and-int/lit16.\n\n- Added rBP, rSI, and rDI to spill registers for the x86 jni compiler.\n\n- Various fixes and additions to the x86 disassembler.\n\nChange-Id: I365fe7dec5cc64d181248fd58e90789f100b45e7\n" }, { "commit": "fdffdf898f12d91765c7dbe7bcb1ccbbcd2b72d1", "tree": "87a7c98d46415dce49aea9a9c73a1351a5d64626", "parents": [ "f1f863695b28f630abb772f50170fefaddc2fb91" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Jul 11 16:08:43 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jul 12 14:32:54 2012 -0700" }, "message": "Fixes to enable TrackLiveTemps optimization on x86.\n\n- Created new kRegRegStore instruction class for Movdrx, where the\n source is first, and the destination is second.\n\n- Reverted neg_float and neg_double implementation to prevent confusion\n of register types when optimizations are performed.\n\n- Swapped order of loads for wide values to prevent base pointer from\n being clobbered when the base pointer equals the low destination reg.\n\n- Implemented opRegCopyWide for general purpose reg source to floating\n point reg destination and vice versa.\n\n- Added more opcode coverage to x86 disassembler.\n\nChange-Id: I4e58eec91742cc51333003fa5a678ba5b23eb575\n" }, { "commit": "e296248a124ed8287b38a9225463696c18d84cd6", "tree": "ffa3305cfb89082b39982d5d617f408c13cf3e66", "parents": [ "837210218c82a4f8e69304e58f8d018dbeb313b8" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jun 28 11:29:57 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jun 28 11:39:22 2012 -0700" }, "message": "Fixes for x86 compiler optimizations.\n\nx86 works with all but a few optimizations turned on, and the broken\nones are still disabled for now. This change includes:\n\n- Flagging of opcodes to incidate register use and def. Also, made\n flagging more complete for loads/stores and set/use ccodes.\n\n- Fixes to load store elimination, though it still doesn\u0027t work yet.\n\n- Prevent double values that are loaded or stored from losing their\n FP_DOUBLE flag. Later optimizations use this sizing.\n\n- Renumbering of DOUBLE registers so they alias with FP regs when\n masked.\n\n- Add support in the disassembler to recognize shifts.\n\nChange-Id: I758cdce418409fdd84206ce295005d5c9ab635f8\n" }, { "commit": "174651dea03956e160a2cff0d842954823c49134", "tree": "cee1f154612afe918a0640ee8aa33644b604c039", "parents": [ "640529bdc78deaeb8d1f3e95da90f9eb5ce9806d" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Apr 19 15:27:22 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Apr 19 16:01:28 2012 -0700" }, "message": "Fixed x86 division and modulus and merged their entry points.\n\nAlso enabled compilation of fill-array-data instructions in x86\n(untested), and improved x86 disassembly.\n\nChange-Id: Ia3d8d0766080d01f1c228f9283085024cadd528b\n" }, { "commit": "16b5c294c37460b51dc1f5296000cc80bbd33419", "tree": "93724e7c43a919cda2298719120895fa705bc529", "parents": [ "54a3e919ef3c8788e39a21696944d00826c25af3" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 20:37:16 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 20:37:16 2012 -0700" }, "message": "Disassemble x86 0xd0 and 0xd1 shifts.\n\nChange-Id: Id061e1971e7a829f57bb83e5299d999d1da8d21e\n" }, { "commit": "14178a99fd397737124e65d5ccb9446f85c5ca93", "tree": "5d6a25f1cc4ca806985ea6450b6dcffaa83c8ae3", "parents": [ "3ea0f42467790809fcfc9fc861605d465808090f" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 17:24:51 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 17:24:51 2012 -0700" }, "message": "Always show the sign of an x86 relative branch, like we do for architectures.\n\nChange-Id: I7f3d4d72179b741064832f9032c9801e201b3b4f\n" }, { "commit": "bf989802bfcd0a0e1d27feb6b67b19cccb7b31e8", "tree": "d2597060cc7ca7e299260aeb6a0256443df0f417", "parents": [ "5450e0ef824b71d9cccc4b322048cabc96f141e6" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 16 16:07:49 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 16 16:07:49 2012 -0700" }, "message": "SSE disassembler support.\n\nChange-Id: I43f5d52ea960e9410cd4db61a14e16eb919419fc\n" }, { "commit": "92301d97693ea52f5f6a9bc62d0c7fc611f87c7b", "tree": "79a55125e94fe1906b354d3d74277354b5aa1706", "parents": [ "b92bcabcbb28f69fe99e1c2f2e5559ab2c47aa60" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 10 15:57:52 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 10 15:57:52 2012 -0700" }, "message": "Decode thread offsets in x86 disassembly.\n\nChange-Id: I924521998c743e61f94cc0d5d71ef53d531d8b56\n" }, { "commit": "0589ca9245849df238812444952c674e01361f2a", "tree": "6c1abb39d336da73c49267b8ba231e2542356ec3", "parents": [ "28fa76d17d741238da86dbdb47f721ae97c9eac8" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 18:26:20 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 18:26:20 2012 -0700" }, "message": "Disassemble x86 opcode 0xc7.\n\nThis was our most popular unknown opcode by far. Example (now):\n\n 0x0007: move-exception v0\n 0x60f51fe8: 648B0578000000 mov eax, fs:[0x78]\n 0x60f51fef: 64C7057800000000000000 mov fs:[0x78], 0\n\nChange-Id: I39d8dde72503a4c418b2d4f5cb7e238ae576d74c\n" }, { "commit": "28fa76d17d741238da86dbdb47f721ae97c9eac8", "tree": "de34f96fbbda6d650db267bd595a20191b9a07cf", "parents": [ "82914b6164fd0109531391975389e4f0ff6832c8" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 17:31:46 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 17:59:35 2012 -0700" }, "message": "A dirty (but useful) hack to decode thread offsets in disassembly.\n\nPlus more readable x86 formatting.\n\nAlso fix a bug decoding LDR (immediate, Thumb) encoding T1.\n\nChange-Id: I95c79d3fb4d912d1ef386b5843abd37d3652a476\n" }, { "commit": "7caad77632ae121c9f64c488e3f8f710e2c4813d", "tree": "6b12ff6e0c27529f5434c5655b3306a1f79bd379", "parents": [ "4855cd516d97c9728fa58312acdf6c4b8b81397a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 30 01:07:54 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 04 09:56:48 2012 -0700" }, "message": "Implement various missing parts of the X86 compiler\n\nChange-Id: I76f08580600befe268328f8cf7102c6146460c5e\n" }, { "commit": "0f3c55331439970e01af67f80ac117c473bc04cf", "tree": "cfa28ad2a58af1ffddb0a2ce90443ad4606743c3", "parents": [ "273cf36d199cf73de3cf61a559ad27c9d23f9825" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Mar 30 14:51:51 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Mar 30 14:51:51 2012 -0700" }, "message": "Kill constants.h and fix some copyright headers.\n\nChange-Id: I51c04d731d6de035328781d8ac134ad6fcf49897\n" }, { "commit": "b25c3f6a86dc634ce44fb2849385b49465caa84d", "tree": "f359c72d821d913f78b977d8dde0fc7023afb511", "parents": [ "fc9e6fabed89d948fa8c0e9d673e430076712c60" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Mar 26 16:35:06 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Mar 26 17:11:59 2012 -0700" }, "message": "Fix cpplint\u0027s whitespace complaints.\n\nChange-Id: I11fd2db2badf7bd98e7866ca2155d8ef1e112408\n" }, { "commit": "706a10ea53a32455c6b3ffc5e5e0e1f6f191ec2a", "tree": "445e94f7b51a5d2b21366afabdf58128116cd065", "parents": [ "9f798f9c7e92a5437c8ad901bb17b9c4e1e9e209" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 23 17:00:55 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 23 23:05:07 2012 -0700" }, "message": "X86 disassembler.\n\nChange-Id: Ie38c55979931f365ec20073a651cfbccc4b86bb4\n" } ] }