)]}' { "log": [ { "commit": "31afbec96e9f9c8e58778694e74aea7ce55e1378", "tree": "1ad1633c75fb6c65fbb25d09fb9dcf92c4a81b8c", "parents": [ "c53528a048e47ef8c51fc5c9667061ebd840adf1" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Mar 14 15:30:19 2017 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Mar 16 05:31:59 2017 -0700" }, "message": "ART: Bit intrinsics for Mterp interpreter\n\nAnother batch of interpreter intrinisics, mostly around bit\nmanipulation. Also some formatting changes and inclusion of a\ncomprehensive list of recognized intrinisics (to assist with\ntelling what\u0027s left to do).\n\nBug: 30933338\n\nBenchmarks:\n 20% Improvement for Reversi\n 10% Improvement for Scimark2\n 3% Improvement for ChessBench\n\nTest: ART_TEST_INTERPRETER\u003dtrue m test-art-host\nTest: art/tools/run-libcore-tests --host (edited for force -Xint)\n\nNote: Added intrinsics have existing test coverage via\n082-inline-execute, 123-inline-execute2, 565-checker-rotate,\n564-checker-bitcount, 566-checker-signum \u0026 567-checker-compare\n\nChange-Id: I29f0386e28eddba37c44f9ced44e7d5f8206bb47\n" }, { "commit": "3c3c4a1da1e8c03e78813d175a9974fb9f1097ea", "tree": "8f93825423a9cfa2ab591de05a1399990f2df12f", "parents": [ "ea36aaf1ebd5342e24ea414d0b797b25eb8d7936" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Tue Feb 21 16:49:59 2017 -0800" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Fri Feb 24 10:22:06 2017 -0800" }, "message": "Improve the region space memory mapping.\n\nAdd a region space mmap fallback when the initial address isn\u0027t\navailable.\n\nClean up around the asan-specific base address.\n\nAdd MemMap::AlignBy to align the region space base address by the\nregion size, which is currently required by ReadBarrierTable.\n\nDisable some read barriers in ZygoteCompactingCollector to avoid a\nDCHECK failure in LockWord::SetMarkBitState when classes are in the\nforward state due to unnecessary read barriers on\nSizeOf/VisitReference.\n\nBug: 12687968\nTest: test-art-host with CC and CMS.\nTest: marlin-userdebug_asan_coverage boot.\nTest: angler boots with CC and CMS.\n\nChange-Id: I70f99779df6acc1b64cab6402f3ef7c73ce5b39b\n" }, { "commit": "58246a13ded36d5256c6fcd3cc60bae5705a73bd", "tree": "c541e811079bd74d506db3a1b906c5f32ed7684e", "parents": [ "a4850b0fa18c8b92dd5c20c166856cfe87aec72f" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 26 12:51:53 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 26 12:55:11 2016 -0700" }, "message": "ART: Revert base/logging conditional hacks\n\nThis partially reverts commit bda1d606f2d31086874b68edd9254e3817d8049c.\nART was switched to libbase logging.\n\nBug: 31338270\nTest: m test-art-host\nChange-Id: I1a2f90d1ddb67d45ebe28d970b3ee7fd2d16a730\n" }, { "commit": "bda1d606f2d31086874b68edd9254e3817d8049c", "tree": "db07417935fe72e99c3da60152e13f0620c7d8d7", "parents": [ "d14d515df39cd963179088b8721768f9645243aa" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 29 17:43:45 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 08 10:13:47 2016 -0700" }, "message": "ART: Detach libart-disassembler from libart\n\nSome more intrusive changes than I would have liked, as long as\nART logging is different from libbase logging.\n\nFix up some includes.\n\nBug: 15436106\nBug: 31338270\nTest: m test-art-host\nChange-Id: I9fbe4b85b2d74e079a4981f3aec9af63b163a461\n" }, { "commit": "f04cf5470fd53d93f7ae5b07205284c19fa59f41", "tree": "2eeb90611ef858fb542ec475c2d8cbb1ee719d8f", "parents": [ "081e7a16c4fcbdb014441a236e12f58eb89ff99a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 31 15:25:25 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 31 16:53:30 2016 +0100" }, "message": "Remove workarounds for [D]CHECK()s in constexpr functions.\n\nWe\u0027re now using C++14, so we can use [D]CHECK()s directly\nin constexpr functions. Remove the C++11 workaround macros\n([D]CHECK_CONSTEXPR) and C++ version checks. Also remove the\n\u0027static\u0027 qualifier from inline functions in affected files.\n\nTest: m test-art-host\nChange-Id: I0f962ad75e4efe9b65325d022cd272b229574222\n" }, { "commit": "09ed09866da6d8c7448ef297c148bfa577a247c2", "tree": "dad6a5dae6ca6131f1eba201eaa371edc6d9929d", "parents": [ "e28ad4b91591c226ed404a2b01104bb99bfeb28f" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Feb 12 21:58:43 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Mar 31 22:12:07 2016 +0100" }, "message": "Pack stack map entries on bit level to save space.\n\nUse only the minimum number of bits required to store stack map data.\nFor example, if native_pc needs 5 bits and dex_pc needs 3 bits, they\nwill share the first byte of the stack map entry.\n\nThe header is changed to store bit offsets of the fields rather than\nbyte sizes. Offsets also make it easier to access later fields without\ncalculating sum of all previous sizes.\n\nAll of the header fields are byte sized or encoded as ULEB128 instead\nof the previous fixed size encoding. This shrinks it by about half.\n\nIt saves 3.6 MB from non-debuggable boot.oat (AOSP).\nIt saves 3.1 MB from debuggable boot.oat (AOSP).\n\nIt saves 2.8 MB (of 99.4 MB) from /system/framework/arm/ (GOOG).\nIt saves 1.0 MB (of 27.8 MB) from /system/framework/oat/arm/ (GOOG).\n\nField loads from stackmaps seem to get around 10% faster.\n(based on the time it takes to load all stackmap entries from boot.oat)\n\nBug: 27640410\nChange-Id: I8bf0996b4eb24300c1b0dfc6e9d99fe85d04a1b7\n" }, { "commit": "88b2b80aed15bb1f931cddd40e44ca525ef10018", "tree": "04b2f9d27863cd469dae8050335f197496f24ff2", "parents": [ "cf6bd55863ded11e0533966657871aca444505a5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Dec 04 14:19:04 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Dec 07 12:38:21 2015 +0000" }, "message": "Allow initializing runtime with parsed options.\n\nNeeded by upcoming refactoring of dex2oat to allow\nearly writing of dex files to the oat file.\n\nChange-Id: Ia13c26132846801522f181f51f64035d625e8416\n" }, { "commit": "0d5a281c671444bfa75d63caf1427a8c0e6e1177", "tree": "fd9bbe0f1c581bcc7c05bbfb2643ffe0b1fb014e", "parents": [ "dd4cbcc924c8ba2a578914a4a366996693bdcd74" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Nov 13 10:07:31 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Sun Nov 15 12:16:41 2015 +0000" }, "message": "x86/x86-64 read barrier support for concurrent GC in Optimizing.\n\nThis first implementation uses slow paths to instrument heap\nreference loads and GC root loads for the concurrent copying\ncollector, respectively calling the artReadBarrierSlow and\nartReadBarrierForRootSlow (new) runtime entry points.\n\nNotes:\n- This implementation does not instrument HInvokeVirtual\n nor HInvokeInterface instructions (for class reference\n loads), as the corresponding read barriers are not stricly\n required with the current concurrent copying collector.\n- Intrinsics which may eventually call (on slow path) are\n disabled when read barriers are enabled, as the current\n slow path infrastructure does not support this case.\n- When read barriers are enabled, the code generated for a\n HArraySet instruction always go into the array set slow\n path for object arrays (delegating the operation to the\n runtime), as we are lacking a mechanism to keep a\n temporary register live accross a runtime call (needed for\n the instrumentation of type checking code, which requires\n two successive read barriers).\n\nBug: 12687968\nChange-Id: I14cd6107233c326389120336f93955b28ffbb329\n" }, { "commit": "dbce0d738e9d7956d2bd73e932a0fdd28f2229b4", "tree": "336a92e522c4f20386f65f2a34534f982cf28089", "parents": [ "002117f95896ffa5db74bee808ae61e876b6e8b0" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Sep 17 13:34:00 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Oct 05 18:12:30 2015 -0700" }, "message": "MIPS64r6 Assembler Tests\n\nAssembler tests for:\n\n- SQRT.fmt - ABS.fmt - ROUND.L.fmt - ROUND.W.fmt\n- CEIL.L.fmt - CEIL.W.fmt - FLOOR.L.fmt - FLOOR.W.fmt\n- SEL.fmt - RINT.fmt - CLASS.fmt - MIN.fmt\n- MAX.fmt - cvt.d.l - BITSWAP - DBITSWAP\n- DSBH - DSHD - WSBH - ROTR\n- SELEQZ - SELNEZ - CLZ - CLO\n- DCLZ - DCLO - SC - SCD\n- LL - LLD\n\nThese are the assembler instructions which were added to support\nintrinsic functions on MIPS64. Tests for additional assembler\ninstructions will follow.\n\nSupport added to the testing infrastructure for:\n\n- Assembler instructions which use three registers; previously\n instructions were limited to one, or two, registers.\n- Immediate values which have their sizes specified by the number of\n bits required to store them rather than the number of bytes, in both\n signed and unsigned versions.\n\nChange-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b\n" }, { "commit": "151ab8d096be02b04391fd32460a31ee60ae2b0a", "tree": "566224aba5d6eb10a2ef5dee01314a21481fc6b3", "parents": [ "5e289b2bca7a0bc67fcf00a1017d70db8b363113" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 14 23:01:49 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 17 13:45:36 2015 -0700" }, "message": "Revert \"Revert \"ART: DCHECK zero case for CLZ/CTZ\"\"\n\nThis reverts commit 4318d91ea4be673d4deba39d33ac4718d77986a7.\n\nFix up the lit\u003d-1 case in the arm32 Quick backend; add test case.\n\nChange-Id: I8d0861133db950090ee959f532ede1448683dfa9\n" }, { "commit": "cf36d493124d8048efa0bd6f67d817ce3cd6b725", "tree": "fac1336f54ea477ce1afe2e99a04b68db38c7ac8", "parents": [ "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 12 19:27:26 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 17 10:04:42 2015 +0100" }, "message": "ART: Compress LengthPrefixedArray on 32-bit targets.\n\nPreviously, the LengthPrefixedArray\u003cArtMethod\u003e on 32-bit\ntargets contained a 64-bit length field followed by the\nArtMethod elements with size only a multiple of 4, not 8.\nConsequently, an odd-length array broke the alignment for\nthe following array which would have the 64-bit length\nplaced at an unaligned address.\n\nTo fix that, we make the length field 32-bit and explicitly\npass the alignment information to the LengthPrefixedArray.\nThis also makes the 32-bit boot image a bit smaller.\nOn Nexus 5, AOSP, ToT, the field section is 11528B smaller\nand the method section is 21036B smaller. 64-bit targets\nshould see the same savings for the field section but no\ndifference for the methods section.\n\nChange-Id: I3e03e7b94129025c8a1c117c27645a34dec516d2\n" }, { "commit": "7bf2b4f1d08050f80782217febac55c8cfc5e4ef", "tree": "61b26b116454c5a114ac4b2f55c71153be7a9d43", "parents": [ "569e81e500725f52116b7d0342ec80a6d1e0089b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 08 10:11:59 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 08 14:22:19 2015 +0100" }, "message": "Revert \"Revert \"Remove interpreter entrypoint in ArtMethod.\"\"\n\nThe start of the interned strings in the image was not aligned\nproperly, now that ArtMethods just need to be word aligned.\n\nThis reverts commit 7070ccd8b6439477eafeea7ed3736645d78e003f.\n\nbug:22242193\n\nChange-Id: I580c23310c33c239fe0e5d15c72f23a936f58ed1\n" }, { "commit": "7070ccd8b6439477eafeea7ed3736645d78e003f", "tree": "e32dca6b4342ce7b42952e0d9150a85fba361562", "parents": [ "fa2c054b28d4b540c1b3651401a7a091282a015f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 08 09:41:54 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 08 09:41:54 2015 +0000" }, "message": "Revert \"Remove interpreter entrypoint in ArtMethod.\"\n\nBuild failures on bots. Investigating.\n\nThis reverts commit fa2c054b28d4b540c1b3651401a7a091282a015f.\n\nChange-Id: Id65b2009aa66cb291fb8c39758a58e0b0d22616c\n" }, { "commit": "fa2c054b28d4b540c1b3651401a7a091282a015f", "tree": "d39c2eca12dce2e0366a092b05715b3eab1319b4", "parents": [ "c87c8939ea1bcfbddb954478d527cf1138f4f343" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 01 14:32:54 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 08 09:31:25 2015 +0100" }, "message": "Remove interpreter entrypoint in ArtMethod.\n\nSaves 4/8 bytes for each ArtMethod.\n\nChange-Id: I110ecdddf8516b0759a31fa157609643e6d60b15\n" }, { "commit": "80afd02024d20e60b197d3adfbb43cc303cf29e0", "tree": "ef054c7b4f2a739f7cf063e0bc4c501c2c7e41b5", "parents": [ "559b178e34c5d92e7932f92e5d8a981ac334606f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 19 18:08:00 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 26 15:59:02 2015 +0100" }, "message": "ART: Clean up arm64 kNumberOfXRegisters usage.\n\nAvoid undefined behavior for arm64 stemming from 1u \u003c\u003c 32 in\nloops with upper bound kNumberOfXRegisters.\n\nCreate iterators for enumerating bits in an integer either\nfrom high to low or from low to high and use them for\n\u003carch\u003eContext::FillCalleeSaves() on all architectures.\n\nRefactor runtime/utils.{h,cc} by moving all bit-fiddling\nfunctions to runtime/base/bit_utils.{h,cc} (together with\nthe new bit iterators) and all time-related functions to\nruntime/base/time_utils.{h,cc}. Improve test coverage and\nfix some corner cases for the bit-fiddling functions.\n\nBug: 13925192\nChange-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7\n" } ] }