)]}' { "log": [ { "commit": "16d9f949698faed28435af7aa9c9ebacbfd5d1a8", "tree": "870fbd499c10f70cecc5f62246b26e1332b600da", "parents": [ "7c95b4e22897a6f14ef79ec6e547e2eed686814a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 25 17:27:56 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 25 17:27:56 2016 +0100" }, "message": "Re-enable the ArraySet fast path with Baker read barriers.\n\nBenchmarks (ARM64) score variations on Nexus 5X with CPU\ncores clamped at 960000 Hz (aosp_bullhead-userdebug build):\n- Ritzperf - average (lower is better): -0.95% (virtually unchanged)\n- CaffeineMark - average (higher is better): +2.50% (slightly better)\n- DeltaBlue (lower is better): -0.55% (virtually unchanged)\n- Richards - average (lower is better): +0.67% (virtually unchanged)\n- SciMark2 - average (higher is better): -0.10% (virtually unchanged)\n\nDetails about Ritzperf benchmarks with meaningful variations\n(lower is better):\n- GenericCalcActions.MemAllocTest: -5.05% (better)\n\nDetails about CaffeineMark benchmarks with meaningful variations\n(higher is better):\n- Method: +16.88% (better)\n\nDetails about Richards benchmarks with meaningful variations\n(lower is better):\n- deutsch_acc_interface: +9.86% (worse)\n\nBoot image code size variation on Nexus 5X\n(aosp_bullhead-userdebug build):\n- total ARM64 framework Oat files size change:\n 105933472 bytes -\u003e 106027680 bytes (+0.09%)\n- total ARM framework Oat files size change:\n 89157936 bytes -\u003e 89239856 bytes (+0.09%)\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29516974\nBug: 29506760\nBug: 12687968\nChange-Id: Ib9e9709712295e17804b8888ac10e3d518ff2e70\n" }, { "commit": "953437bd51059801d92079295f728d0260efca31", "tree": "b52816b5092a143361ea3878ef0e06d311c4a56f", "parents": [ "c67d22ac6db73aaa9540294c86344bf8021495b3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 08:30:46 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 13:20:32 2016 +0100" }, "message": "Revert \"Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\"\n\nFixed the fault handler recognizing the TEST instruction and\nfault address within the lock word. Added tests to 439-npe.\n\nBug: 29966877\nBug: 12687968\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\n\nThis reverts commit ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15.\n\nChange-Id: I8990def5f719c9205bf6e5fdba32027fa82bec50\n" }, { "commit": "ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15", "tree": "8e271269eb0f3e40388311478fe441bfeb47ab47", "parents": [ "ccf06d8f19a37432de4a3b768747090adfbd18ec" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "message": "Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\n\nFault handler does not recognize the instruction\n F6 /0 ib TEST r/m8, imm8\nso we get crashes instead of NPEs.\n\nBug: 29966877\nBug: 12687968\n\nThis reverts commit ccf06d8f19a37432de4a3b768747090adfbd18ec.\n\nChange-Id: Ib7db3b59f44c0d3ed5e24a20b6c6ee596a89d709\n" }, { "commit": "ccf06d8f19a37432de4a3b768747090adfbd18ec", "tree": "fcb3ba46184db6882e695cecf1cfe495417593ae", "parents": [ "cf834d00de838272cf28f2382ffc26fe716aae5c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 12 13:37:55 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 11:41:44 2016 +0100" }, "message": "x86/x86-64: Avoid temporary for read barrier field load.\n\nAdd TEST instructions for memory and immediate. Use the byte\nversion to avoid a temporary in read barrier field load.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\nBug: 29966877\nBug: 12687968\nChange-Id: Ia415d3c2e1ae1ff6dff11d72bbb7d96d5deed6ee\n" }, { "commit": "9c07ab332b8ebbcb1586c311bfcb75e19b8a35b4", "tree": "26a300b803f77e64c17e3d239a1880a4c5960666", "parents": [ "6670bd2098264d4c4e19750ab4741121da7ee54b", "bf44e0e5281de91f2e38a9378b94ef8c50ad9b23" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Aug 19 17:33:03 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 19 17:33:03 2016 +0000" }, "message": "Merge \"ART: Implement a fixed size string dex cache\"" }, { "commit": "0b671c0408e98824e1f92b1ee951b210c090fe7a", "tree": "0bc58c031cd899aa856677fe8c9ffa376228806f", "parents": [ "36bf3a2d281892e7906d3eaf9d7455b0656c9a25" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 12:02:34 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 16:00:09 2016 +0100" }, "message": "Add support for Baker read barriers in SystemArrayCopy intrinsics.\n\nBenchmarks (ARM64) score variations on Nexus 5X with CPU\ncores clamped at 960000 Hz (aosp_bullhead-userdebug build):\n- Ritzperf - average (lower is better): -3.03% (slightly better)\n- CaffeineMark - average (higher is better): +1.26% (slightly better)\n- DeltaBlue (lower is better): -10.50% (better)\n- Richards - average (lower is better): -3.36% (slightly better)\n- SciMark2 - average (higher is better): +0.26% (virtually unchanged)\n\nDetails about Ritzperf benchmarks with meaningful variations\n(lower is better):\n- FormulaEvaluationActions.EvaluateAndApplyChanges: -13.26% (better)\n- FormulaEvaluationActions.EvaluateCascadingSums: -10.94% (better)\n- FormulaEvaluationActions.EvaluateComplexFormulas: -15.50% (better)\n- FormulaEvaluationActions.EvaluateFibonacci: -10.41% (better)\n- FormulaEvaluationActions.EvaluateLargeSums: +6.02% (worse)\n\nBoot image code size variation on Nexus 5X\n(aosp_bullhead-userdebug build):\n- total ARM64 framework Oat files size change:\n 107047632 bytes -\u003e 107154128 bytes (+0.10%)\n- total ARM framework Oat files size change:\n 90932028 bytes -\u003e 91009852 bytes (+0.09%)\n\nTest: ART host and target (ARM, ARM64) tests + Nexus 5X boot.\nBug: 29516905\nBug: 29506760\nBug: 12687968\nChange-Id: I85431368d09965687a0301ae2eb3c991f276ce5d\n" }, { "commit": "bf44e0e5281de91f2e38a9378b94ef8c50ad9b23", "tree": "bb6e65a3434806dc58f286ee75ad3b78ba9d6c36", "parents": [ "d99565069c64fefc069005286de04599dc2619b8" ], "author": { "name": "Christina Wadsworth", "email": "cwadsworth@google.com", "time": "Thu Aug 18 10:37:42 2016 -0700" }, "committer": { "name": "Christina Wadsworth", "email": "cwadsworth@google.com", "time": "Thu Aug 18 16:18:36 2016 -0700" }, "message": "ART: Implement a fixed size string dex cache\n\nPreviously, the string dex cache was dex_file-\u003eNumStringIds() size, and\n@ruhler found that only ~1% of that cache was ever getting filled. Since\nmany of these string dex caches were previously 100,000+ indices in\nlength, we\u0027re wasting a few hundred KB per app by storing null pointers.\nThe intent of this project was to reduce the space the string dex cache\nis using, while not regressing on time that much. This is the first of a\nfew CLs, which implements the new fixed size array and disables the\ncompiled code so it always goes slow path. In four other CLs, I\nimplemented a \"medium path\" that regresses from the previous \"fast path\"\nonly a bit in assembly in the entrypoints. @vmarko will introduce new\ncompiled code in the future so that we ultimately won\u0027t be regressing on\ntime at all. Overall, space savings have been confirmed as on the order\nof 100 KB per application.\n\nA 4-5% slow down in art-opt on Golem, and no noticeable slow down in the\ninterpreter. The opt slow down should be diminished once the new\ncompiled code is introduced.\n\nTest: m test-art-host\n\nBug: 20323084\n\nChange-Id: Ic654a1fb9c1ae127dde59290bf36a23edb55ca8e\n" }, { "commit": "554b6fb8759d186eba1046c220c9cff9a8610525", "tree": "0b28f10d2235c82ba13f75829a018457d2ce9a66", "parents": [ "fe74ba9ea6c2c47a02d2ba7436b3a603b459468c", "4a3aa578eff94eb10450fae1772deb7cb8ddc6a6" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Aug 15 14:35:48 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 15 14:35:48 2016 +0000" }, "message": "Merge \"Revert \"Enable IntermediateAddress for primitive arrays with read barriers.\"\"" }, { "commit": "4a3aa578eff94eb10450fae1772deb7cb8ddc6a6", "tree": "abb3aa17279c6a9edc9dd1c0691738a7f7c69a10", "parents": [ "12ecf0800d465acdaa3deccd383ff8ed3428a183" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 15 13:17:06 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 15 13:17:06 2016 +0000" }, "message": "Revert \"Enable IntermediateAddress for primitive arrays with read barriers.\"\n\nThis CL breaks the angler-userdebug build with\n`ART_USE_READ_BARRIER\u003dtrue`.\n\nTest: Build angler-userdebug with `ART_USE_READ_BARRIER\u003dtrue`.\nBug: 30762467\nBug: 26601270\nBug: 12687968\n\nThis reverts commit 12ecf0800d465acdaa3deccd383ff8ed3428a183.\n\nChange-Id: Ia2069ac9436d2336311dd8d0f183c02e587586ae\n" }, { "commit": "7cbd27fe778f2c348136540d52b5473e28f5769d", "tree": "80c0fa4ff2a223c061245c6799d992cd4d863fa0", "parents": [ "3d1d18d74dfac5039b6093ddf04f74eee4f157a3" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 11 23:53:33 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 12 13:19:51 2016 +0100" }, "message": "Adjust spacing before NOLINT comments in ART.\n\nNote that neither clang-tidy nor cpplint.py complain about\nthese style \"issues\", precisely because of the NOLINT\ncomments.\n\nTest: WITH_TIDY\u003d1 WITH_TIDY_CHECKS\u003d\u0027-*,misc-macro-parentheses\u0027 mmma art\nChange-Id: Id692fd394ffbd4fe208cbbe4407b4d5e208462bb\n" }, { "commit": "51616fb233df2760fd6002a02dce692f24b93fb6", "tree": "61766bfa4bb53bf8f57a6c2645e81d375aa902bf", "parents": [ "c10ad423024432df36f6360eafca8332d07b946a", "12ecf0800d465acdaa3deccd383ff8ed3428a183" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 08 10:16:43 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 08 10:16:43 2016 +0000" }, "message": "Merge \"Enable IntermediateAddress for primitive arrays with read barriers.\"" }, { "commit": "12ecf0800d465acdaa3deccd383ff8ed3428a183", "tree": "229f7438b82c945f4b3221f6c1033eaf96a9a1c6", "parents": [ "d16ae7fe70d74091778e5952b7920df14866287f" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 08 10:18:37 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 08 10:18:37 2016 +0100" }, "message": "Enable IntermediateAddress for primitive arrays with read barriers.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 26601270\nBug: 12687968\nChange-Id: I6736ba7b1809bece1bf3cd82c69e4f42a0d3c4a7\n" }, { "commit": "965c0b9f98a4acbec7be148291196e30784bba2d", "tree": "c9b53c36226535f2941d47a1ea222da114266680", "parents": [ "2e98023165349ab91855555f63fed8dad3c471fe", "952dbb19cd094b8bfb01dbb33e0878db429e499a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 04 14:44:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 04 14:44:10 2016 +0000" }, "message": "Merge \"Change suspend entrypoint to save all registers.\"" }, { "commit": "952dbb19cd094b8bfb01dbb33e0878db429e499a", "tree": "82932c2b00245042e2c129f3d4133f6431657da3", "parents": [ "df638c66d1f385d4e217b2ab22c5e48a7eefdef4" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 28 12:01:51 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 04 14:51:52 2016 +0100" }, "message": "Change suspend entrypoint to save all registers.\n\nWe avoid the need to save/restore registers in slow paths\nand get significant code size savings. On Nexus 9, AOSP:\n - 32-bit boot.oat: -1.4MiB (-1.9%)\n - 64-bit boot.oat: -2.0MiB (-2.3%)\n - other 32-bit oat files in dalvik-cache: -200KiB (-1.7%)\n - other 64-bit oat files in dalvik-cache: -2.3MiB (-2.1%)\n\nTest: Run ART test suite on host and Nexus 9 with gc stress.\nBug: 30212852\nChange-Id: I7015afc1e7d30341618c9200a3dc9ae277afd134\n" }, { "commit": "36a270ae4f288e49493432b7128f899ad579849e", "tree": "99f134bbfe111b1c42b1b0c19d8b65175a3e6fc8", "parents": [ "89bd8358c0a69e8cd6456d81d88ef366e261f732" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jul 28 18:08:51 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Aug 03 15:46:18 2016 -0700" }, "message": "Change one read barrier bit to mark bit\n\nOptimization to help slow path performance. When the GC marks an\nobject through the read barrier slow path. The GC sets the mark bit\nin the lock word of that reference. This bit is checked from the\nassembly entrypoint the common case is that it is set. If the bit is\nset, the read barrier knows the object is already marked and there is\nno work to do.\n\nTo prevent dirty pages in zygote and image, the bit is set by the\nimage writer and zygote space creation.\n\nEAAC score (lower is better):\nN9: 777 -\u003e 700 (average 31 of runs)\nN6P (960000 mhz): 1737.48 -\u003e 1442.31 (average of 25 runs)\n\nBug: 30162165\nBug: 12687968\n\nTest: N9, N6P booting, test-art-host, test-art-target all with CC\n\nChange-Id: Iae0cacfae221e33151d3c0ab65338d1c822ab63d\n" }, { "commit": "89bd8358c0a69e8cd6456d81d88ef366e261f732", "tree": "e024d9507acadbc0ea1c142a83e9a3221baf7718", "parents": [ "01b7982a45fe53218d432ed1e8172d9d032d93ab", "b2b753c85433d81bcf44ad35b7b053d8fc753148" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 03 17:56:02 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Aug 03 17:56:03 2016 +0000" }, "message": "Merge \"ARM64: Use the zero register in the parallel-move resolver.\"" }, { "commit": "a7426c6a9ceeec193f6d886df7d0dcb3018f919d", "tree": "51e3513626ec0faf4ed648032e498bbd5e9c40d9", "parents": [ "d16ae7fe70d74091778e5952b7920df14866287f" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 03 15:02:10 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 03 15:05:43 2016 +0100" }, "message": "Fix an assertion in the non-Baker read barrier ARM64 slow path.\n\nTest: m ART_USE_READ_BARRIER\u003dtrue ART_READ_BARRIER_TYPE\u003dTABLELOOKUP test-art-target (ARM64).\nBug: 30563701\nChange-Id: Ib7969bd78e9c14cc2be9d5527d80385486b4f409\n" }, { "commit": "b2b753c85433d81bcf44ad35b7b053d8fc753148", "tree": "a10d2fd40109c5ca4a31e78a1de9cc3b83d2ca18", "parents": [ "d16ae7fe70d74091778e5952b7920df14866287f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 02 13:45:28 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Aug 03 09:24:31 2016 +0100" }, "message": "ARM64: Use the zero register in the parallel-move resolver.\n\nWhen moving zero to a stack slot, this will change\n\n mov temp, #0\n str temp, [...]\n\ninto\n\n str zr, [...]\n\nChange-Id: I2211b00d70f3fa0a02e781c90198757290b2bf89\n" }, { "commit": "542451cc546779f5c67840e105c51205a1b0a8fd", "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a", "parents": [ "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 26 09:02:02 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 18:54:48 2016 -0700" }, "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n" }, { "commit": "dec8f63fdf50815f24efe1c03af64208da15f339", "tree": "36c8dec8c2c93312d17c6d9d1452d4b133212dbd", "parents": [ "41c7e2e6ac0a59da2f3e066e20630b295fbe4661" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 22 17:10:06 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 22 18:54:35 2016 +0100" }, "message": "Do not emit stack maps for runtime calls to ReadBarrierMarkRegX.\n\n* Boot image code size variation on Nexus 5X\n (aosp_bullhead-userdebug build):\n - total ARM64 framework Oat files size change:\n 115584120 bytes -\u003e 109124728 bytes (-5.59%)\n - total ARM framework Oat files size change:\n 97387728 bytes -\u003e 92517584 (-5.00%)\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I979d9fb2b4e09f4c0c7bf33af2cd91750a67f989\n" }, { "commit": "057361ca33625ed14b33ffd8e641e27916fb2fea", "tree": "cf13a0b5c0e5504fdcf320ab9a9936d0d489bdf5", "parents": [ "65ad9b3516c4f4bc4e7abf5c6e065a675cf024d8", "4359e61927866c254bc2d701e3ea4c48de10b79c" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 12:11:15 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 12:11:15 2016 +0000" }, "message": "Merge \"Move caller-saves saving/restoring to ReadBarrierMarkRegX.\"" }, { "commit": "4359e61927866c254bc2d701e3ea4c48de10b79c", "tree": "05d274ecd6b5ff6eb890f64cd3bb670c7170bf15", "parents": [ "2be946bbf995496fe56364d9b7c4957fcb6aeec5" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 20 11:32:19 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 11:21:20 2016 +0100" }, "message": "Move caller-saves saving/restoring to ReadBarrierMarkRegX.\n\nInstead of saving/restoring live caller-save registers\nbefore/after the call to read barrier mark entry points\nReadBarrierMarkRegX, have these entry points save/restore\nall the caller-save registers themselves (except register\nrX, which contains the return value).\n\nAlso refactor the assembly code of these entry points\nusing macros.\n\n* Boot image code size variation on Nexus 5X\n (aosp_bullhead-userdebug build):\n - total ARM64 framework Oat files size change:\n 119196792 bytes -\u003e 115575920 bytes (-3.04%)\n - total ARM framework Oat files size change:\n 100435212 bytes -\u003e 97621188 bytes (-2.80%)\n\n* Benchmarks (ARM64) score variations on Nexus 5X\n (aosp_bullhead-userdebug build):\n - RitzPerf (lower is better)\n - average score difference: -2.71%\n - CaffeineMark (higher is better)\n - no real difference for most tests\n (absolute variation lower than 1%)\n - better score on the \"Method\" benchmark:\n score variation 41253 -\u003e 44891 (+8.82%)\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I881bf73139a3f1c2bee9ffc6fc8c00f9a392afa6\n" }, { "commit": "a92938a17b75eed3213030faaff9cfb321d47f37", "tree": "c6db649f7c1f6b6a86eb568212a721aac4ee6d96", "parents": [ "89b03e0cfb03e3194e39f07fa8c1bd46e3b28a34", "328429ff48d06e2cad4ebdd3568ab06de916a10a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 21 09:17:15 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 09:17:16 2016 +0000" }, "message": "Merge \"ARM: Port instr simplification of array accesses.\"" }, { "commit": "328429ff48d06e2cad4ebdd3568ab06de916a10a", "tree": "6290ac8afc3e93488382727f6765f548a2cfff04", "parents": [ "79e73245140f4115039a7284b3797d701f368fe6" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 06 16:23:04 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 21 09:16:43 2016 +0000" }, "message": "ARM: Port instr simplification of array accesses.\n\nAfter changing the addressing mode for array accesses (in\nhttps://android-review.googlesource.com/248406) the \u0027add\u0027\ninstruction that calculates the base address for the array can be\nshared across accesses to the same array.\n\nBefore https://android-review.googlesource.com/248406:\n add IP, r[Array], r[Index0], LSL #2\n ldr r0, [IP, #12]\n add IP, r[Array], r[Index1], LSL #2\n ldr r0, [IP, #12]\n\nBefore this CL:\n add IP. r[Array], #12\n ldr r0, [IP, r[Index0], LSL #2]\n add IP. r[Array], #12\n ldr r0, [IP, r[Index1], LSL #2]\n\nAfter this CL:\n add IP. r[Array], #12\n ldr r0, [IP, r[Index0], LSL #2]\n ldr r0, [IP, r[Index1], LSL #2]\n\nLink to the original optimization:\n https://android-review.googlesource.com/#/c/127310/\n\nTest: Run ART test suite on Nexus 6.\nChange-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f\n" }, { "commit": "e4b1c86d13c3f60362708f4a128b62db156f5fde", "tree": "4920c33f3510a21dba212650659174a7bb44c855", "parents": [ "ce1ba111bfa122247ac186e7d2c6cf5943ba28cd", "465ecc86ff65ca546629630c9469deb6d2d8137e" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 21 00:04:52 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 00:04:52 2016 +0000" }, "message": "Merge \"Revert \"Revert \"Refactor GetIMTIndex\"\"\"" }, { "commit": "6740997e6934bbca27d5830a32352d82aabbd38b", "tree": "684ab2e46ddeaaf251fb6919bf64295810e46afa", "parents": [ "dc4f4d42aa1712a7ac2e4c24c0aebe58b71ae2c0" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 19 22:34:53 2016 -0700" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 20 11:44:25 2016 +0100" }, "message": "ART: Change return types of field access entrypoints\n\nEnsure that return types guarantee full-width data as the compiled\ncode and mterp expect by using size_t and ssize_t.\n\nThis fixes Clang no longer sign-/zero-extending small return types.\n\nBug: 30232671\nTest: m ART_TEST_RUN_TEST_NDEBUG\u003dtrue ART_TEST_INTERPRETER\u003dtrue test-art-host-run-test\nChange-Id: Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1\n" }, { "commit": "465ecc86ff65ca546629630c9469deb6d2d8137e", "tree": "3a0ed3f2d3ab9fd2cffec44a659036efab35fb4e", "parents": [ "bae13af2fc2fa89985d0466cedf155cb96767910" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jul 19 21:32:52 2016 +0000" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jul 19 21:48:06 2016 +0000" }, "message": "Revert \"Revert \"Refactor GetIMTIndex\"\"\n\nOriginally reverted in order to revert\nhttps://android-review.googlesource.com/#/c/244190/\nbut can now be merged again.\n\nThis reverts commit d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c.\n\nTest: m test-art-host\n\nChange-Id: Id9205f2b77a378fc0f06088e78c66e81a49f712d\n" }, { "commit": "5668e58daf0f54d6cc8a6919033acc3506fc86ee", "tree": "de19460ff3c2f940ce5b0f7036a4bf756b59ed4e", "parents": [ "24670a7aac24c7a9b661220ab76b36c75f1494c5", "97c72b76cf776228196c6abd33973ef751de61ad" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 18 14:28:05 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 18 14:28:06 2016 +0000" }, "message": "Merge \"Fixes to build against new VIXL interface.\"" }, { "commit": "97c72b76cf776228196c6abd33973ef751de61ad", "tree": "7a78a2b19b0847281f8cf69af735b30b15732fa8", "parents": [ "1fd347303275a424d114c9833f954e8e27812554" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jun 24 16:19:36 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jul 15 09:48:07 2016 +0100" }, "message": "Fixes to build against new VIXL interface.\n\n- Fix namespace usage and use of deprecated functions.\n- Link all dependants to new libvixl-arm64 target for now.\n\nChange-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509\n" }, { "commit": "2c30a373428b8d19bf97866d5d323c4ca2fbca72", "tree": "8927430b0ae7185b0583615e8dbd7481ac13c6c7", "parents": [ "7598736db0647eb963e77fafc22af6c0a5747d20", "02b75806a80f8b75c3d6ba2ff97c995117630f36" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 14 09:32:34 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 14 09:32:34 2016 +0000" }, "message": "Merge \"Introduce more compact ReadBarrierMark slow-paths.\"" }, { "commit": "ff484b95b25a5181a6a8a191cbd11da501c97651", "tree": "a14875e1a28afd1c5f7bd6a0a80414674253e593", "parents": [ "1fd347303275a424d114c9833f954e8e27812554" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 13 14:13:48 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 13 16:13:03 2016 +0100" }, "message": "Fix a bug in ClassTableGet code generation for IMTs.\n\nIntroduced by:\n https://android-review.googlesource.com/#/c/244980/\n\ntest:566-polymorphic-inling for fixing x86 crash. Also\nfixes a performance regression.\nbug:29188168\n\nChange-Id: Id90cb819c88e7ba3db1cb3c50c517a112ab7d784\n" }, { "commit": "02b75806a80f8b75c3d6ba2ff97c995117630f36", "tree": "ecdb1852c3e33f120110091cc2d07a9737fbd3b5", "parents": [ "5f485719b166ceb8e591329d40e76c5e50988022" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 13 11:54:35 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 13 11:54:35 2016 +0100" }, "message": "Introduce more compact ReadBarrierMark slow-paths.\n\nReplace entry point ReadBarrierMark with 32\nReadBarrierMarkRegX entry points, using register\nnumber X as input and output (instead of the standard\nruntime calling convention) to save two moves in Baker\u0027s\nread barrier mark slow-path code.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I73cfb82831cf040b8b018e984163c865cc44ed87\n" }, { "commit": "058d934b429513380218b029fc2ee562c7f47696", "tree": "0966acbb887bdb072d793f8bbbd6837367b9f912", "parents": [ "2f378bf675e0fa99cf20ee4c7c5d6b2c0325cf51", "877a0335d3d86ee7e63e25af3f0ed82c89468d51" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 15:02:31 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 12 15:02:31 2016 +0000" }, "message": "Merge \"ARM64: Shorter fast-path for read barrier field load.\"" }, { "commit": "877a0335d3d86ee7e63e25af3f0ed82c89468d51", "tree": "d14daa76937d926481b6a3a5ac987a24cb2f3800", "parents": [ "dedde3f10d7801ad862d1ca1de89135decff6a60" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 11 19:30:56 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 14:50:34 2016 +0100" }, "message": "ARM64: Shorter fast-path for read barrier field load.\n\nReduces the aosp_flounder-userdebug 64-bit boot.oat by\n~4.2MiB, i.e. ~3.5%, in the ART_USE_READ_BARRIER\u003dtrue\nconfiguration.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on Nexus 9.\nBug: 29966877\nBug: 12687968\nChange-Id: Ic9853ec82747a1702e4091fcf9cbf06674fcd5f6\n" }, { "commit": "d8f5f56f2dd90e2bcb6d41cb48403320b9eb04b9", "tree": "6c0c43f98f6c50c799c45449a4a45fa121ab1ba3", "parents": [ "6caea66f9d73b9fe4693090e3b3ceb1cf0b248d1", "54ff482710910929900f8348a19c5b875e519237" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 12 11:07:50 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 12 11:07:50 2016 +0000" }, "message": "Merge \"Rename kCall to kCallOnMainOnly\"" }, { "commit": "54ff482710910929900f8348a19c5b875e519237", "tree": "82667795ef43a33a87a585f9bc841c88ff3460f1", "parents": [ "2e7acaffda05db1df6e0631468f10726e898a20a" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Jul 07 18:03:19 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 11 17:59:29 2016 +0000" }, "message": "Rename kCall to kCallOnMainOnly\n\nThis patch renames kCall to kCallOnMainOnly in preparation for\nthe next patch in this series which will be adding kCallOnMainAndSlowPath.\n\nNote: With this patch there will be places where we use kCallOnMainOnly\neven though we call on the slow path too. The next patch in this series\nwill fix that.\n\nTest: ART host tests.\nChange-Id: Iabfdb0901990d163be5d780f3bdd2fab6fa17b32\n" }, { "commit": "a62cb9bb6cb2278cb41ab0664191623e178c6a4f", "tree": "62263dac644e2d80a34a04f2649e4741a1bed6f4", "parents": [ "bb8d501c9bb882a8927c6ceda07bf9577e06c3e1" ], "author": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Thu Jun 30 09:18:25 2016 +0000" }, "committer": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Thu Jul 07 10:01:04 2016 +0000" }, "message": "Revert \"Revert \"Optimize IMT\"\"\n\nThis reverts commit 88f288e3564d79d87c0cd8bb831ec5a791ba4861.\n\nChange-Id: I49605d53692cbec1e2622e23ff2893fc51ed4115\n" }, { "commit": "88f288e3564d79d87c0cd8bb831ec5a791ba4861", "tree": "dd051a7b2985d1af3fea91ad6000de4bdc701a19", "parents": [ "e36389f20c83083c0aaba2dcac0888951e55cae1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:17:52 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:41:25 2016 +0000" }, "message": "Revert \"Optimize IMT\"\n\nBug: 29188168 (for initial CL)\nBug: 29778499 (reason for revert)\n\nThis reverts commit badee9820fcf5dca5f8c46c3215ae1779ee7736e.\n\nChange-Id: I32b8463122c3521e233c34ca95c96a5078e88848\n" }, { "commit": "e36389f20c83083c0aaba2dcac0888951e55cae1", "tree": "3fe74b637f8dc90e3cbc8ad3949f3f340236537f", "parents": [ "abf64415cf99a9a7ee048ae26c76f7bbe972a6b9", "d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:40:14 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 29 08:40:14 2016 +0000" }, "message": "Merge \"Revert \"Refactor GetIMTIndex\"\"" }, { "commit": "d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c", "tree": "982948a67a88a1f9a734c935f919f8d307969f48", "parents": [ "50706437d8216e41f0fea1e413cda7891324d397" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:39:47 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:39:47 2016 +0000" }, "message": "Revert \"Refactor GetIMTIndex\"\n\nI need to revert this to get https://android-review.googlesource.com/#/c/244190/ to cleanly revert. Matthew, do you mind rewriting it?\n\nThis reverts commit 50706437d8216e41f0fea1e413cda7891324d397.\n\nChange-Id: I5c1435f5dffb46dbb5b613b22adb88c7770304f2\n" }, { "commit": "31167a5785f7a5124de96535066db9890559f546", "tree": "3d0ddb1bb390389532b5fc94dd6f2f5c8d648582", "parents": [ "bad21cb538d76105712c967b62d1cf677777a956", "3d31242300c3525e5c85665d9e34acf87002db63" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 24 13:04:36 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 24 13:04:37 2016 +0000" }, "message": "Merge changes I4d8da7ce,I4da5be01,Idfbead82\n\n* changes:\n Re-enable most intrinsics with read barriers.\n Fix ARM \u0026 ARM64 UnsafeGetObject intrinsics with read barriers.\n Fix x86 \u0026 x86-64 UnsafeGetObject intrinsics with read barriers.\n" }, { "commit": "3d31242300c3525e5c85665d9e34acf87002db63", "tree": "c7f66d95fa3d65241a1c9f10381c1e0ec0989a4e", "parents": [ "bfea33585e229973f7887afbf51fe45c2ba41e91" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 13:53:42 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 14:05:17 2016 +0100" }, "message": "Re-enable most intrinsics with read barriers.\n\nAlso extend sun.misc.Unsafe test coverage to exercise\nsun.misc.Unsafe.{get,put}{Int,Long,Object}Volatile.\n\nBug: 26205973\nBug: 29516905\nChange-Id: I4d8da7cee5c8a310c8825c1631f71e5cb2b80b30\nTest: Covered by ART\u0027s run-tests.\n" }, { "commit": "bfea33585e229973f7887afbf51fe45c2ba41e91", "tree": "018aff4a08f760fc489e5784a2b71e90a29a9084", "parents": [ "0fcd2b84210db2bcf8b2d7a2b98a1a2bca367cac" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 13:48:47 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 14:05:17 2016 +0100" }, "message": "Fix ARM \u0026 ARM64 UnsafeGetObject intrinsics with read barriers.\n\nThe implementation was incorrectly interpreting the \u0027offset\u0027\ninput as an index in a (4-byte) object reference array,\nwhereas it is a (1-byte) offset to an object reference field\nwithin the \u0027base\u0027 (object) input.\n\nBug: 29516905\nChange-Id: I4da5be0193217965f25e5d141c242592dea6ffe8\nTest: Covered by test/004-UnsafeTest.\n" }, { "commit": "4692c35c151951aa1fa901ca24bfa302a9beeacf", "tree": "8d28d7714dd7fa0ae1ff44888ae61f3c8786bfeb", "parents": [ "f6d4f6e0e61977777b7a9ca18b75bcd26e98e9f9", "87f3fcbd0db352157fc59148e94647ef21b73bce" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 16:18:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 21 16:18:10 2016 +0000" }, "message": "Merge \"Replace String.charAt() with HIR.\"" }, { "commit": "87f3fcbd0db352157fc59148e94647ef21b73bce", "tree": "5bdeabb246f5de86704333b3fcbccc6e9146d246", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 28 15:52:11 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 15:17:38 2016 +0100" }, "message": "Replace String.charAt() with HIR.\n\nReplace String.charAt() with HArrayLength, HBoundsCheck and\nHArrayGet. This allows GVN on the HArrayLength and BCE on\nthe HBoundsCheck as well as using the infrastructure for\nHArrayGet, i.e. better handling of constant indexes than\nthe old intrinsic and using the HArm64IntermediateAddress.\n\nBug: 28330359\nChange-Id: I32bf1da7eeafe82537a60416abf6ac412baa80dc\n" }, { "commit": "dbb7f5bef10138ade0fb202da1d61f562b2df649", "tree": "f0aa4b390c534b215a6e000c865783cdd9852353", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 30 13:23:58 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 15:11:57 2016 +0100" }, "message": "Improve HLoadClass code generation.\n\nFor classes in the boot image, use either direct pointers\nor PC-relative addresses. For other classes, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe type\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -252KiB (-0.3%)\n - 64-bit boot.oat: -412KiB (-0.4%)\n - 32-bit dalvik cache total: -392KiB (-0.4%)\n - 64-bit dalvik-cache total: -2312KiB (-1.0%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -124KiB (-0.2%)\n - 64-bit boot.oat: -420KiB (-0.5%)\n - 32-bit dalvik cache total: -136KiB (-0.1%)\n - 64-bit dalvik-cache total: -1136KiB (-0.5%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 27950288\nChange-Id: I4da991a4b7e53c63c92558b97923d18092acf139\n" }, { "commit": "50706437d8216e41f0fea1e413cda7891324d397", "tree": "23c7c5d1198b8cdde6261198626cfe443eab59ba", "parents": [ "badee9820fcf5dca5f8c46c3215ae1779ee7736e" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jun 14 11:31:04 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Wed Jun 15 09:08:35 2016 -0700" }, "message": "Refactor GetIMTIndex\n\nThis allows us to more easily maintain and experiment with\ninterface method table indexing and hashing.\n\nChange-Id: I719920fae7490dcedcda7c1c36db225c2b8b16df\n" }, { "commit": "badee9820fcf5dca5f8c46c3215ae1779ee7736e", "tree": "982948a67a88a1f9a734c935f919f8d307969f48", "parents": [ "614968198625a6693666bdc1e5609e2f663f5638" ], "author": { "name": "Nelli Kim", "email": "nelli.kim@samsung.com", "time": "Fri May 13 13:08:53 2016 +0300" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jun 14 10:05:47 2016 -0700" }, "message": "Optimize IMT\n\n* Remove IMT for classes which do not implement interfaces\n* Remove IMT for array classes\n* Share same IMT\n\nSaved memory (measured on hammerhead):\nboot.art:\nTotal number of classes: 3854\nNumber of affected classes: 1637\nSaved memory: 409kB\n\nChrome (excluding classes in boot.art):\nTotal number of classes: 2409\nNumber of affected classes: 1259\nSaved memory: 314kB\n\nGoogle Maps (excluding classes in boot.art):\nTotal number of classes: 6988\nNumber of affected classes: 2574\nSaved memory: 643kB\n\nPerformance regression on benchmarks/InvokeInterface.java benchmark\n(measured timeCall10Interface)\n1st launch: 9.6%\n2nd launch: 6.8%\n\nChange-Id: If07e45390014a6ee8f3c1c4ca095b43046f0871f\n" }, { "commit": "880f119810869ae8dad3803dfd4d3a02c94a8711", "tree": "df2328d07e0ebde211e64cc0add062a97e2139b5", "parents": [ "cace1ba2ab3a28c335005c73d160d9c0401a0e4e" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Jun 13 16:04:50 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Jun 13 16:04:50 2016 +0100" }, "message": "ARM64: Use VIXL\u0027s conditional select helper.\n\nChange-Id: Id6bb880e2fffb54cf1f480191fc734eaaf4cd293" }, { "commit": "372f10e5b0b34e2bb6e2b79aeba6c441e14afd1f", "tree": "1f29c2467c8909ef0e0147f37f176caa1bcd2ccc", "parents": [ "1b66fdf3f33c72dfdda4d31f6f17b6a0d8607402" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 17 16:30:10 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 02 19:04:20 2016 +0100" }, "message": "Refactor handling of input records.\n\nIntroduce HInstruction::GetInputRecords(), a new virtual\nfunction that returns an ArrayRef\u003c\u003e to all input records.\nImplement all other functions dealing with input records as\nwrappers around GetInputRecords(). Rewrite functions that\npreviously used multiple virtual calls to deal with input\nrecords, especially in loops, to prefetch the ArrayRef\u003c\u003e\nonly once for each instruction. Besides avoiding all the\nextra calls, this also allows the compiler (clang++) to\nperform additional optimizations.\n\nThis speeds up the Nexus 5 boot image compilation by ~0.5s\n(4% of \"Compile Dex File\", 2% of dex2oat time) on AOSP ToT.\n\nChange-Id: Id8ebe0fb9405e38d918972a11bd724146e4ca578\n" }, { "commit": "fba39972d99701c80bf3beb7451aca508d67593c", "tree": "0d80ecb6997290140503926b08a72e7418915526", "parents": [ "718d4e269810c17d03df909c84b2f7bbd4f61fb9" ], "author": { "name": "Chih-Hung Hsieh", "email": "chh@google.com", "time": "Wed May 11 11:26:48 2016 -0700" }, "committer": { "name": "Chih-Hung Hsieh", "email": "chh@google.com", "time": "Fri May 13 10:38:56 2016 -0700" }, "message": "Fix misc-macro-parentheses warnings.\n\n* Add parentheses to fix warnings.\n* Use NOLINT to suppress wrong clang-tidy warnings.\n\nBug: 28705665\nChange-Id: Icc8bc9b59583dee0ea17ab83e0ff0383b8599c3e\n" }, { "commit": "dce016eab87302f02b0bd903dd2cd86ae512df2d", "tree": "3af3c0e6b9d845e611b560484882e6b438ef439a", "parents": [ "a246510965fc57ec51d1b202649304535adfe9f3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 28 13:10:02 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 09 20:40:32 2016 +0100" }, "message": "Intrinsify String.length() and String.isEmpty() as HIR.\n\nUse HArrayLength for String.length() in anticipation of\nchanging the String.charAt() to HBoundsCheck+HArrayGet to\nallow the existing BCE to seamlessly work for strings.\nUse HArrayLength+HEqual for String.isEmpty().\n\nWe previously relied on inlining but we now want to apply\nthe new intrinsics even when we do not inline, i.e. when\ncompiling debuggable (as is currently the case for boot\nimage) or when we hit inlining limits, i.e. depth, size,\nor the number of accumulated dex registers.\n\nBug: 28330359\nChange-Id: Iab9d2f6d2967bdd930a72eb461f27efe8f37c103\n" }, { "commit": "ffc87076dda9878cb2cc098149bae441d38b9268", "tree": "e587208d6a8e62532792add3e1ace6b4e6d73e0f", "parents": [ "97cbc9206e9adc473a90650ebdb5d620f517ff04" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Apr 20 14:22:09 2016 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 28 16:15:04 2016 +0100" }, "message": "Split profile recording from jit compilation\n\nWe still use ProfileInfo objects to record profile information. That\ngives us the flexibility to add the inline caches in the future and the\nconvenience of the already implemented GC.\n\nIf UseJIT is false and SaveProfilingInfo true, we will only record the\nProfileInfo and never launch compilation tasks.\n\nBug: 27916886\n\n(cherry picked from commit e5de54cfab5f14ba0b8ff25d8d60901c7021943f)\n\nChange-Id: I68afc181d71447895fb12346c1806e99bcab1de2\n" }, { "commit": "c01a66465a398ad15da90ab2bdc35b7f4a609b17", "tree": "e85cb2aa05be5c1491814fa83b94748439b8394b", "parents": [ "dad35b0762f97ce79ce3b9a35c9df5021b7dbd17" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "message": "Fix: correctly destruct VIXL labels.\n\nBug: 27505766\nChange-Id: I077465e3d308f4331e7a861902e05865f9d99835" }, { "commit": "93205e395f777c1dd81d3f164cf9a4aec4bde45f", "tree": "1d08efd9b7bca9fe23df9ae9489c5dd575d3c6df", "parents": [ "6990775e323cd9164d6cc10955a047b9d9f15f32" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 13 11:59:46 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 13 17:50:16 2016 +0100" }, "message": "Move Assemblers to the Arena.\n\nAnd clean up some APIs to return std::unique_ptr\u003c\u003e instead\nof raw pointers that don\u0027t communicate ownership.\n\nChange-Id: I3017302307a0253d661240750298802fb0d9585e\n" }, { "commit": "dee58d6bb6d567fcd0c4f39d8d690c3acaf0e432", "tree": "5a2f20546ca3c1544c44bee560062580e22dc79c", "parents": [ "391e155a6936a05bd39b171031ec21d2dee62133" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 09:54:26 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 16:03:16 2016 +0000" }, "message": "Revert \"Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\"\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nThis CL fixed an issue with parsing quickened instructions.\n\nBug: 27894376\nBug: 27998571\nBug: 27995065\n\nChange-Id: I20dbe1bf2d0fe296377478db98cb86cba695e694\n" }, { "commit": "40ecb12f8eeb97b810e11f895278abbf7988ed4d", "tree": "54d999605c0eaf3b4d311f83f8162684506f4a31", "parents": [ "5827507da8efdaf4536c70dfdc54407c28e37852" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 06 17:33:41 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 06 17:33:41 2016 +0100" }, "message": "Optimizing: Fix codegens for MethodLoadKind::kDexCacheViaMethod.\n\nUse the original method index instead of the target method\nindex because the target method may point to a different dex\nfile.\n\nNo regression test: this currently happens only if the\ncodegen uses the kDexCacheViaMethod as a fallback for\nanother load kind and we aim to avoid that fallback, so it\nwould be difficult to write a reliable regression test. We\ncould try and exploit current fallbacks for irreducible\nloops on x86 and arm but those fallbacks will eventually\ndisappear anyway.\n\nBug: 28036230\nChange-Id: I4cc9e046480d3d60a7fb521f0ca6a98914625cdc\n" }, { "commit": "60328910cad396589474f8513391ba733d19390b", "tree": "01702f6df5c39925b354a3152dd04289e7d97062", "parents": [ "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "message": "Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\n\nBug: 27995065\nThis reverts commit e3ff7b293be2a6791fe9d135d660c0cffe4bd73f.\n\nChange-Id: I5363c7ce18f47fd422c15eed5423a345a57249d8\n" }, { "commit": "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f", "tree": "d578d27cb78e6d2caef683cd8ac94c9a9752b192", "parents": [ "86ea7eeabe30c98bbe1651a51d03cb89776724e7" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 02 16:48:20 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 11:21:30 2016 +0100" }, "message": "Refactor HGraphBuilder and SsaBuilder to remove HLocals\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nBug: 27894376\nChange-Id: Iefe28d40600c169c5d306fd2c77034ae19476d90\n" }, { "commit": "cac5a7e871f1f346b317894359ad06fa7bd67fba", "tree": "2df7d4892216a7c976dfe848c9893cb5eb8fa6a5", "parents": [ "6f51d7756a9c66007fe7666b19399e1f60ff6092" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 22 10:39:50 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 29 19:27:40 2016 +0100" }, "message": "Optimizing: Improve const-string code generation.\n\nFor strings in the boot image, use either direct pointers\nor pc-relative addresses. For other strings, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe string\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -692KiB (-0.9%)\n - 64-bit boot.oat: -948KiB (-1.1%)\n - 32-bit dalvik cache total: -900KiB (-0.9%)\n - 64-bit dalvik cache total: -3672KiB (-1.5%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -380KiB (-0.5%)\n - 64-bit boot.oat: -928KiB (-1.0%)\n - 32-bit dalvik cache total: -468KiB (-0.4%)\n - 64-bit dalvik cache total: -1928KiB (-0.8%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 26884697\nChange-Id: Iec7266ce67e6fedc107be78fab2e742a8dab2696\n" }, { "commit": "0ced281ae6216c29f57ca0f8b7388a722e8da97b", "tree": "b7f8273bb117c8ec8f8546ed937a8c0a96d2e5de", "parents": [ "843a65556616183a36792bbcc1632c6d8d0e78b2", "1a65388f1d86bb232c2e44fecb44cebe13105d2e" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Mar 24 10:25:51 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 24 10:25:51 2016 +0000" }, "message": "Merge \"Clean up art::HConstant predicates.\"" }, { "commit": "5b5b9319ff970979ed47d41a41283e4faeffb602", "tree": "e7795abf120cf512627786fd6302efd34535724b", "parents": [ "0c25da0276f5b6f6119793ae9d45d1bca8172c2b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 22 14:57:31 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 22 14:57:31 2016 +0000" }, "message": "Fix and improve shift and rotate operations.\n\n- Define maximum int and long shift \u0026 rotate distances as\n int32_t constants, as shift \u0026 rotate distances are 32-bit\n integer values.\n- Consider the (long, long) inputs case as invalid for\n static evaluation of shift \u0026 rotate rotations.\n- Add more checks in shift \u0026 rotate operations constructors\n as well as in art::GraphChecker.\n\nChange-Id: I754b326c3a341c9cc567d1720b327dad6fcbf9d6\n" }, { "commit": "1a65388f1d86bb232c2e44fecb44cebe13105d2e", "tree": "515e3000b3ad6d195101f20f33f3c9498e536593", "parents": [ "f808e8a0cc218c2b98023ef0e91f3c5b74ad2962" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Mar 18 18:05:57 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Mar 18 18:05:57 2016 +0000" }, "message": "Clean up art::HConstant predicates.\n\n- Make the difference between arithmetic zero and zero-bit\n pattern non ambiguous.\n- Introduce Boolean predicates in art::HIntConstant for when\n they are used as Booleans.\n- Introduce aritmetic positive and negative zero predicates\n for floating-point constants.\n\nBug: 27639313\nChange-Id: Ia04ecc6f6aa7450136028c5362ed429760c883bd\n" }, { "commit": "e943c3b831dc0da4a6b09e940ae25c3285850e96", "tree": "b4756bbc16f49d50087a881b40722657451e6eac", "parents": [ "7c06aef061fa176331b77a88c1ff2c6ae401a5f0", "d28f4a00933a4a3b8d5e9db73b8532924d0f989d" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Mar 18 12:37:03 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 18 12:37:03 2016 +0000" }, "message": "Merge \"Generate native debug stackmaps before calls as well.\"" }, { "commit": "d28f4a00933a4a3b8d5e9db73b8532924d0f989d", "tree": "1205844a68ee9e2c502f8ecbfd2d5cf96acd4190", "parents": [ "fbc61e19578d281d05728bcd120e1ace57c2fbd8" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Mar 14 17:14:24 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Mar 17 16:58:55 2016 +0000" }, "message": "Generate native debug stackmaps before calls as well.\n\nThe debugger looks up PC of the call instruction, so the runtime\u0027s\nstackmap is not sufficient since it is at PC after the instruction.\n\nChange-Id: I0dd06c0b52e8079ea5d064ea10beb12c93584092\n" }, { "commit": "a5c4a4060edd03eda017abebc85f24cffb083ba7", "tree": "85f69512d33c19d82e172a490a241f3a17d66560", "parents": [ "713c519db15aaa8d6f33b744fd28adddb97a07c2" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 15 15:02:50 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Mar 16 16:49:36 2016 +0000" }, "message": "Make art::HCompare support boolean, byte, short and char inputs.\n\nAlso extend tests covering the IntegerSignum, LongSignum,\nIntegerCompare and LongCompare intrinsics and their\ntranslation into an art::HCompare instruction.\n\nBug: 27629913\nChange-Id: I0afc75ee6e82602b01ec348bbb36a08e8abb8bb8\n" }, { "commit": "914d71ead70bb6f2084b2ed39a9fd58fd014f67d", "tree": "50f30d6e47d18aa6c3ccec9f05727b4898268b20", "parents": [ "1583e624d4c970d8e571b265b9a8f08402d91f82", "2ae48182573da7087bffc2873730bc758ec29696" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:40:08 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 16 14:40:08 2016 +0000" }, "message": "Merge \"Clean up NullCheck generation and record stats about it.\"" }, { "commit": "2ae48182573da7087bffc2873730bc758ec29696", "tree": "d6955329ad876aefd477f7ef8905b070b9ab95dd", "parents": [ "6915898b28cea6c9836ca1be6814d87e89cc6d76" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:05:09 2016 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:10:27 2016 +0000" }, "message": "Clean up NullCheck generation and record stats about it.\n\nThis removes redundant code from the generators and allows for easier\nstat recording.\n\nChange-Id: Iccd4368f9e9d87a6fecb863dee4e2145c97851c4\n" }, { "commit": "e5671618d19489ad0781ec0d204c7765317170cf", "tree": "317d451ebf639f89e91d4c1e482d950579da0a0f", "parents": [ "d35f4a2eacf9ee9c9d75bb0c00eec7ae31ad1949" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 11:03:54 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 11:14:20 2016 +0000" }, "message": "Accept boolean as an input of HDivZeroCheck.\n\nAll our arithmetic operations accept it.\n\nbug:27624718\nChange-Id: I1f6bb95dc77ecb3fb2fcabb35a93b31c524bfa0a\n" }, { "commit": "7fc6350f6f1ab04b52b9cd7542e0790528296cbe", "tree": "26a33ef7bb2e49a9b7c7d9436194a92cb447b317", "parents": [ "b7f257f353b1eb2db2732939a0404c118316891d" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Feb 09 17:15:29 2016 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Mar 11 12:49:27 2016 +0000" }, "message": "Integrate BitwiseNegated into shared framework.\n\nShare implementation between arm and arm64.\n\nChange-Id: I0dd12e772cb23b4c181fd0b1e2a447470b1d8702\n" }, { "commit": "01c30e8dbc45bdc5d922cef6e5a404be7bed0e8c", "tree": "45d5c735386d3253e65a986b15e3eab9b9bf75cd", "parents": [ "af86c4e44184bd17411de330d48aad7784d569d4", "a1de9188a05afdecca8cd04ecc4fefbac8b9880f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Feb 26 16:39:57 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Feb 26 16:39:57 2016 +0000" }, "message": "Merge \"Optimizing: Reduce memory usage of HInstructions.\"" }, { "commit": "a1de9188a05afdecca8cd04ecc4fefbac8b9880f", "tree": "a671c8aef814ccf194e5c3950a551f2711516c53", "parents": [ "950d063395c7cecbbe372fd607468018d661a35c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Feb 25 11:37:38 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Feb 26 16:01:59 2016 +0000" }, "message": "Optimizing: Reduce memory usage of HInstructions.\n\nPack narrow fields and flags into a single 32-bit field.\n\nChange-Id: Ib2f7abf987caee0339018d21f0d498f8db63542d\n" }, { "commit": "9ff0d205fd60cba6753a91f613b198ca2d67f04d", "tree": "86689672064d66d2c473045f934f948211ba0389", "parents": [ "950d063395c7cecbbe372fd607468018d661a35c" ], "author": { "name": "Kevin Brodsky", "email": "kevin.brodsky@linaro.org", "time": "Mon Jan 11 13:43:31 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 25 16:26:13 2016 +0000" }, "message": "Optimizing: ARM64 negated bitwise operations simplification\n\nUse negated instructions on ARM64 to replace [bitwise operation + not]\npatterns, that is:\na \u0026 ~b (BIC)\na | ~b (ORN)\na ^ ~b (EON)\n\nThe simplification only happens if the Not is only used by the bitwise\noperation. It does not happen if both inputs are Not\u0027s (this should be\nhandled by a generic simplification applying De Morgan\u0027s laws).\n\nChange-Id: I0e112b23fd8b8e10f09bfeff5994508a8ff96e9c\n" }, { "commit": "4a0dad67867f389e01a5a6c0fe381d210f687c0d", "tree": "91f1e70f4a2d0bd32aa7eb51e546f5330d72f772", "parents": [ "d15ede2df7d157ea5480614fd18c2bf0d37a6c2a" ], "author": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Tue Jan 26 12:28:31 2016 +0300" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Feb 25 10:14:30 2016 +0000" }, "message": "Revert \"Revert \"ARM/ARM64: Extend support of instruction combining.\"\"\n\nThis reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.\n\nChange-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6\n" }, { "commit": "9cd6d378bd573cdc14d049d32bdd22a97fa4d84a", "tree": "be293c89806b919143b7dcd203bae14f5f4eaf04", "parents": [ "0e02ee9efbf1dbdde05d2b10f7307bbe191c52f5" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 15:24:47 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:25:29 2016 +0000" }, "message": "Associate slow paths with the instruction that they belong to.\n\nAlmost all slow paths already know the instruction they belong to,\nthis CL just moves the knowledge to the base class as well.\n\nThis is needed to be be able to get the corresponding dex pc for\nslow path, which allows us generate better native line numbers,\nwhich in turn fixes some native debugging stepping issues.\n\nChange-Id: I568dbe78a7cea6a43a4a71a014b3ad135782c270\n" }, { "commit": "c7098ff991bb4e00a800d315d1c36f52a9cb0149", "tree": "3a150e927bc7f4894f5b148ec6f5a2b796cdd80d", "parents": [ "5322e55ab9a15996a197456ca39d9c77488cd5c1" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 14:30:11 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:21:57 2016 +0000" }, "message": "Remove HNativeDebugInfo from start of basic blocks.\n\nWe do not require full environment at the start of basic block.\nThe dex pc contained in basic block is sufficient for line mapping.\n\nChange-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa\n" }, { "commit": "c0b601b5e4c1add5eefd45f2f4d2c376a20ba4d4", "tree": "5afda879812dd7984f2d5970d4ff4ab3bc22a7d0", "parents": [ "b3ba4ec3fac34f0a45aa654ef88033b2f34c3640" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Feb 08 14:20:45 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Feb 15 13:11:04 2016 +0000" }, "message": "ART: Implement HSelect with CSEL/FCSEL on arm64\n\nChange-Id: I549af0cba3c5048066a2d1206b78a70b496d349e\n" }, { "commit": "6e332529c33be4d7dae5dad3609a839f4c0d3bfc", "tree": "cedd2e1beb170fd5821136fe974e3f34adfcddc2", "parents": [ "d3caabd4f85f86dd744da432993e12935d843a83" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Feb 02 16:15:27 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Feb 12 15:17:50 2016 +0000" }, "message": "ART: Remove HTemporary\n\nChange-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03\n" }, { "commit": "ca0bf0349f8da35b284df49732e30eeb62591034", "tree": "5275be61f01748fc01137147740a19b30f2142a6", "parents": [ "f637d80872d418fc62ee1d40b19e1f5a676d1399" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Feb 09 12:49:18 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Feb 09 12:49:18 2016 +0000" }, "message": "Fix ARM64 Baker\u0027s read barrier fast path for ArraySet.\n\nDo not exhaust the pool of scratch (temporary) registers\ngratuitously when emitting an instrumented array load with a\nlarge constant index.\n\nBug: 26817006\nBug: 12687968\nChange-Id: I65a4fe676aa3c9e2c8d7e26195d9af6432c83ff9\n" }, { "commit": "a19616e3363276e7f2c471eb2839fb16f1d43f27", "tree": "ad3e7fd0f53229e95fb0443586fc30eedabe6967", "parents": [ "9fba3f67a0792ad5eeb495e489d11a87211c318f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 01 18:57:58 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Feb 05 09:26:21 2016 -0800" }, "message": "Implemented compare/signum intrinsics as HCompare\n(with all code generation for all)\n\nRationale:\nAt HIR level, many more optimizations are possible, while ultimately\ngenerated code can take advantage of full semantics.\n\nChange-Id: I6e2ee0311784e5e336847346f7f3c4faef4fd17e\n" }, { "commit": "5f16c05407ed5f7f72fa761263fd5eac37de0077", "tree": "69983c047840a25851ad570eb838675284ccaa56", "parents": [ "b86f963ce95b25bfae892fa425ab02f2fb706f87", "4a6a67ca93289b232a620bdf8bf30ff8b7b0b428" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Feb 02 14:36:58 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Feb 02 14:36:58 2016 +0000" }, "message": "Merge \"Remove unused DMB code paths in the ARM64 Optimizing Compiler\"" }, { "commit": "9ff1de06d6ed1da36f7e976224a2d13e5e9882bf", "tree": "9121c384f3e0375fccfa4ca9f71c7d86baf38904", "parents": [ "bee600ff66e3e233274faa1391890ff424a8244e", "a42363f79832a6e14f348514664dc6dc3edf9da2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 28 16:09:16 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 28 16:09:16 2016 +0000" }, "message": "Merge \"Implement first kind of polymorphic inlining.\"" }, { "commit": "a42363f79832a6e14f348514664dc6dc3edf9da2", "tree": "bcd43acdf9903a704b566af00b5c740786284b7b", "parents": [ "9cea9139033a4d04437ebc5542e9466fd67137fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 17 14:57:09 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 28 15:55:46 2016 +0000" }, "message": "Implement first kind of polymorphic inlining.\n\nAdd HClassTableGet to fetch an ArtMethod from the vtable or imt,\nand compare it to the only method the profiling saw.\n\nChange-Id: I76afd3689178f10e3be048aa3ac9a97c6f63295d\n" }, { "commit": "74eb1b264691c4eb399d0858015a7fc13c476ac6", "tree": "0b6fc4f3003d50bf6c388601013cdfc606e53859", "parents": [ "75fd2a8ab9b4aff59308034da26eb4986d10fa9e" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Dec 14 11:44:01 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 28 15:50:27 2016 +0000" }, "message": "ART: Implement HSelect\n\nThis patch adds a new HIR instruction to Optimizing. HSelect returns\none of two inputs based on the outcome of a condition.\n\nThis is only initial implementation which:\n - defines the new instruction,\n - repurposes BooleanSimplifier to emit it,\n - extends InstructionSimplifier to statically resolve it,\n - updates existing code and tests accordingly.\n\nCode generators currently emit fallback if/then/else code and will be\nupdated in follow-up CLs to use platform-specific conditional moves\nwhen possible.\n\nChange-Id: Ib61b17146487ebe6b55350c2b589f0b971dcaaee\n" }, { "commit": "b3e773eea39a156b3eacf915ba84e3af1a5c14fa", "tree": "6c0d3a748d7b445a0d776ed306c7add43a0e1dd3", "parents": [ "05aeb408f292d8d94af1646a94bc69faf77f0b46" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Jan 26 11:28:37 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 28 15:48:00 2016 +0000" }, "message": "ART: Implement support for instruction inlining\n\nOptimizing HIR contains \u0027non-materialized\u0027 instructions which are\nemitted at their use sites rather than their defining sites. This\nwas not properly handled by the liveness analysis which did not\nadjust the use positions of the inputs of such instructions.\nDespite the analysis being incorrect, the current use cases never\nproduce incorrect code.\n\nThis patch generalizes the concept of inlined instructions and\nupdates liveness analysis to set the compute use positions correctly.\n\nChange-Id: Id703c154b20ab861241ae5c715a150385d3ff621\n" }, { "commit": "4a6a67ca93289b232a620bdf8bf30ff8b7b0b428", "tree": "54e8c8fad3de00a8edd2fb8766bdfb0e2b6fc533", "parents": [ "2aaf58e90c9229610b2a16644e9866b6741ce9ca" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Jan 27 09:19:56 2016 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Jan 27 21:24:08 2016 +0000" }, "message": "Remove unused DMB code paths in the ARM64 Optimizing Compiler\n\nCurrently all ARM64 CPUs will be using the acquire-release code paths.\nThis patch removes the instruction set feature PreferAcquireRelease()\nas well as all the unused DMB code paths.\n\nChange-Id: I61c320d6d685f96c9e260f25eac3593907793830\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "7d9f95f29d07c455c3ab76d89b7952755a3e0a28", "tree": "155e5e1f0a88f5d5c713f3a248741389bdc8c5b0", "parents": [ "a7d507eb0fc55240700232a0b6269d1388e9b5a5", "44015868a5ed9f6915d510ade42e84949b719e3a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 14:20:37 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jan 22 14:20:37 2016 +0000" }, "message": "Merge \"Revert \"Revert \"ARM64 Baker\u0027s read barrier fast path implementation.\"\"\"" }, { "commit": "44015868a5ed9f6915d510ade42e84949b719e3a", "tree": "c23fd6c5de3d727ff310ef6fe06574a502133150", "parents": [ "28a2ff0bd6c30549f3f6465d8316f5707b1d072f" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:47:17 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:47:17 2016 +0000" }, "message": "Revert \"Revert \"ARM64 Baker\u0027s read barrier fast path implementation.\"\"\n\nThis reverts commit 28a2ff0bd6c30549f3f6465d8316f5707b1d072f.\n\nBug: 12687968\nChange-Id: I6e25c70f303368629cdb1084f1d7039261cbb79a\n" }, { "commit": "6b5afdd144d2bb3bf994240797834b5666b2cf98", "tree": "d536cd7b3aaf55c563e82c2c522521a91b2bb953", "parents": [ "debeb98aaa8950caf1a19df490f2ac9bf563075b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 22 09:31:52 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 22 09:31:52 2016 +0000" }, "message": "Revert \"ARM/ARM64: Extend support of instruction combining.\"\n\nThe test fails its checker parts.\n\nThis reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.\n\nChange-Id: I49929e15950c7814da6c411ecd2b640d12de80df\n" }, { "commit": "28a2ff0bd6c30549f3f6465d8316f5707b1d072f", "tree": "4d181bd254584f78cf1f3d81d3acb23d6f2f8b3d", "parents": [ "c8f1df9965ca7f97ba9e6289f8c7a717765a59a9" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jan 21 18:21:59 2016 +0000" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jan 21 18:21:59 2016 +0000" }, "message": "Revert \"ARM64 Baker\u0027s read barrier fast path implementation.\"\n\nThis reverts commit c8f1df9965ca7f97ba9e6289f8c7a717765a59a9.\n\nThis breaks master.\n\nChange-Id: Ic07f602af8732e2835bd11f65e3b9e766d3349c7\n" }, { "commit": "debeb98aaa8950caf1a19df490f2ac9bf563075b", "tree": "b2a7a7cc6fb2f56d4bcc6cecaa80035668f38dc4", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Ilmir Usmanov", "email": "i.usmanov@samsung.com", "time": "Fri Dec 11 11:39:44 2015 +0300" }, "committer": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Thu Jan 21 11:07:38 2016 +0300" }, "message": "ARM/ARM64: Extend support of instruction combining.\n\nCombine multiply instructions in the following way:\nARM64:\nMUL/NEG -\u003e MNEG\nARM32 (32-bit integers only):\nMUL/ADD -\u003e MLA\nMUL/SUB -\u003e MLS\n\nChange-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb\n" }, { "commit": "086d27e2ef9d11138f8832190d09a56e72346f15", "tree": "30217b1a5b8bb0cfdb6c351058678a7ad128950f", "parents": [ "0021c310e2e613d6d180acda0d9d422dba8688b0" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 20 17:02:00 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 20 19:19:24 2016 -0800" }, "message": "Fix missing case in ARM64 codegen.\n\nRationale:\nRather than excluding conditions that are not handled,\nchanged the right-hand-side is zero optimized code\nto list handled conditions explicitly instead.\n\nbug\u003d26689526\n\nChange-Id: I636e01548659c579d9e318f07bda2c24a12371e5\n" }, { "commit": "c8f1df9965ca7f97ba9e6289f8c7a717765a59a9", "tree": "7c04fd5601293cc251651ce2df2dfd2416737a1c", "parents": [ "fef7aabd582ae0237a44947c5e0b24cb63e395f0" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jan 20 16:38:05 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jan 20 16:38:05 2016 +0000" }, "message": "ARM64 Baker\u0027s read barrier fast path implementation.\n\nIntroduce an ARM64 fast path implementation in Optimizing\nfor Baker\u0027s read barriers (for both heap reference loads and\nGC root loads). The marking phase of the read barrier is\nperformed by a slow path, invoking the runtime entry point\nartReadBarrierMark.\n\nOther read barrier algorithms continue to use the original\nslow path based implementation, which has been renamed as\nGenerateReadBarrierSlow/GenerateReadBarrierForRootSlow.\n\nBug: 12687968\nBug: 26601270\nChange-Id: I60da15249b58a8ee1a065ed9be2c4e438ee17150\n" }, { "commit": "955d24c4221aa514067dc13d8a40c8b5071f467d", "tree": "67a527b7e8360579d233ece14b1bb6718b39777a", "parents": [ "ae9f99e2973edd24302b893d109224e8b05dbdf6", "58282f4510961317b8d5a364a6f740a78926716f" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 17:13:14 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 18 17:13:14 2016 +0000" }, "message": "Merge \"ART: Remove Baseline compiler\"" }, { "commit": "58282f4510961317b8d5a364a6f740a78926716f", "tree": "5d97c0db9fe01dd6e8df2357ef11f614abb853e8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 12:45:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 16:39:30 2016 +0000" }, "message": "ART: Remove Baseline compiler\n\nWe don\u0027t need Baseline any more and it hasn\u0027t been maintained for\na while anyway. Let\u0027s remove it.\n\nChange-Id: I442ed26855527be2df3c79935403a25b1ee55df6\n" }, { "commit": "d6e069b16a7d4964e546daf3d340ea11756ab090", "tree": "3b6509b03527e2cb0d9135bdccb02ddf9ea00cd8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 18 11:11:01 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 18 13:16:48 2016 +0000" }, "message": "Optimizing: Improve floating point comparisons on arm and arm64.\n\nAvoid the extra check for unordered inputs by using the\nappropriate arm/arm64 condition.\n\nChange-Id: Ib5e775a90428db7a2cf377ad9fd6a3192d670617\n" }, { "commit": "cd3d0fb5a4c113cfdb610454d133762a2ab0e6de", "tree": "482d31703326300fd8c53a2ebbfe6dbf58a74448", "parents": [ "8c8e997d29fadaa9bfb4007e95a8cd6cb76d6e80" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 15 19:26:48 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Sun Jan 17 11:58:18 2016 +0000" }, "message": "Do not use HArm64IntermediateAddress with read barriers.\n\nThis ARM64 instruction simplification does not yet work\ncorrectly with the read barrier compiler instrumentation.\n\nBug: 26601270\nBug: 12687968\nChange-Id: I0c3c5d0043ebd936e00984740efbae8b3025c7ca\n" }, { "commit": "6de1938e562b0d06e462512dd806166e754035ea", "tree": "f9df086a73860c20768d17ff7bc5be4139567941", "parents": [ "f5b84ee14a3bc578f799a39dca1ae512b49356ea" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jan 08 17:37:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 16:22:13 2016 +0000" }, "message": "ART: Remove incorrect HFakeString optimization\n\nSimplification of HFakeString assumes that it cannot be used until\nString.\u003cinit\u003e is called which is not true and causes different\nbehaviour between the compiler and the interpreter. This patch\nremoves the optimization together with the HFakeString instruction.\n\nInstead, HNewInstance is generated and an empty String allocated\nuntil it is replaced with the result of the StringFactory call. This\nis consistent with the behaviour of the interpreter but is too\nconservative. A follow-up CL will attempt to optimize out the initial\nallocation when possible.\n\nBug: 26457745\nBug: 26486014\n\nChange-Id: I7139e37ed00a880715bfc234896a930fde670c44\n" }, { "commit": "42249c3602c3d0243396ee3627ffb5906aa77c1e", "tree": "1e822a21c87331246cbde3923eac88fa315fa2cc", "parents": [ "922698ded1e80cad1ecce4c2172a88c76a216373" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 07 15:33:50 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 12 16:39:20 2016 -0800" }, "message": "Reduce code size by sharing slow paths.\n\nRationale:\nSharing identical slow path code reduces code size.\n\nBackground:\nCurrently, slow paths with the same dex-pc, same physical register\nspilling code, and identical stack maps are shared (making this\nonly useful for deopt slow paths). The newly introduced mechanism\nis sufficiently general to allow future improvements by e.g.\nallowing different dex-pc (by passing this to runtime) or even\nthe kind of slow paths (by passing runtime addresses to the slowpath).\n\nChange-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0\n" }, { "commit": "8566a91502db625ff9428a3c2418714488ecd5d9", "tree": "fc3ade71413203fd053d06b98210f263084e34c9", "parents": [ "20b6863769357d798464a65c5ee5dfd64464d400", "b7070a2db8b0b7eca14f01f932be305be64ded57" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Jan 11 14:47:37 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 11 14:47:37 2016 +0000" }, "message": "Merge \"Generate Nops to ensure that debug stack maps have distinct PC.\"" } ], "next": "b7070a2db8b0b7eca14f01f932be305be64ded57" }