)]}' { "log": [ { "commit": "e3b034a6f6f0d80d519ab08bdd18be4de2a4a2db", "tree": "660cc713e0ad2d71ccd1e0af1399c92665b626c7", "parents": [ "119a8025bbc1c6f4a2d537e9a6d22f33ef31e552" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Sun May 31 14:29:23 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Sun May 31 17:36:10 2015 -0700" }, "message": "Fix some ArtMethod related bugs\n\nAdded root visiting for runtime methods, not currently required\nsince the GcRoots in these methods are null.\n\nAdded missing GetInterfaceMethodIfProxy in GetMethodLine, fixes\n--trace run-tests 005, 044.\n\nFixed optimizing compiler bug where we used a normal stack location\ninstead of double on ARM64, this fixes the debuggable tests.\n\nTODO: Fix JDWP tests.\n\nBug: 19264997\n\nChange-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "b176d7c6c8c01a50317f837a78de5da57ee84fb2", "tree": "81ec0c16267c527bdc64923b374be915206e6af9", "parents": [ "713c59e813daa92da3f1678add6c4c7e16dcff11" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 20 18:48:31 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 21 12:10:00 2015 +0100" }, "message": "Also encode the InvokeType in an InlineInfo.\n\nThis will be needed to recover the call stack.\n\nChange-Id: I2fe10785eb1167939c8cce1862b2d7f4066e16ec\n" }, { "commit": "b1d0f3f7e92fdcc92fe2d4c48cbb1262c005583f", "tree": "0e3ce752f82ff5d7f10d37d46bda058ca54d7e40", "parents": [ "119b21a6dfdb09d983a9e56a837fbf5c98e57096" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 14 12:41:51 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 13:00:29 2015 +0100" }, "message": "Support InlineInfo in StackMap.\n\nChange-Id: I9956091775cedc609fdae7dec1433fcb8858a477\n" }, { "commit": "0a23d74dc2751440822960eab218be4cb8843647", "tree": "39d69de5d812826c4065d0acd38a58cd983f21f0", "parents": [ "cdeb0b5fede4c06488f43a212591e661d946bc78" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 07 11:57:35 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 11 14:17:22 2015 +0100" }, "message": "Add a parent environment to HEnvironment.\n\nThis code has no functionality change. It adds a placeholder\nfor chaining inlined frames.\n\nChange-Id: I5ec57335af76ee406052345b947aad98a6a4423a\n" }, { "commit": "3e3d73349a2de81d14e2279f60ffbd9ab3f3ac28", "tree": "69ad3378263c9a4b967cb7e27de0027264c12eb6", "parents": [ "a0ee862288b702468f8c2b6d0ad0f1c61be0b483" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 11:00:54 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 11:00:54 2015 +0100" }, "message": "Have HInvoke instructions know their number of actual arguments.\n\nAdd an art::HInvoke::GetNumberOfArguments routine so that\nart::HInvoke and its subclasses can return the number of\nactual arguments of the called method. Use it in code\ngenerators and intrinsics handlers.\n\nConsequently, no longer remove a clinit check as last input\nof a static invoke if it is still present during baseline\ncode generation, but ensure that static invokes have no such\ncheck as last input in optimized compilations.\n\nChange-Id: Iaf9e07d1057a3b15b83d9638538c02b70211e476\n" }, { "commit": "4f46ac5179967dda5966f2dcecf2cf08977951ef", "tree": "4c9ea50d9a135767c6e9a4abcf9b9c401a033414", "parents": [ "4ceed922d44b68c3fa7cbe670014c9e2e003b92b" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 23 18:47:21 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 23 19:58:22 2015 +0100" }, "message": "Cleanup and improve stack map stream\n\n- transform AddStackMapEntry into BeginStackMapEntry/EndStackMapEntry.\nThis allows for nicer code and less assumptions when searching for equal\ndex register maps.\n- store the components sizes and their start positions as fields to\navoid re-computation.\n- store the current stack map entry as a field to avoid the copy\nsemantic when updating its value in the stack maps array.\n- remove redundant methods and fix visibility for the remaining ones.\n\nChange-Id: Ica2d2969d7e15993bdbf8bc41d9df083cddafd24\n" }, { "commit": "641547a5f18ca2ea54469cceadcfef64f132e5e0", "tree": "441e325fc9bea377c549101756d9e8dc68f95779", "parents": [ "296c6cc2e5e90a81bdfc5f5486eae6b64d80e595" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Apr 21 22:08:51 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Apr 22 11:40:25 2015 +0100" }, "message": "[optimizing] Fix a bug in moving the null check to the user.\n\nWhen taking the decision to move a null check to the user we did not\nverify if the next instruction checks the same object.\n\nChange-Id: I2f4533a4bb18aa4b0b6d5e419f37dcccd60354d2\n" }, { "commit": "88c13cddc3a4184908662b0f3de796565d348c76", "tree": "6986849099ff7afc042eac31a3e53df0c468962b", "parents": [ "f458ba7d9c04bc8d499532b5470af28db18e4149" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Apr 14 17:35:39 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 20 11:35:44 2015 +0100" }, "message": "Opt compiler: Correctly require register or FPU register.\n\nAlso add a check that location summary are correctly typed\nwith the HInstruction.\n\nChange-Id: I699762ff4e8f4e321c7db01ea005236ea1934af9\n" }, { "commit": "9021825d1e73998b99c81e89c73796f6f2845471", "tree": "13e1038931cbb8bf8b8d0f4e3f51553ba1bfa983", "parents": [ "858d28ca2e73a785977f53141e775a7d4841b89d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 11:56:51 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 12:53:42 2015 +0100" }, "message": "Type MoveOperands.\n\nThe ParallelMoveResolver implementation needs to know if a move\nis for 64bits or not, to handle swaps correctly.\n\nBug found, and test case courtesy of Serguei I. Katkov.\n\nChange-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506\n" }, { "commit": "c6b4dd8980350aaf250f0185f73e9c42ec17cd57", "tree": "ef8d73e37abc04aecb430072a8bc463c73398fee", "parents": [ "dd97393aca1a3ff2abec4dc4f78d7724300971bc" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:32:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 16:47:50 2015 +0100" }, "message": "Implement CFI for Optimizing.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2\n" }, { "commit": "65b798ea10dd716c1bb3dda029f9bf255435af72", "tree": "774e9901b6917989a63f07f927c3b4d8b921a013", "parents": [ "c411c6cc327d3f2b3b4d1987b07dd442205d9454" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 09:35:22 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 14:05:07 2015 -0700" }, "message": "ART: Enable more Clang warnings\n\nChange-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c\n" }, { "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c", "tree": "01b21964ce0516bda835faa15b260ac290714fe0", "parents": [ "dcff612c3a6e1427749771c4559f198fa480f709" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 22:16:59 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 08:45:38 2015 -0400" }, "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures. Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b64b782f9ae7a94ecbbf64c83cbcdc7d716ba560", "tree": "df3aa814ff7762d681c50781c413fd510440ae61", "parents": [ "2c2d00e8ca841aa2f57fa2f852e896378ef67144", "46e2a3915aa68c77426b71e95b9f3658250646b7" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 24 17:31:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 24 17:31:31 2015 +0000" }, "message": "Merge \"ART: Boolean simplifier\"" }, { "commit": "46e2a3915aa68c77426b71e95b9f3658250646b7", "tree": "2b0a4470b05291894db73c631fe94f0fdff8c46b", "parents": [ "bce0855ca1dbb1fa226c5b6a81760272ce0b64ef" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Mar 16 17:31:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 24 17:28:37 2015 +0000" }, "message": "ART: Boolean simplifier\n\nThe optimization recognizes the negation pattern generated by \u0027javac\u0027\nand replaces it with a single condition. To this end, boolean values\nare now consistently assumed to be represented by an integer.\n\nThis is a first optimization which deletes blocks from the HGraph and\ndoes so by replacing the corresponding entries with null. Hence,\nexisting code can continue indexing the list of blocks with the block\nID, but must check for null when iterating over the list.\n\nChange-Id: I7779da69cfa925c6521938ad0bcc11bc52335583\n" }, { "commit": "da4d79bc9a4aeb9da7c6259ce4c9c1c3bf545eb8", "tree": "151dd61c4b6a8fd512ea4c2c862af28b02f4ed9c", "parents": [ "af87659f462ac650009fce295097cae3dabce171" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 24 14:36:11 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 24 16:02:21 2015 +0000" }, "message": "Unify ART\u0027s various implementations of bit_cast.\n\nART had several implementations of art::bit_cast:\n\n1. one in runtime/base/casts.h, declared as:\n\n template \u003cclass Dest, class Source\u003e\n inline Dest bit_cast(const Source\u0026 source);\n\n2. another one in runtime/utils.h, declared as:\n\n template\u003ctypename U, typename V\u003e\n static inline V bit_cast(U in);\n\n3. and a third local version, in runtime/memory_region.h,\n similar to the previous one:\n\n template\u003ctypename Source, typename Destination\u003e\n static Destination MemoryRegion::local_bit_cast(Source in);\n\nThis CL removes versions 2. and 3. and changes their callers\nto use 1. instead. That version was chosen over the others\nas:\n- it was the oldest one in the code base; and\n- its syntax was closer to the standard C++ cast operators,\n as it supports the following use:\n\n bit_cast\u003cDestination\u003e(source)\n\n since `Source\u0027 can be deduced from `source\u0027.\n\nChange-Id: I7334fd5d55bf0b8a0c52cb33cfbae6894ff83633\n" }, { "commit": "eeefa1276e83776f08704a3db4237423b0627e20", "tree": "d7c647ca77703f3712f567704f40b00d59a125de", "parents": [ "02c0bac34c246c1bd974dbb86d292d4b52ba98e4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:52:59 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 16 10:48:21 2015 +0000" }, "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n" }, { "commit": "02c0bac34c246c1bd974dbb86d292d4b52ba98e4", "tree": "83774758f02a48a0b59e042d2c6f4a4a7edf60a2", "parents": [ "ccac273186a7f624ee20d1a3e19ea34bb3fd305f", "fead4e4f397455aa31905b2982d4d861126ab89d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:46:44 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 13 18:46:44 2015 +0000" }, "message": "Merge \"[optimizing] Don\u0027t record None locations in the stack maps.\"" }, { "commit": "fead4e4f397455aa31905b2982d4d861126ab89d", "tree": "21e4ccd99472bbf5cf1fac3bc20d0bca6f176022", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 14:39:40 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:28:19 2015 +0000" }, "message": "[optimizing] Don\u0027t record None locations in the stack maps.\n\n- moved environment recording from code generator to stack map stream\n- added creation/loading factory methods for the DexRegisterMap (hides\ninternal details)\n- added new tests\n\nChange-Id: Ic8b6d044f0d8255c6759c19a41df332ef37876fe\n" }, { "commit": "a8ac9130b872c080299afacf5dcaab513d13ea87", "tree": "2bd0a2a88cbb6e7a3ae79dff84c466bed9189eb5", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:36:36 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:47:44 2015 +0000" }, "message": "Refactor code in preparation of correct stack maps in slow path.\n\nMove the logic of saving/restoring live registers in slow path\nin the SlowPathCode method. Also add a RecordPcInfo helper to\nSlowPathCode, that will act as the placeholder of saving correct\nstack maps.\n\nChange-Id: I25c2bc7a642ef854bbc8a3eb570e5c8c8d2d030c\n" }, { "commit": "a4d120c88e79eece333e66eec64c4e909d770e3e", "tree": "086e8196778127b9bbd77d63e5521b2a86fb1668", "parents": [ "ddd04a64a13bde9551ca1174957e055cd2132cff" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 08:55:09 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 08:55:09 2015 +0000" }, "message": "Fix build breakage.\n\nChange-Id: I86959eca5d8f5458ff75c78776b0af9db9c26800\n" }, { "commit": "ddd04a64a13bde9551ca1174957e055cd2132cff", "tree": "cfee62d10e81752ec3af2be1b03dc04a4b176fc9", "parents": [ "90a6adc0f6e55ec02f9443c12e93fea85c1a9393", "915b9d0c13bb5091875d868fbfa551d7b65d7477" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 08:45:10 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 13 08:45:12 2015 +0000" }, "message": "Merge \"Tweak liveness when instructions are used in environments.\"" }, { "commit": "915b9d0c13bb5091875d868fbfa551d7b65d7477", "tree": "63822d7081b0da33ccda2019dd52025f0ecedb35", "parents": [ "bf5565a75876a84c8c2401df597d922a7870a8f2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 11 15:11:19 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 12 17:55:01 2015 +0000" }, "message": "Tweak liveness when instructions are used in environments.\n\nInstructions remain live when debuggable, but only instructions\nwith object types remain live when non-debuggable.\n\nEnable StackVisitor::GetThisObject for optimizing.\n\nChange-Id: Id87b2cbf33a02450059acc9993995782e5f28987\n" }, { "commit": "a2d8ec6876325e89e5d82f5dbeca59f96ced3ec1", "tree": "65bf174b669ff3cd9694dc5a1124fb9f2225ade1", "parents": [ "39d9fe2eb3552a002c53ed41701c6faffe3cd75a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Mar 12 15:25:29 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Mar 12 15:25:29 2015 +0000" }, "message": "Compress the Dex register maps built by the optimizing compiler.\n\n- Replace the current list-based (fixed-size) Dex register\n encoding in stack maps emitted by the optimizing compiler\n with another list-based variable-size Dex register\n encoding compressing short locations on 1 byte (3 bits for\n the location kind, 5 bits for the value); other (large)\n values remain encoded on 5 bytes.\n- In addition, use slot offsets instead of byte offsets to\n encode the location of Dex registers placed in stack\n slots at small offsets, as it enables more values to use\n the short (1-byte wide) encoding instead of the large\n (5-byte wide) one.\n- Rename art::DexRegisterMap::LocationKind as\n art::DexRegisterLocation::Kind, turn it into a\n strongly-typed enum based on a uint8_t, and extend it to\n support new kinds (kInStackLargeOffset and\n kConstantLargeValue).\n- Move art::DexRegisterEntry from\n compiler/optimizing/stack_map_stream.h to\n runtime/stack_map.h and rename it as\n art::DexRegisterLocation.\n- Adjust art::StackMapStream,\n art::CodeGenerator::RecordPcInfo,\n art::CheckReferenceMapVisitor::CheckOptimizedMethod,\n art::StackVisitor::GetVRegFromOptimizedCode, and\n art::StackVisitor::SetVRegFromOptimizedCode.\n- Implement unaligned memory accesses in art::MemoryRegion.\n- Use them to manipulate data in Dex register maps.\n- Adjust oatdump to support the new Dex register encoding.\n- Update compiler/optimizing/stack_map_test.cc.\n\nChange-Id: Icefaa2e2b36b3c80bb1b882fe7ea2f77ba85c505\n" }, { "commit": "5f8741860d465410bfed495dbb5f794590d338da", "tree": "cf295594b5b018e96959ddf474e7c8b7374006b5", "parents": [ "c670efd6ba9dbd1166bfd8c805bb6b2df7d4313a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Mar 04 15:42:45 2015 -0500" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 05 11:08:33 2015 +0000" }, "message": "[optimizing] Use callee-save registers for x86\n\nAdd ESI, EDI, EBP to available registers for non-baseline mode. Ensure\nthat they aren\u0027t used when byte addressible registers are needed.\n\nChange-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "579885a26d761f5ba9550f2a1cd7f0f598c2e1e3", "tree": "58d144157b7a24bbdf7f8892631a15abeefa2c9f", "parents": [ "2eb5168bd9e43b80452eaee5be32c063e124886e" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sun Feb 22 20:51:33 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Mon Mar 02 14:16:56 2015 +0000" }, "message": "Opt Compiler: ARM64: Enable explicit memory barriers over acquire/release\n\nImplement remaining explicit memory barrier code paths and temporarily\nenable the use of explicit memory barriers for testing.\n\nThis CL also enables the use of instruction set features in the ARM64\nbackend. kUseAcquireRelease has been replaced with PreferAcquireRelease(),\nwhich for now is statically set to false (prefer explicit memory barriers).\n\nPlease note that we still prefer acquire-release for the ARM64 Optimizing\nCompiler, but we would like to exercise the explicit memory barrier code\npath too.\n\nChange-Id: I84e047ecd43b6fbefc5b82cf532e3f5c59076458\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "76f82fc75f245101828e2fdbbdec676af1717f0b", "tree": "300049142f90d978526d108ec1c08d28f014110a", "parents": [ "e90ccca801a3b7bda094ee0cc145fc62afd8d718", "442b46a087c389a91a0b51547ac9205058432364" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Feb 20 10:27:12 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Feb 20 10:27:13 2015 +0000" }, "message": "Merge \"Display optimizing compiler\u0027s CodeInfo objects in oatdump.\"" }, { "commit": "d6138ef1ea13d07ae555542f8898b30d89e9ac9a", "tree": "a8ffd5fd966512fd280bc1b3214f4e57a9e1805f", "parents": [ "92095533ac28879ddd8b44b559d700527ca12b8a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 14:48:53 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 19 14:01:18 2015 +0000" }, "message": "Ensure the graph is correctly typed.\n\nWe used to be forgiving because of HIntConstant(0) also being\nused for null. We now create a special HNullConstant for such uses.\n\nAlso, we need to run the dead phi elimination twice during ssa\nbuilding to ensure the correctness.\n\nChange-Id: If479efa3680d3358800aebb1cca692fa2d94f6e5\n" }, { "commit": "442b46a087c389a91a0b51547ac9205058432364", "tree": "4efa4b4da919dd7b9aa18996a5316febcf1c8989", "parents": [ "aa9b7c48069699e2aabedc6c0f62cb131fee0c73" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Feb 18 16:54:21 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 19 12:13:09 2015 +0000" }, "message": "Display optimizing compiler\u0027s CodeInfo objects in oatdump.\n\nA few elements are not displayed yet (stack mask, inline info) though.\n\nChange-Id: I5e51a801c580169abc5d1ef43ad581aadc110754\n" }, { "commit": "dc23d8318db08cb42e20f1d16dbc416798951a8b", "tree": "e7a883bb3263ccb971898df98bc58700604c1d1d", "parents": [ "e5f5953e744060fde3b4489cea4d934d529e3e32" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 16 11:15:43 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 09:53:32 2015 +0000" }, "message": "Avoid generating jmp +0.\n\nWhen a block branches to a non-following block, but blocks\nin-between do branch to it, we can avoid doing the branch.\n\nChange-Id: I9b343f662a4efc718cd4b58168f93162a24e1219\n" }, { "commit": "c0572a451944f78397619dec34a38c36c11e9d2a", "tree": "2cc6f3c6f5ad45b4b85fb62627e797fe7e7734e1", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 14:35:25 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 17:37:57 2015 +0000" }, "message": "Optimize leaf methods.\n\nAvoid suspend checks and stack changes when not needed.\n\nChange-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628\n" }, { "commit": "829280cc90b7a84db42864589b4bafb4c94a79d9", "tree": "8c6f0235011e046bc711ebf795678f6d1a2fedda", "parents": [ "69d69ea40fe64ff2e70daffc365a2fffe5964fcc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 28 10:20:37 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 04 09:11:40 2015 +0000" }, "message": "Finally implement Location::kNoOutputOverlap.\n\nThe [i, i + 1) interval scheme we chose for representing\nlifetime positions is not optimal for doing this optimization.\nIt however doesn\u0027t prevent recognizing a non-split interval\nduring the TryAllocateFreeReg phase, and try to re-use\nits inputs\u0027 registers.\n\nChange-Id: I80a2823b0048d3310becfc5f5fb7b1230dfd8201\n" }, { "commit": "4c204bafbc8d596894f8cb8ec696f5be1c6f12d8", "tree": "3608d188815a8a80e86f98611edcfe3bbaad8b17", "parents": [ "08029544d72bd9bec162956978afcb59204ea97b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 03 15:12:35 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 03 17:13:17 2015 +0000" }, "message": "Use a different block order when not compiling baseline.\n\nUse the linearized order instead, as it puts blocks logically\nnext to each other in a better way. Also, it does not contain\ndead blocks.\n\nChange-Id: Ie65b56041a093c8155e6c1e06351cb36a4053505\n" }, { "commit": "4dee636d21d9ce54386cdfbb824e5eb2a9c1af0d", "tree": "ee8650cc14ec18ce0d7abf089c7d2e0dfc9e079d", "parents": [ "336247fa6deba2948f5ede1df806f48cf67c790a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 18:23:14 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 24 14:34:01 2015 +0000" }, "message": "Support callee-save registers on ARM.\n\nChange-Id: I7c519b7a828c9891b1141a8e51e12d6a8bc84118\n" }, { "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c", "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8", "parents": [ "c698b78a17043d8898deb817098181595fbe734e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 22 13:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 09:20:42 2015 +0000" }, "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n between backends.\n- Remove explicit stack overflow check support: we need to adjust\n them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "9dec5a74014e96d41f84373990b4d4ac83206a88", "tree": "3aacf08f959a3d2558b9dc5985b6a3069506f4c8", "parents": [ "b6b114c02b8bacd3b5d64e646fdaefa03c069c61", "0ada95d8de4b04b5f201b4b7e9c3c2fd2cc321ae" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jan 21 17:36:33 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 21 17:36:33 2015 +0000" }, "message": "Merge \"ART: Replace NULL to nullptr in the optimizing compiler\"" }, { "commit": "0ada95d8de4b04b5f201b4b7e9c3c2fd2cc321ae", "tree": "97231800ac31c9ae1ce6351ca94d1d35dfc8caf8", "parents": [ "03c45ccf104fade857cb01a2b760b08fad5e304a" ], "author": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Thu Dec 04 11:20:20 2014 -0800" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jan 21 17:33:12 2015 +0000" }, "message": "ART: Replace NULL to nullptr in the optimizing compiler\n\nReplace macro NULL to the nullptr variation for C++.\n\nChange-Id: Ib6e48dd4bb3c254343383011b67372622578ca76\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\n" }, { "commit": "6c2dff8ff8e1440fa4d9e1b2ba2a44d036882801", "tree": "da2d48b3d84733ac6b29194cb2f624693a643d48", "parents": [ "22c9285142169691eb2a9e2d4a49751fc7e57c2a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 14:56:54 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 15:19:06 2015 +0000" }, "message": "Revert \"Revert \"Fully support pairs in the register allocator.\"\"\n\nThis reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f.\n\nChange-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5\n" }, { "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea", "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242", "parents": [ "4d2c611bf17ff309abfa152e56c0b98a21ec8787" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 12 18:45:46 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 14:26:35 2015 +0000" }, "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n" }, { "commit": "c399fdc442db82dfda66e6c25518872ab0f1d24f", "tree": "6f0841ad5e8e80b09e34e084ae8eac336bce73a2", "parents": [ "41aedbb684ccef76ff8373f39aba606ce4cb3194" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "message": "Revert \"Fully support pairs in the register allocator.\"\n\nLibcore tests fail.\n\nThis reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194.\n\nChange-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c\n" }, { "commit": "41aedbb684ccef76ff8373f39aba606ce4cb3194", "tree": "94929237a0fe9b24dda7409d9433f07e82af4461", "parents": [ "97c89e4c081dcf4bacbde70b6609e366c9da417e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 10:49:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 11:27:57 2015 +0000" }, "message": "Fully support pairs in the register allocator.\n\nEnabled on ARM for longs and doubles.\n\nChange-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b\n" }, { "commit": "e7fd3e3a8e7f10048b7ea558cc525331c97bbefa", "tree": "a5d1a942460fe34c82f3dce7846d004b90ebd08d", "parents": [ "606a81aab3b9289d37d828375793020b93718c6a", "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Jan 20 12:28:09 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 20 12:28:11 2015 +0000" }, "message": "Merge \"Add implicit null checks for the optimizing compiler\"" }, { "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f", "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f", "parents": [ "12c03ac7575db242a6f35739bb459e8277115da4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Jan 08 17:35:35 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Jan 16 17:27:03 2015 +0000" }, "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n" }, { "commit": "42d1f5f006c8bdbcbf855c53036cd50f9c69753e", "tree": "fb885c3df20797b55f19e5ceccf72dac1c13017b", "parents": [ "36740379b9b1c81b7eb06ea9c9df411d0a9a765e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 09:14:18 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 11:22:08 2015 +0000" }, "message": "Do not use register pair in a parallel move.\n\nThe ParallelMoveResolver does not work with pairs. Instead,\ndecompose the pair into two individual moves.\n\nChange-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f\n" }, { "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd", "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 13 09:20:58 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 15 11:21:37 2015 -0500" }, "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine. This fails for X86,\nwhere a double in an XMM register takes up 8 bytes. Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "11adb76fbc2dc3d8cbb6665945ff5d6733e2a8e6", "tree": "f1a5cb2ce14e1592dd557c28bd1e1ba3c5ea071e", "parents": [ "f3401f7a21c99ebec7355de27ab7bc0840f28726", "12df9ebf72255544b0147c81b1dca6644a29764e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 12 10:46:18 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 12 10:46:18 2015 +0000" }, "message": "Merge \"Move code around in OptimizingCompiler::Compile to reduce stack space.\"" }, { "commit": "12df9ebf72255544b0147c81b1dca6644a29764e", "tree": "93a47865d0c93922cfc036fba1f2490b64549912", "parents": [ "4270e74152d8a7cd979ab5a92fe2a8f84adb8a42" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 09 14:53:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 12 08:49:25 2015 +0000" }, "message": "Move code around in OptimizingCompiler::Compile to reduce stack space.\n\nAlso fix an (intentional) memory leak, by allocating the CodeGenerator\non the heap instead of the arena: they construct an Assembler object\nthat requires destruction.\n\nBUG:18787334\n\nChange-Id: I8cf0667cb70ce5b14d4ac334bd4487a562635f1b\n" }, { "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce", "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518", "parents": [ "893e8881e31180721512c1b9e5ffacb03aad2e45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 07 16:01:24 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 13:57:51 2015 +0000" }, "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n" }, { "commit": "3416601a9e9be81bb7494864287fd3602d18ef13", "tree": "dd228519bfb9733aa7627b9cea81ecb28974a1ab", "parents": [ "8558375377946aabbbda6ab584e13f754590bd89" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Dec 19 17:22:29 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 05 16:25:59 2015 +0000" }, "message": "Look at instruction set features when generating volatiles code\n\nChange-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a\n" }, { "commit": "e21dc3db191df04c100620965bee4617b3b24397", "tree": "2ad762c6afb024bf95e1eced3d584649a4d57d23", "parents": [ "6d1a047b4b3f9707d4ee1cc19e99717ee021ef48" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 08 16:59:43 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 22 10:01:27 2014 -0800" }, "message": "ART: Swap-space in the compiler\n\nIntroduce a swap-space and corresponding allocator to transparently\nswitch native allocations to memory backed by a file.\n\nBug: 18596910\n\n(cherry picked from commit 62746d8d9c4400e4764f162b22bfb1a32be287a9)\n\nChange-Id: I131448f3907115054a592af73db86d2b9257ea33\n" }, { "commit": "6048838af46f41c08c4132ba242040dc49bd5f23", "tree": "5124300bf9a7106d534e126b1926cc9d787ae2dc", "parents": [ "ca747ea9951188dbc6f5217d49aca34aeadcc2a6", "5b4b898ed8725242ee6b7229b94467c3ea3054c8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:46:12 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 18 17:46:13 2014 +0000" }, "message": "Merge \"Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\"" }, { "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8", "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519", "parents": [ "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n" }, { "commit": "e408f8c6ac0ee80543ee1a695695e8917e45eaf3", "tree": "8637636ea603b134b410cf535281fb56249f9d55", "parents": [ "452a8bec86e7795c99f774e81c02f12f1b1e502f", "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 15:49:52 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 18 15:49:53 2014 +0000" }, "message": "Merge \"Don\u0027t block quick callee saved registers for optimizing.\"" }, { "commit": "6004796d6c630696127df2494dcd4f30d1367a34", "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97", "parents": [ "407d77f344cfbdbbfb50531c5f0766bc0892e2fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 00:01:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 14:59:50 2014 +0000" }, "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n" }, { "commit": "e53798a7e3267305f696bf658e418c92e63e0834", "tree": "8979bbed96b107a5a6bbae9285ff4e0c362dad95", "parents": [ "e6c0cdd11097dd72275ac24f1e98217c299d973e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 10:31:54 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 22:52:27 2014 +0000" }, "message": "Inlining support in optimizing.\n\nCurrently only inlines simple things that don\u0027t require an\nenvironment, such as:\n- Returning a constant.\n- Returning a parameter.\n- Returning an arithmetic operation.\n\nChange-Id: Ie844950cb44f69e104774a3cf7a8dea66bc85661\n" }, { "commit": "d2ec87d84057174d4884ee16f652cbcfd31362e9", "tree": "9456c5851f157566380c37895407dfce4749bb4d", "parents": [ "f551efff34c20e2f0cf962c3fc267204d5e7611f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Dec 08 14:24:46 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Dec 08 17:02:11 2014 +0000" }, "message": "[optimizing compiler] Add REM_FLOAT and REM_DOUBLE\n\n- for arm, x86, x86_64 backends\n- reinstated fmod quick entry points for x86. This is a partial revert\nof bd3682eada753de52975ae2b4a712bd87dc139a6 which added inline assembly\nfor floting point rem on x86. Note that Quick still uses the inline\nversion.\n- fix rem tests for longs\n\nChange-Id: I73be19a9f2f2bcf3f718d9ca636e67bdd72b5440\n" }, { "commit": "624279f3c70f9904cbaf428078981b05d3b324c0", "tree": "a81f8d8facfc28cac479a68a1042edc74c36d25b", "parents": [ "9a64a46e8edfa89402598d8650b8ebb337ba3d52" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "message": "Add support for float-to-long in the optimizing compiler.\n\n- Add support for the float-to-long Dex instruction in the\n optimizing compiler.\n- Add a Dex PC field to art::HTypeConversion to allow the\n x86 and ARM code generators to produce runtime calls.\n- Instruct art::CodeGenerator::RecordPcInfo not to record\n PC information for HTypeConversion instructions.\n- Add S0 to the list of ARM FPU parameter registers.\n- Have art::x86_64::X86_64Assembler::cvttss2si work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n float to long HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I954214f0d537187883f83f7a83a1bb2dd8a21fd4\n" }, { "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa", "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Nov 25 20:05:46 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 12:02:58 2014 +0000" }, "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "647b9ed41cdb7cf302fd356627a3ba372419b78c", "tree": "f1ca054aa20ae4c489f208982e7a6cba5d5ee21e", "parents": [ "35ecc8ca8fba713728b8fc60e9e2a275da2028aa" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 12:06:00 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 12:06:00 2014 +0000" }, "message": "Add support for long-to-double in the optimizing compiler.\n\n- Add support for the long-to-double Dex instruction in the\n optimizing compiler.\n- Enable requests of temporary FPU (double) registers during\n code generation.\n- Fix art::x86::X86Assembler::LoadLongConstant and extend\n it to int64_t values.\n- Have art::x86_64::X86_64Assembler::cvtsi2sd work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n long to double HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ie73d9e5e25bd2e15f585c371e8fc2dcb83438ccd\n" }, { "commit": "87d03761f35ad6cbe0bffbf1ec739875a471da6d", "tree": "139fd83737c4f88747214a662e205cd064f1709d", "parents": [ "d79ac38df2a5e56b8929501803183f70053494bf" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 15:17:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 18:11:05 2014 +0000" }, "message": "Fix safepoint bug when computing live registers.\n\nChange-Id: I8f28dd287c0e04223c49dea6a323058c1b210913\n" }, { "commit": "d77ae8a11e6493ac738864eae073ca4909e4d847", "tree": "f6835a2f659cedfc47975bf82f52f05927f8b4b2", "parents": [ "39edb50e16334c8a4ebbfcf0efac38b25074a2dd", "f97f9fbfdf7f2e23c662f21081fadee6af37809d" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Nov 13 11:16:27 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Nov 13 11:16:28 2014 +0000" }, "message": "Merge \"[optimizing compiler] add HTemporary support for long and doubles\"" }, { "commit": "f97f9fbfdf7f2e23c662f21081fadee6af37809d", "tree": "aa5c7b6d42fc1dcd26f4a4f4d75fa488c575091a", "parents": [ "0eaf65edf1b2af63a3eeb77ee1864d84d3154d1e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 11 15:38:19 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 12 18:38:49 2014 +0000" }, "message": "[optimizing compiler] add HTemporary support for long and doubles\n\nChange-Id: I5247ecd71d0193050484b7632c804c9bfd20f924\n" }, { "commit": "f0e3937b87453234d0d7970b8712082062709b8d", "tree": "e552c1173ee90fea1d2ba11cc08878efe65ba0be", "parents": [ "59321e0e10ea09694efecf6154704e2743b9bffd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:50:07 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:55:24 2014 +0000" }, "message": "Do a parallel move in BoundsCheckSlowPath.\n\nThe two locations of the index and length could overlap,\nso we need a parallel move. Also factorize the code for\ndoing a parallel move based on two locations.\n\nChange-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4\n" }, { "commit": "9806199033fc2fb61bfd2260f0156d1b38d56beb", "tree": "14a5cd067fb01ace19fb5e0f7d494bd9e8744845", "parents": [ "255507d9c695aa9c774b882308faa8278382006b", "52839d17c06175e19ca4a093fb878450d1c4310d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 10 10:36:59 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 10 10:37:00 2014 +0000" }, "message": "Merge \"Support invoke-interface in optimizing.\"" }, { "commit": "52839d17c06175e19ca4a093fb878450d1c4310d", "tree": "552ea632ad4d1f688bdfd04b66102e25312bd237", "parents": [ "a453307957afdc3ef0a7988025539ab8919464bc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 17:47:25 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 10 10:33:37 2014 +0000" }, "message": "Support invoke-interface in optimizing.\n\nChange-Id: Ic18d7c3d2810557231caf0571956e0c431f5d384\n" }, { "commit": "f43083d560565aea46c602adb86423daeefe589d", "tree": "6c812e88723c40ee77ab5c9ba38625a10cc9b364", "parents": [ "de87f405a5f8a4ffd57f01d0d667188e8f0ca8cd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 10:48:10 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 07 14:43:19 2014 +0000" }, "message": "Do not update Out after it has a valid location.\n\nSlow paths use LocationSummary to know where to move\nthings around, and they are executed at the end of the\ncode generation.\n\nThis fix is needed for https://android-review.googlesource.com/#/c/113345/.\n\nChange-Id: Id336c6409479b1de6dc839b736a7234d08a7774a\n" }, { "commit": "de58ab2c03ff8112b07ab827c8fa38f670dfc656", "tree": "c872bfbcad1e90845008140bbddcc43e56dc19d2", "parents": [ "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 05 12:46:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 06 16:49:52 2014 +0000" }, "message": "Implement try/catch/throw in optimizing.\n\n- We currently don\u0027t run optimizations in the presence of a try/catch.\n- We therefore implement Quick\u0027s mapping table.\n- Also fix a missing null check on array-length.\n\nChange-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f\n" }, { "commit": "26dcecb0ef620fb225cd5dd39f6e41b07e34c83d", "tree": "5f4d8b1584059dc9570be48030fe4c6aad82457b", "parents": [ "29ce77f654412dbb5fb3d5949da4053952917101", "3c03503d66df3b4440f851ae7d0c4fae5e7872df" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 30 18:20:07 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 30 18:20:07 2014 +0000" }, "message": "Merge \"Follow-up CL after hard float changes.\"" }, { "commit": "19a19cffd197a28ae4c9c3e59eff6352fd392241", "tree": "265b971afd0e33afc8986317aea2f5a6fe817aec", "parents": [ "7c049c1f34220b0dc1a7f68f3b30f388bae7bdb9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 22 16:07:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 29 13:01:48 2014 +0000" }, "message": "Add support for static fields in optimizing compiler.\n\nChange-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9\n" }, { "commit": "3c03503d66df3b4440f851ae7d0c4fae5e7872df", "tree": "6f10a0da8e1a06d4a0a88e015db091a824aec7fb", "parents": [ "d3271e8a48768ed53bfa2515474b57245e7d9a41" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 28 10:46:40 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 28 10:46:40 2014 +0000" }, "message": "Follow-up CL after hard float changes.\n\nAddressing comments from Zheng Xu.\n\nChange-Id: I8c599cdfab03373e82a1b90b711005c490bc6ca0\n" }, { "commit": "1ba0f596e9e4ddd778ab431237d11baa85594eba", "tree": "c1d51616adf4d98aab3ebccf47ad5146635cb87f", "parents": [ "1ef3495abfa2a858b3cc7a1844383c8e7dff0b60" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 27 15:14:55 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 27 17:20:35 2014 +0000" }, "message": "Support hard float on arm in optimizing compiler.\n\nAlso bump oat version, needed after latest hard float switch.\n\nChange-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965\n" }, { "commit": "5319defdf502fc4569316473846b83180ec08035", "tree": "909c6b29f065c79c8368a283946947cbb582d1c7", "parents": [ "37a7188810e865a1ee0a7bdc2d01d62c1f1ea49e" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Oct 23 10:03:10 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 23 13:44:42 2014 +0100" }, "message": "ART: optimizing compiler: initial support for ARM64.\n\nThe ARM64 port uses VIXL for code generation, to which it defers work\nlike label binding and branch resolving, register type coherency\nchecking, and immediate values handling.\n\nChange-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\nSigned-off-by: Alexandre Rames \u003calexandre.rames@arm.com\u003e\n" }, { "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f", "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a", "parents": [ "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 15 18:31:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 16:03:51 2014 +0100" }, "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n" }, { "commit": "92a73aef279be78e3c2b04db1713076183933436", "tree": "e73b214fb7d740588f5d065b2e4ff3eb8c527e34", "parents": [ "5c5efc253507eb43265997c9afcd778f72b6cef4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 16 11:12:52 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 16 15:17:44 2014 +0100" }, "message": "Don\u0027t use assembler classes in code_generator.h.\n\nThe arm64 backend uses its own assembler and does not share\nthe same classes as the other backends. To avoid conflicts\nor unnecessary mappings, just don\u0027t use those classes in the\nshared part of the code generator.\n\nChange-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d\n" }, { "commit": "71175b7f19a4f6cf9cc264feafd820dbafa371fb", "tree": "5370e7c7c9f7d1edf148a00548cb1334d5118f8d", "parents": [ "b76c5495c4879fcfa0866b1490031a3123baf9ee" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 22:13:55 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Oct 10 11:36:03 2014 +0000" }, "message": "Cleanup baseline register allocator.\n\n- Use three arrays for blocking regsters instead of\n one and computing offsets in that array.]\n- Don\u0027t pass blocked_registers_ to methods, just use the field.\n\nChange-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6\n" }, { "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f", "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a", "parents": [ "a3c4d72210de174552f47b2d117b1946f274af1e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 11:47:51 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 14:42:13 2014 +0100" }, "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n" }, { "commit": "7fb49da8ec62e8a10ed9419ade9f32c6b1174687", "tree": "8b1bec67452b84809cecd5645543e1f885ccbd44", "parents": [ "4a1b4679cda2f0d2893b8e3f910c21231849291c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 06 09:12:41 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 20:19:47 2014 +0100" }, "message": "Add support for floats and doubles.\n\n- Follows Quick conventions.\n- Currently only works with baseline register allocator.\n\nChange-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3\n" }, { "commit": "3c04974a90b0e03f4b509010bff49f0b2a3da57f", "tree": "52649104e3e80272c3774793350f4d9f260ae732", "parents": [ "c0d36abb12cdbb9469039c1dc153a586bd984015" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 24 18:10:46 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 25 12:23:40 2014 +0100" }, "message": "Optimize suspend checks in optimizing compiler.\n\n- Remove the ones added during graph build (they were added\n for the baseline code generator).\n- Emit them at loop back edges after phi moves, so that the test\n can directly jump to the loop header.\n- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.\n\nChange-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a\n" }, { "commit": "3bca0df855f0e575c6ee020ed016999fc8f14122", "tree": "15e15c8290ad314c29ca608f51d89d4db68fd9ba", "parents": [ "d41491adb23764f28a80cbb7f2bd7af6491cd892" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Sep 19 11:01:00 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 23 13:57:30 2014 +0100" }, "message": "Support for saving and restoring live registers in a slow path.\n\nAnd use it in suspend check slow paths.\n\nChange-Id: I79caf28f334c145a36180c79a6e2fceae3990c31\n" }, { "commit": "8a16d97fb8f031822b206e65f9109a071da40563", "tree": "9dbbf5feaac15d2e4f54fbfc3c204fcdd6e8317a", "parents": [ "c7f6b86c269727fe031146b9c18652d40916d46f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 11 10:30:02 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 11 10:32:12 2014 +0100" }, "message": "Fix valgrind errors.\n\nFor now just stack allocate the code generator. Will think\nabout cleaning up the root problem later (CodeGenerator being an\narena object).\n\nChange-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7\n" }, { "commit": "3946844c34ad965515f677084b07d663d70ad1b8", "tree": "0d85bfba2ff69c34a2897351d1e50a1464509305", "parents": [ "e2c23739c6395a83b30ece38f8a2e9e1bf7cf3ce" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 02 15:17:15 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Sep 08 12:15:07 2014 +0100" }, "message": "Runtime support for the new stack maps for the opt compiler.\n\nNow most of the methods supported by the compiler can be optimized,\ninstead of using the baseline.\n\nChange-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa\n" }, { "commit": "e3ea83811d47152c00abea24a9b420651a33b496", "tree": "dd3b8018176ada85d51b2f8ca46e515fbf55b50f", "parents": [ "9dcf75c80187504ec88e7ef91d64a6a68279eb9d" ], "author": { "name": "Yevgeny Rouban", "email": "yevgeny.y.rouban@intel.com", "time": "Fri Aug 08 16:29:38 2014 +0700" }, "committer": { "name": "Tong Shen", "email": "endlessroad@google.com", "time": "Fri Aug 15 15:04:12 2014 -0700" }, "message": "ART source line debug info in OAT files\n\nOAT files have source line information enough for ART runtime needs like\njump to/from interpreter and thread suspension. But this information\nis not enough for finer grained source level debugging and low-level\nprofiling (VTune or perf).\n\nThis patch adds to OAT files two additional sections:\n.debug_line - DWARF formatted Elf32 section with detailed source line\n information (mapping from native PC to Java source lines).\n\nIn addition to the debugging symbols added using the dex2oat option\n--include-debug-symbols, the source line information is added to\nthe section .debug_line.\n\nThe source line info can be read by many Elf reading tools like objdump,\nreadelf, dwarfdump, gdb, perf, VTune, ...\n\ngdb can use this debug line information in x86. In 64-bit mode\nthe information can be used if the oat file is mapped in the lower\naddress space (address has higher 32 bits zeroed). Relocation works.\n\nTesting:\n1. art/test/run-test --host --gdb [--64] 001-HelloWorld\n2. in gdb: break Main.java:19\n3. in gdb: break Runtime.java:111\n4. in gdb: run - stops at void java.lang.Runtime.\u003cinit\u003e()\n5. in gdb: backtrace - shows call stack down to main()\n6. in gdb: continue - stops at void Main.main() (only in 32-bit mode)\n7. in gdb: backtrace - shows call stack down to main()\n8. objdump -W \u003coat-file\u003e - addresses are from VMA range of .text\n section reported by objdump -h \u003cfile\u003e\n9. dwarfdump -ka \u003coat-file\u003e - no errors expected\n\nSize of aosp-x86-eng boot.oat increased by 11% from 80.5Mb to 89.2Mb\nwith two sections added .debug_line (7.2Mb) and .rel.debug (1.5Mb).\n\nChange-Id: Ib8828832686e49782a63d5529008ff4814ed9cda\nSigned-off-by: Yevgeny Rouban \u003cyevgeny.y.rouban@intel.com\u003e\n" }, { "commit": "73e80c3ae76fafdb53afe3a85306dcb491fb5b00", "tree": "6c437ad0e24f0ed66251e8f37c13b6e6675db1f2", "parents": [ "16fc9f617e395758eb95b5f2124c79a828186b55" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 22 17:47:56 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 22 17:47:56 2014 +0100" }, "message": "Make unit test tell if a method is a leaf.\n\nThe runtime is not initialized completely in gtests, so we\ncannot run code (such as explicit stack overflow checks) that\nlook at tls values.\n\nChange-Id: I74a4449b01eb203f1b411dda700e9459878d0d55\n" }, { "commit": "f12feb8e0e857f2832545b3f28d31bad5a9d3903", "tree": "0a7320caf995441ea4577875abaf731fc37dd0a9", "parents": [ "ebb6b5c90857f390db5a4f840bbe67b3a59a22d8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 17 18:32:41 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 22 16:07:59 2014 +0100" }, "message": "Stack overflow checks and NPE checks for optimizing.\n\nChange-Id: I59e97448bf29778769b79b51ee4ea43f43493d96\n" }, { "commit": "ab032bc1ff57831106fdac6a91a136293609401f", "tree": "5891daefe635283443a255a811ab6a3f3b8a62cd", "parents": [ "635561b86ac03f5562bdb779baa6db12f31b3cae" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 15 12:55:21 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 15 12:58:29 2014 +0100" }, "message": "Fix a braino in the stack layout.\n\nAlso do some refactoring to have this code be just in CodeGenerator.\n\nChange-Id: I88de109889138af8d60027973c12a64bee813cb7\n" }, { "commit": "e50383288a75244255d3ecedcc79ffe9caf774cb", "tree": "8858489463a57c7b50f7db4d972abec21302b7a7", "parents": [ "cf90ba7ebe00346651f3b7ce1e5b1f785f7caabd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 04 09:41:32 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 14 10:06:11 2014 +0100" }, "message": "Support fields in optimizing compiler.\n\n- Required support for temporaries, to be only used by baseline compiler.\n- Also fixed a few invalid assumptions around locations and instructions\n that don\u0027t need materialization. These instructions should not have an Out.\n\nChange-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62\n" }, { "commit": "9cf35523764d829ae0470dae2d5dd99be469c841", "tree": "889459a8ecf8fdf801ea46dd58d15268dfb25af8", "parents": [ "b08f63c21de64f8b74003e3638e100471bd099f3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 09 18:40:10 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jun 13 09:49:30 2014 +0100" }, "message": "Add x86_64 support to the optimizing compiler.\n\nChange-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be\n" }, { "commit": "86dbb9a12119273039ce272b41c809fa548b37b6", "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5", "parents": [ "c936622863a50bdda9b10062515dfc02a8c8b652" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 04 11:12:39 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 12 10:02:06 2014 +0100" }, "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n inputs/output to be at a specific location, and the allocator\n needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n" }, { "commit": "f635e63318447ca04731b265a86a573c9ed1737c", "tree": "47cab84a6ac47d8a4f5f281e3eabdf1780f220d0", "parents": [ "d115735fe5523ff72319f0968f773683323c7f79" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 14 09:43:38 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 14 14:26:11 2014 +0100" }, "message": "Add a compilation tracing mechanism to the new compiler.\n\nCode mostly imported from: https://android-review.googlesource.com/#/c/81653/.\n\nChange-Id: I150fe942be0fb270e03fabb19032180f7a065d13\n" }, { "commit": "804d09372cc3d80d537da1489da4a45e0e19aa5d", "tree": "b226350fdf3dc0c55a11e1615010c8475f167f90", "parents": [ "0095e0b8380a8802f40a21928800b9df6e11f1d7" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 02 08:46:00 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 07 10:32:11 2014 +0100" }, "message": "Build live-in, live-out and kill sets for each block.\n\nThis information will be used when computing live ranges of\ninstructions.\n\nChange-Id: I345ee833c1ccb4a8e725c7976453f6d58d350d74\n" }, { "commit": "f529d776ca9f48b115714f6c79677755ecc37d24", "tree": "707d3f8478a0500dc6e32cfa61d5ebcc6acca596", "parents": [ "608168b380b741e2c7e1a2b0b568c0738986166b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 02 11:03:30 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 02 11:06:50 2014 +0100" }, "message": "Make all registers available when allocating an output register.\n\nOn ARM we currently only have two register pairs available, so we\nneed to use one already used for an input.\n\nChange-Id: I5411862310009a41e50ddab3549d3a9e9052266a\n" }, { "commit": "a7aca370a7d62ca04a1e24423d90e8020d6f1a58", "tree": "65d501b0f9711abddbea1a9d06623baafa4ae2b3", "parents": [ "5dee5df89aa2cefef6c886d5b9b642cc6f1c595b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 28 17:47:12 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Apr 29 10:55:30 2014 +0100" }, "message": "Setup policies for register allocation.\n\nChange-Id: I857e77530fca3e2fb872fc142a916af1b48400dc\n" }, { "commit": "c32e770f21540e4e9eda6dc7f770e745d33f1b9f", "tree": "56a76d7399bf749a4500fb60483e0dc075a24ee7", "parents": [ "618a87009202dc959c935ed8f237ae32bdec57d0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 24 12:43:16 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 28 16:21:40 2014 +0100" }, "message": "Add a Transform to SSA phase to the optimizing compiler.\n\nChange-Id: Ia9700756a0396d797a00b529896487d52c989329\n" }, { "commit": "b55f835d66a61e5da6fc1895ba5a0482868c9552", "tree": "44659a826aeadcf2bf176c2e8d31108ba64c88eb", "parents": [ "427ca38b0a6c6fd7dc0dbb380619e2b91b56cf1c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 07 15:26:35 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Apr 08 08:43:50 2014 +0100" }, "message": "Test control flow instruction with optimizing compiler.\n\nAdd support for basic instructions to implement these tests.\n\nChange-Id: I3870bf9301599043b3511522bb49dc6364c9b4c0\n" }, { "commit": "f583e5976e1de9aa206fb8de4f91000180685066", "tree": "0e7c2d30af5c713012f0a33e6dd7d8f71e7fc85d", "parents": [ "7ab4e5c5288e04b7beb6d8ddfd5e8bf878002732" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 07 13:20:42 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 07 15:24:23 2014 +0100" }, "message": "Add support for taking parameters in optimizing compiler.\n\n- Fix stack layout to mimic Quick\u0027s.\n- Implement some sub operations.\n\nChange-Id: I8cf75a4d29b662381a64f02c0bc61d859482fc4e\n" }, { "commit": "707c809f661554713edfacf338365adca8dfd3a3", "tree": "21aaa53a3beb7d73fb2af9ab55bee7a538254fcb", "parents": [ "7efad5d3a806a15166109837439f2e149031feef" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Apr 04 10:50:14 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Apr 04 10:50:14 2014 +0100" }, "message": "Use target-specific word instead of runtime word.\n\nChange-Id: Ia11dc3cc520a1a5c7bd017013e5699af9570ce91\n" }, { "commit": "a7b2826fa469c626ff2c3ff26fd848c28bccc092", "tree": "f53277bb95088b5b650cf982d0da666f1204517a", "parents": [ "5a4139fd33547d09c94d9650157e3a4e4c9eede4", "4a34a428c6a2588e0857ef6baf88f1b73ce65958" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 03 16:49:25 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 03 16:49:25 2014 +0000" }, "message": "Merge \"Support passing arguments to invoke-static* instructions.\"" }, { "commit": "4a34a428c6a2588e0857ef6baf88f1b73ce65958", "tree": "a9f025c17752a175c4e6a203c01e935cb438efb1", "parents": [ "8549cf9d83688f7decbbea2a8de761ce29e95f3c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 03 10:38:37 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Apr 03 17:09:22 2014 +0100" }, "message": "Support passing arguments to invoke-static* instructions.\n\n- Stop using the frame pointer for accessing locals.\n- Stop emulating a stack when doing code generation. Instead,\n rely on dex register model, where instructions only reference\n registers.\n\nChange-Id: Id51bd7d33ac430cb87a53c9f4b0c864eeb1006f9\n" }, { "commit": "6a58cb16d803c9a7b3a75ccac8be19dd9d4e520d", "tree": "c142777f40178fd9b9090cd7316be694befb3f21", "parents": [ "8549cf9d83688f7decbbea2a8de761ce29e95f3c" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Wed Apr 02 17:27:59 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Thu Apr 03 13:06:55 2014 +0700" }, "message": "art: Handle x86_64 architecture equal to x86\n\nThis patch forces FE/ME to treat x86_64 as x86 exactly.\nThe x86_64 logic will be revised later when assembly will be ready.\n\nChange-Id: I4a92477a6eeaa9a11fd710d35c602d8d6f88cbb6\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" } ], "next": "8ccc3f5d06fd217cdaabd37e743adab2031d3720" }