)]}'
{
  "log": [
    {
      "commit": "99ad7230ccaace93bf323dea9790f35fe991a4a2",
      "tree": "095705c674703953bf4c50f6a30a105420b770b5",
      "parents": [
        "a9e3d2ccfdbf7f4c7b1508bcb2b774037399b1d4"
      ],
      "author": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Tue Feb 25 17:41:08 2014 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Mar 26 16:20:09 2014 -0700"
      },
      "message": "Relaxed memory barriers for x86\n\nX86 provides stronger memory guarantees and thus the memory barriers can be\noptimized. This patch ensures that all memory barriers for x86 are treated\nas scheduling barriers. And in cases where a barrier is needed (StoreLoad case),\nan mfence is used.\n\nChange-Id: I13d02bf3f152083ba9f358052aedb583b0d48640\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n"
    },
    {
      "commit": "7d180cb41d3104af7c85a5b808bb9f57c264c2a6",
      "tree": "5834b83ef7395a9ee9c5ceb8f1c4b4f2ae052c91",
      "parents": [
        "027f7fa539514d2a50b448de1de39ac307087483"
      ],
      "author": {
        "name": "Dmitriy Ivanov",
        "email": "dimitry@google.com",
        "time": "Tue Mar 25 10:31:04 2014 -0700"
      },
      "committer": {
        "name": "Dmitriy Ivanov",
        "email": "dimitry@google.com",
        "time": "Tue Mar 25 10:31:52 2014 -0700"
      },
      "message": "Fix imm5 and shift_type detection\n\nBug: 13628315\nChange-Id: I8ff044cc18721b7ea50c75c796a2fb63a1e189f9\n"
    },
    {
      "commit": "38e12034f1ef2b32e98b6e49cb36b7cc37a7f1be",
      "tree": "9a879d4034bce742c8b5ef0680c2da2d8da5139d",
      "parents": [
        "fb5b21d1d598b6b42e5d5ca1dac4a040832558fb"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Mar 14 14:06:14 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Mar 14 14:16:04 2014 -0700"
      },
      "message": "x86-64 disassembler support.\n\nChange-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0\n"
    },
    {
      "commit": "c2687ef3ef95c9888af885ec3fa1516b218906ff",
      "tree": "79604605fc47c44f5bc6d65f3f32b39e71ea2e61",
      "parents": [
        "b9d50a9829b795932eac4cc50a99b4ce80b0ecb4"
      ],
      "author": {
        "name": "Brian Carlstrom",
        "email": "bdc@google.com",
        "time": "Thu Mar 13 15:12:11 2014 -0700"
      },
      "committer": {
        "name": "Brian Carlstrom",
        "email": "bdc@google.com",
        "time": "Thu Mar 13 15:12:11 2014 -0700"
      },
      "message": "Avoid bus error from reading unaligned 64-bit literal\n\nChange-Id: I5932f130e6a8d31e09ef615e8544ff0e1073ede9\n"
    },
    {
      "commit": "2b9aa967b22f6114f25a8f7c72c58dc476dc35a2",
      "tree": "6e2061ba046fd6e997564e82c25d571b5751b3fb",
      "parents": [
        "3dfc5c168506b89e345c977355a4eabebfede72a",
        "e6622be6c353c7178f34adf814c58370a51c5ed7"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Mon Mar 10 18:48:31 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Mar 10 18:48:31 2014 +0000"
      },
      "message": "Merge \"AArch64: Add ARM64 Disassembler\""
    },
    {
      "commit": "e6622be6c353c7178f34adf814c58370a51c5ed7",
      "tree": "2b6ed31cd1d2ed27998538ff0da327d47e930113",
      "parents": [
        "e2d080ca23ee6146bc28c2caa6c856bd5af41043"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Feb 27 15:36:47 2014 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Mon Mar 10 18:27:01 2014 +0000"
      },
      "message": "AArch64: Add ARM64 Disassembler\n\nThis patch adds disassembler support for ARM64 based on VIXL.\n\nChange-Id: Ic7f5e197350809632145d932dbae8f6c16aebd13\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "e19649a91702234f9aa9941d76da447a1e0dcc2a",
      "tree": "76e8f8c99aaf462f2cb52a049a96819fc9dc7c95",
      "parents": [
        "d57abe5f75e2c82052d7396d6ec6eafc7f3af58a"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Thu Feb 27 13:30:55 2014 +0000"
      },
      "committer": {
        "name": "Stuart Monteith",
        "email": "srdmarm@gmail.com",
        "time": "Mon Mar 10 14:11:54 2014 +0000"
      },
      "message": "ARM: Remove duplicated instructions; add vcvt, vmla, vmls disassembler.\n\nRemove kThumb2VcvtID in the assembler which was duplicated.\nAdd vcvt, vmla, vmls in the disassembler.\n\nChange-Id: I14cc39375c922c9917274d8dcfcb515e888fdf26\n"
    },
    {
      "commit": "b48b9eb6d181a1f52e2e605cf26a21505f1d46ed",
      "tree": "117d99c16f201b2f14adfe0922e56b9ff433c133",
      "parents": [
        "3c506f9877b4a106d93169b6bb5610b24a84d61c"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Feb 28 16:20:21 2014 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Feb 28 19:03:57 2014 -0800"
      },
      "message": "Fix clang to compile and run host tests.\n\nDon\u0027t use the computed goto interpreter with clang 3.4 as it causes compilation\nto hang.\nAvoid inclusion of LLVM_(HOST|DEVICE)_BUILD_MK except for with portable as it\nsets clang incompatible cflags.\nMost fixes are self-evident, for the quick dex file method inliner the enums\nwere being used with ostreams, so fix the enums and operator out python script\nto allow this.\nNote this change effects portable but this is untestable as portable was broken\nby ELF file and mc linker changes.\n\nChange-Id: Ia54348f6b1bd3f76d3b71c6e8c5f97626386b903\n"
    },
    {
      "commit": "4028a6c83a339036864999fdfd2855b012a9f1a7",
      "tree": "c86f355cb39adc7a14469f0a4e5727623fbda443",
      "parents": [
        "0b2b3dbaa3db62c0af0d2f23f6aa1c539afe7443"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Feb 19 20:06:20 2014 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Feb 20 15:46:42 2014 -0800"
      },
      "message": "Inline x86 String.indexOf\n\nTake advantage of the presence of a constant search char or start index\nto tune the generated code.\n\nChange-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "dc781a13ddb4dabf646bb45d0c53b65cab948e5b",
      "tree": "b74e4a579747ce12297b5a66f04669f42dfffa6a",
      "parents": [
        "89925e948c49616689eb4959aaf0e4ff1de18161"
      ],
      "author": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Tue Feb 04 16:22:03 2014 -0800"
      },
      "committer": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Tue Feb 18 17:22:15 2014 -0800"
      },
      "message": "art: convert makefiles to support multilib build\n\nConvert makefiles to allow for building two architectures at the\nsame time.  More changes may be necessary to get the tests to\nbuild.\n\nChange-Id: I02ba11706b7e5b5592d76e43c167bcbf0e665b93\n"
    },
    {
      "commit": "614c2b4e219631e8c190fd9fd5d4d9cd343434e1",
      "tree": "8236046426615c78eb6b2f6c2ca29b63d5665d97",
      "parents": [
        "6b3697fec487b355d107b693c965919bf5fff906"
      ],
      "author": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Tue Jan 28 17:05:21 2014 -0800"
      },
      "committer": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Tue Feb 11 18:10:33 2014 -0800"
      },
      "message": "Support to generate inline long to FP bytecodes for x86\n\nlong-to-float and long-to-double are now generated inline instead of calling\na helper routine. The conversion is done by using x87.\n\nChange-Id: I196e526afec1be212898baceca8527549c3655b6\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n"
    },
    {
      "commit": "ef7d42fca18c16fbaf103822ad16f23246e2905d",
      "tree": "c67eea52a349c2ea7f2c3bdda8e73933c05531a8",
      "parents": [
        "822115a225185d2896607eb08d70ce5c7099adef"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Mon Jan 06 12:55:46 2014 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Feb 06 23:20:27 2014 -0800"
      },
      "message": "Object model changes to support 64bit.\n\nModify mirror objects so that references between them use an ObjectReference\nvalue type rather than an Object* so that functionality to compress larger\nreferences can be captured in the ObjectRefererence implementation.\nObjectReferences are 32bit and all other aspects of object layout remain as\nthey are currently.\n\nExpand fields in objects holding pointers so they can hold 64bit pointers. Its\nexpected the size of these will come down by improving where we hold compiler\nmeta-data.\nStub out x86_64 architecture specific runtime implementation.\nModify OutputStream so that reads and writes are of unsigned quantities.\nMake the use of portable or quick code more explicit.\nTemplatize AtomicInteger to support more than just int32_t as a type.\nAdd missing, and fix issues relating to, missing annotalysis information on the\nmutator lock.\nRefactor and share implementations for array copy between System and uses\nelsewhere in the runtime.\nFix numerous 64bit build issues.\n\nChange-Id: I1a5694c251a42c9eff71084dfdd4b51fff716822\n"
    },
    {
      "commit": "2c498d1f28e62e81fbdb477ff93ca7454e7493d7",
      "tree": "94654433a4dae83ab75d432304dcc0358aefeb1c",
      "parents": [
        "1dcff62155e8477eb114c8a86eb1beb0797ffc11"
      ],
      "author": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Wed Jan 29 16:02:57 2014 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Feb 05 22:42:21 2014 -0800"
      },
      "message": "Specializing x86 range argument copying\n\nThe ARM implementation of range argument copying was specialized in some cases.\nFor all other architectures, it would fall back to generating memcpy. This patch\nupdates the x86 implementation so it does not call memcpy and instead generates\nloads and stores, favoring movement of 128-bit chunks.\n\nChange-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n"
    },
    {
      "commit": "7ea5dafc81b2bba7cabad26130bb75dc8f709803",
      "tree": "dfd021549d31697d4c142699e38fb8fa00e64c58",
      "parents": [
        "6e65720d99bd3387b72d528a46291f1ed8184ede",
        "4708dcd68eebf1173aef1097dad8ab13466059aa"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Jan 28 00:29:31 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Jan 28 00:29:31 2014 +0000"
      },
      "message": "Merge \"Improve x86 long multiply and shifts\""
    },
    {
      "commit": "d3266bcc340d653e178e3ab9d74512c8db122eee",
      "tree": "1a3cf8b8e828994c57c533157bc1f84e50c24a14",
      "parents": [
        "26a302b2bb07d754b958a4013116946fbbd78c62"
      ],
      "author": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Fri Jan 24 12:55:31 2014 -0800"
      },
      "committer": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Fri Jan 24 14:38:53 2014 -0800"
      },
      "message": "Reduce x86 sequence for GP pair to XMM\n\nAdded support for punpckldq which is useful for interleaving\n32-bit values from two xmm registers.\n\nThis new instruction is now used for transfers from GP pairs\nto XMM in order to reduce path length.\n\nChange-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n"
    },
    {
      "commit": "4708dcd68eebf1173aef1097dad8ab13466059aa",
      "tree": "92614e1fe36cccda1d2fd7c662c43482ec8bcc85",
      "parents": [
        "a278ac31a1beeebd093ec64026d27a02fdc28807"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Jan 22 09:05:18 2014 -0800"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Jan 24 11:49:06 2014 -0800"
      },
      "message": "Improve x86 long multiply and shifts\n\nGenerate inline code for long shifts by constants and do long\nmultiplication inline. Convert multiplication by a constant to a\nshift when we can. Fix some x86 assembler problems and add the new\ninstructions that were needed (64 bit shifts).\n\nChange-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "2bf31e67694da24a19fc1f328285cebb1a4b9964",
      "tree": "e24b7ec3569ea26e91f1a10179b7d1912f594d7e",
      "parents": [
        "3f5b42f1d31c877abca2571a51dd0a5055a9b94c"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Jan 23 12:13:40 2014 -0800"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Jan 24 10:01:41 2014 -0800"
      },
      "message": "Improve x86 long divide\n\nImplement inline division for literal and variable divisors.  Use the\ngeneral case for dividing by a literal by using a double length multiply\nby the appropriate constant with fixups.  This is the Hacker\u0027s Delight\nalgorithm.\n\nChange-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "0adc680c388913a63666797e907f87c4c6b0b4ea",
      "tree": "845853afb3b58f7288f02ef8abd43d0026fc6782",
      "parents": [
        "805ec1c7016ed46a27a0054397fcec8ff4bbbe92",
        "bd288c2c1206bc99fafebfb9120a83f13cf9723b"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Jan 08 22:56:31 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Jan 08 22:56:31 2014 +0000"
      },
      "message": "Merge \"Add conditional move support to x86 and allow GenMinMax to use it\""
    },
    {
      "commit": "ef6a776af2b4b8607d5f91add0ed0e8497100e31",
      "tree": "dbff2e90823f07915efab7abc5a3e31182b2f2ae",
      "parents": [
        "8ec304764fdc97ee300175ebed16622eddfb6f1f"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Dec 19 17:58:05 2013 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Jan 08 14:09:53 2014 -0800"
      },
      "message": "Inline codegen for long-to-double on ARM.\n\nChange-Id: I4fc443c1b942a2231d680fc2c7a1530c86104584\n"
    },
    {
      "commit": "bd288c2c1206bc99fafebfb9120a83f13cf9723b",
      "tree": "a9f154c4338b888de313517e95ae6a7ee22e7f1f",
      "parents": [
        "51f46ad5edd888b58d706569342c1a0f51e6ae15"
      ],
      "author": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Fri Dec 20 17:27:23 2013 -0800"
      },
      "committer": {
        "name": "Razvan A Lupusoru",
        "email": "razvan.a.lupusoru@intel.com",
        "time": "Wed Jan 08 11:28:46 2014 -0800"
      },
      "message": "Add conditional move support to x86 and allow GenMinMax to use it\n\nX86 supports conditional moves which is useful for reducing branchiness.\nThis patch adds support to the x86 backend to generate conditional reg\nto reg operations. Both encoder and decoder support was added for cmov.\n\nThe x86 version of GenMinMax used for generating inlined version Math.min/max\nhas been updated to make use of the conditional move support.\n\nChange-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n"
    },
    {
      "commit": "b122a4bbed34ab22b4c1541ee25e5cf22f12a926",
      "tree": "624f16271f4481a8fd5aa2f607385f490dc7b3ae",
      "parents": [
        "e40687d053b89c495b6fbeb7a766b01c9c7e039c"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Nov 19 18:00:50 2013 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Dec 20 08:01:57 2013 -0800"
      },
      "message": "Tidy up memory barriers.\n\nChange-Id: I937ea93e6df1835ecfe2d4bb7d84c24fe7fc097b\n"
    },
    {
      "commit": "d19b55a05b52b7f7da9f894eba63ed03e2a62283",
      "tree": "06c50a4d0121eae129e8dc920166e2e3953e3468",
      "parents": [
        "f723f0cdc693f81581c0781fa472b1c85a8b42d6"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Dec 12 09:55:34 2013 -0800"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Dec 12 13:05:18 2013 -0800"
      },
      "message": "Disassemble more x86 instructions\n\nBy using oatdump on the core.oat, I found a couple more instructions\nthat didn\u0027t disassemble properly.  These included another form of imul\nand some FP instructions used by the JNI code.\n\nNow the only unknown opcodes I could find seem to be literal data at\nthe end of the method.\n\nChange-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "f723f0cdc693f81581c0781fa472b1c85a8b42d6",
      "tree": "5d7b37796a71156d805340d88c0bd7f0078bd153",
      "parents": [
        "8755359a35a4aa915fe3753633015263c7e97b74"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Dec 11 17:50:58 2013 -0800"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Dec 11 17:50:58 2013 -0800"
      },
      "message": "Add missing x86 imul opcode to disassembler\n\nWhen playing with ART, I noticed that an integer multiply didn\u0027t\ndisassemble properly.  This patch adds the instruction.\n\nChange-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "70b797d998f2a28e39f7d6ffc8a07c9cbc47da14",
      "tree": "e5607068be133899ff9111e33327e0c2aa525cd1",
      "parents": [
        "057c74a3a2d50d1247d4e6472763ca6f59060762"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 03 15:25:24 2013 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 03 18:32:29 2013 +0000"
      },
      "message": "Unsafe.compareAndSwapLong() intrinsic for x86.\n\nChange-Id: Idbc5371a62dfdd84485a657d4548990519200205\n"
    },
    {
      "commit": "3e5af82ae1a2cd69b7b045ac008ac3b394d17f41",
      "tree": "de4cb3a63320db48bc942de670552167e1d7bea3",
      "parents": [
        "5da3778746375b73e7e77c5f1371f29684674776"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 21 15:01:20 2013 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Nov 26 17:50:59 2013 +0000"
      },
      "message": "Intrinsic Unsafe.CompareAndSwapLong() for ARM.\n\n(cherry picked from cb53fcd79b1a5ce608208ec454b5c19f64aaba37)\n\nChange-Id: Iadd3cc8b4ed390670463b80f8efd579ce6ece226\n"
    },
    {
      "commit": "2247984899247b1402408d39731ff64048f0e274",
      "tree": "da948b429b97506a1dc165debb4f8b5a4c0a585d",
      "parents": [
        "ba9ece9c58de90b39c39b29dbdaee54b1654c066"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Nov 19 17:04:50 2013 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Nov 19 17:07:08 2013 +0000"
      },
      "message": "Clean up kOpCmp on ARM.\n\nkThumb2CmnRI8M is now used.\n\nChange-Id: I300299258ed99d86c300dee45c904c360dd44638\n"
    },
    {
      "commit": "ad435ebd9d011eef66ef77e96b065024220c10ad",
      "tree": "c6b4fcbe0493ffaafbcc4daf4e38cb915813fbc0",
      "parents": [
        "500793f33b8af8bc7ccf5595a66b4b13bce766bc"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 15 15:21:25 2013 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 15 15:21:25 2013 +0000"
      },
      "message": "Fix Thumb2 ldrd/strd disassembly.\n\nChange-Id: Ie75aeab5b970640e90e567621ac45ce1a3a7c377\n"
    },
    {
      "commit": "dd577a3c9849105429fe7afb3559773d59aaafb6",
      "tree": "8add7895dce203bc984f91ef7df21ff4324b61ea",
      "parents": [
        "e21a40730ae51d8dfd0633dc021765a7839f70dc"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 07 19:25:24 2013 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 07 22:35:44 2013 +0000"
      },
      "message": "Disassemble Thumb2 vstm/vldm/vstr/vldr/vpush/vpop/vmov/vmrs.\n\nNot all versions of vmov are disassembled.\n\nChange-Id: I876199f7536d2a9429106deab821016fe8972469\n"
    },
    {
      "commit": "7020278bce98a0735dc6abcbd33bdf1ed2634f1d",
      "tree": "533cf9a77046a49525d916043a58949e59319f2d",
      "parents": [
        "67f128a4023bbbe55827dd2c11ed0538ee387233"
      ],
      "author": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Tue Oct 22 17:52:19 2013 -0700"
      },
      "committer": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Tue Nov 05 16:48:53 2013 -0800"
      },
      "message": "Support hardware divide instruction\n\nBug: 11299025\n\nUses sdiv for division and a combo of sdiv, mul and sub for modulus.\nOnly does this on processors that are capable of the sdiv instruction, as determined\nby the build system.\n\nAlso provides a command line arg --instruction-set-features\u003d to allow cross compilation.\nMakefile adds the --instruction-set-features\u003d arg to build-time dex2oat runs and defaults\nit to something obtained from the target architecture.\n\nProvides a GetInstructionSetFeatures() function on CompilerDriver that can be\nqueried for various features.  The only feature supported right now is hasDivideInstruction().\n\nAlso adds a few more instructions to the ARM disassembler\n\nb/11535253 is an addition to this CL to be done later.\n\nChange-Id: Ia8aaf801fd94bc71e476902749cf20f74eba9f68\n"
    },
    {
      "commit": "1f6754dc482f0175acb05275a82b9950c3d268ee",
      "tree": "2d32754a38701eafc4a9ae2ce8a6570e16b486b5",
      "parents": [
        "a8b4caf7526b6b66a8ae0826bd52c39c66e3c714"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 28 20:27:17 2013 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 28 20:27:17 2013 +0000"
      },
      "message": "Fix whitespace-sensitive build.\n\nChange-Id: I82c6c49e253275543831dbaf288cb63d759ea20a\n"
    },
    {
      "commit": "a8b4caf7526b6b66a8ae0826bd52c39c66e3c714",
      "tree": "3393e7eeea6ae173caa59edd18b7c2c4c014650a",
      "parents": [
        "17088bbded68e35da8050a40206dfd3cbba9e6d2"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 24 15:08:57 2013 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 28 18:30:48 2013 +0000"
      },
      "message": "Add byte swap instructions for ARM and x86.\n\nChange-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d\n"
    },
    {
      "commit": "a9650dd5e7195aec987a69a6ebbdaf33f73a6b00",
      "tree": "bf7bf34e4ce1791c24b3d7f9cc588d8d37bec160",
      "parents": [
        "9f69b62e6b009b29e6420c49e7444e91466a6a33"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Oct 04 08:23:32 2013 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Oct 04 08:23:32 2013 -0700"
      },
      "message": "Implement thumb expansion of immediates.\n\nChange-Id: Ie50c17f82cbf97a16b58350b378914030cc0499f\n"
    },
    {
      "commit": "02ed4c04468ca5f5540c5b704ac3e2f30eb9e8f4",
      "tree": "fd568452f4ae81868087e9a5f6c04a9051d0ef83",
      "parents": [
        "28c2300d9a85f4e7288fb5d94280332f923b4df3"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Sep 06 13:10:04 2013 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Mon Sep 09 08:33:36 2013 -0700"
      },
      "message": "Move disassembler out of runtime.\n\nBug: 9877500.\nChange-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29\n"
    }
  ]
}