)]}'
{
  "log": [
    {
      "commit": "2a3471fc83383bfe3e060799482e372420ba6150",
      "tree": "7b7764521a0b67392e023f1efacc0dbae64fe675",
      "parents": [
        "89ae0f42e38a2f985ac404830f2a05fecf9547e2"
      ],
      "author": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Mon May 08 18:36:40 2017 +0100"
      },
      "committer": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Fri Jun 30 16:32:54 2017 +0100"
      },
      "message": "Disambiguate memory accesses in instruction scheduling\n\nBased on aliasing information from heap location collector,\ninstruction scheduling can further eliminate side-effect\ndependencies between memory accesses to different locations,\nand perform better scheduling on memory loads and stores.\n\nPerformance improvements of this CL, measured on Cortex-A53:\n| benchmarks     | ARM64 backend | ARM backend |\n|----------------+---------------|-------------|\n| algorithm      |         0.1 % |       0.1 % |\n| benchmarksgame |         0.5 % |       1.3 % |\n| caffeinemark   |         0.0 % |       0.0 % |\n| math           |         5.1 % |       5.0 % |\n| stanford       |         1.1 % |       0.6 % |\n| testsimd       |         0.4 % |       0.1 % |\n\nCompilation time impact is negligible, because this\nheap location load store analysis is only performed\non loop basic blocks that get instruction scheduled.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: 706-checker-scheduler\n\nChange-Id: I43d7003c09bfab9d3a1814715df666aea9a7360b\n"
    },
    {
      "commit": "757b26c2442ae792039bc50153bef91145f3c7b4",
      "tree": "4d8798405364a51bb7dd6f2c365bfdffca26f791",
      "parents": [
        "fe9a4f061841a3c597aac6817a47c799c54fcad7"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 29 16:11:41 2017 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 29 16:13:06 2017 +0100"
      },
      "message": "Add CHECKs to help diagnose a crash seen internally.\n\nbug: 62855731\nTest: test.py\nChange-Id: I7904257174ce11a138ca769172dbc2e33e10ef76\n"
    },
    {
      "commit": "7d157fcaaae137cc98dbfb872aa1bdc0105a898f",
      "tree": "2b7d8affda23908e5bfbfaad446079db2ef1ee09",
      "parents": [
        "58d7ddc678e5bcd2364c24c4bdc8a3cfbcfc5358"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed May 10 16:29:23 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu May 11 11:14:54 2017 +0100"
      },
      "message": "Clean up some uses of \"auto\".\n\nMake actual types more explicit, either by replacing \"auto\"\nwith actual type or by assigning std::pair\u003c\u003e elements of\nan \"auto\" variable to typed variables. Avoid binding const\nreferences to temporaries. Avoid copying a container.\n\nTest: m test-art-host-gtest\nChange-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603\n"
    },
    {
      "commit": "f7caf682c6b4769b2a3dd2f2241532b98709c1a3",
      "tree": "88ecbd1fa756e722fd79e2b696620cd61ac3305f",
      "parents": [
        "91f956c925f015b8cd355e8ec2a697a4ba69f7ab"
      ],
      "author": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Wed Mar 01 16:07:02 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 08 08:33:07 2017 +0000"
      },
      "message": "Instruction scheduling for ARM.\n\nPerformance improvements on various benchmarks with this CL:\n\nbenchmarks     improvements\n---------------------------\nalgorithm                1%\nbenchmarksgame           2%\ncaffeinemark             2%\nmath                     3%\nstanford                 4%\n\nTested on ARM Cortex-A53 CPU.\n\nThe code size impact is negligible.\n\nTest: m test-art-host\nTest: m test-art-target\nChange-Id: I314c90c09ce27e3d224fc686ef73c7d94a6b5a2c\n"
    },
    {
      "commit": "22aa54bf8469689c7c6c33f15ff4df2ffba8fa15",
      "tree": "14204d55784dce3ffdd2641382a763afee85ced0",
      "parents": [
        "8116003cc9dd1e74fac1682eec547b8bb0afb061"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Tue Oct 18 09:32:29 2016 +0100"
      },
      "committer": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Wed Jan 25 14:25:20 2017 +0000"
      },
      "message": "AArch64: Add HInstruction scheduling support.\n\nThis commit adds a new `HInstructionScheduling` pass that performs\nbasic scheduling on the `HGraph`.\n\nCurrently, scheduling is performed at the block level, so no\n`HInstruction` ever leaves its block in this pass.\n\nThe scheduling process iterates through blocks in the graph. For\nblocks that we can and want to schedule:\n1) Build a dependency graph for instructions. It includes data\n   dependencies (inputs/uses), but also environment dependencies and\n   side-effect dependencies.\n2) Schedule the dependency graph. This is a topological sort of the\n   dependency graph, using heuristics to decide what node to schedule\n   first when there are multiple candidates. Currently the heuristics\n   only consider instruction latencies and schedule first the\n   instructions that are on the critical path.\n\nTest: m test-art-host\nTest: m test-art-target\n\nChange-Id: Iec103177d4f059666d7c9626e5770531fbc5ccdc\n"
    }
  ]
}