)]}'
{
  "log": [
    {
      "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0",
      "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788",
      "parents": [
        "7113885fcd983b33ee1e350865d21517d6297843"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 27 16:50:47 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu May 11 10:06:04 2017 +0100"
      },
      "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n"
    },
    {
      "commit": "f34dd206d0073fb3949be872224420a8488f551f",
      "tree": "b24b451af6efdd9f67c4cbd5c37ebb4ec6a4aaad",
      "parents": [
        "1f56cb5c594f5757085820b1042988d10f02bb0b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 17:41:46 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 20 00:21:29 2017 +0100"
      },
      "message": "ARM64: Support MultiplyAccumulate for SIMD.\n\nTest: test-art-host, test-art-target.\n\nChange-Id: I06af8415e15352d09d176cae828163cbe99ae7a7\n"
    },
    {
      "commit": "74234daabb28a4b9c804bf8bf908e7334bd4d400",
      "tree": "0b60cb00ab117c1a9a4b92983514962198b548bf",
      "parents": [
        "a7e9bfafeb64b1142433a41b05ddc263cadc61e3"
      ],
      "author": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Jan 13 14:42:47 2017 +0000"
      },
      "committer": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Feb 17 14:59:27 2017 +0000"
      },
      "message": "ARM: Merge data-processing instructions and shifts/(un)signed extensions\n\nThis commit mirrors the work that has already been done for ARM64.\n\nTest: m test-art-target-run-test-551-checker-shifter-operand\nChange-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8\n"
    },
    {
      "commit": "7fa7cf59540f36fbfce6d5b553d11ca486a3f207",
      "tree": "3846c085f8837469cf5c938fc7363a21d79459c1",
      "parents": [
        "e82809a2c8f26aee1e861724908f0257018cd064"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Nov 04 14:10:29 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Nov 04 14:10:29 2016 +0000"
      },
      "message": "Fix ART run-test 562-no-intermediate.\n\n- Rename it to 562-checker-no-intermediate, so that Checker\n  assertions are actually verified.\n- Fix Checker assertions, as they did not match the\n  code expected from the compiler.\n- Have the test use an integer array (instead of a double\n  array), so that Checker assertions can be extended to ARM\n  as well (the ARM back end does not support the\n  IntermediateAddress instruction on long, float and double\n  arrays).\n\nTest: make test-art-target-run-test-562-checker-no-intermediate\nBug: 30888043\nChange-Id: I32c891948c585983d5fe5d6df092bc7a59c19ae6\n"
    },
    {
      "commit": "5319d3cca5a9b8e9e3f59421818272b966575172",
      "tree": "a90bd83b7e69bbff0be601088bb1c764125d8cf6",
      "parents": [
        "9cff32df754c428ef69ddb61e7600abfd4c75266"
      ],
      "author": {
        "name": "Wojciech Staszkiewicz",
        "email": "staszkiewicz@google.com",
        "time": "Mon Aug 01 17:48:59 2016 -0700"
      },
      "committer": {
        "name": "Wojciech Staszkiewicz",
        "email": "staszkiewicz@google.com",
        "time": "Mon Aug 08 11:24:26 2016 -0700"
      },
      "message": "Implement running user defined list of passes\n\nThis change introduces new dex2oat switch --run-passes\u003d. This switch\naccepts path to a text file with names of passes to run.\nCompiler will run optimization passes specified in the file rather\nthen the default ones.\n\nThere is no verification implemented on the compiler side. It is user\u0027s\nresponsibility to provide a list of passes that leads to successful\ngeneration of correct code. Care should be taken to prepare a list\nthat satisfies all dependencies between optimizations.\n\nWe only take control of the optional optimizations. Codegen (builder),\nand all passes required for register allocation will run unaffected\nby this mechanism.\n\nChange-Id: Ic3694e53515fefcc5ce6f28d9371776b5afcbb4f\n"
    },
    {
      "commit": "328429ff48d06e2cad4ebdd3568ab06de916a10a",
      "tree": "6290ac8afc3e93488382727f6765f548a2cfff04",
      "parents": [
        "79e73245140f4115039a7284b3797d701f368fe6"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jul 06 16:23:04 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jul 21 09:16:43 2016 +0000"
      },
      "message": "ARM: Port instr simplification of array accesses.\n\nAfter changing the addressing mode for array accesses (in\nhttps://android-review.googlesource.com/248406) the \u0027add\u0027\ninstruction that calculates the base address for the array can be\nshared across accesses to the same array.\n\nBefore https://android-review.googlesource.com/248406:\n    add IP, r[Array], r[Index0], LSL #2\n    ldr r0, [IP, #12]\n    add IP, r[Array], r[Index1], LSL #2\n    ldr r0, [IP, #12]\n\nBefore this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index1], LSL #2]\n\nAfter this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    ldr r0, [IP, r[Index1], LSL #2]\n\nLink to the original optimization:\n    https://android-review.googlesource.com/#/c/127310/\n\nTest: Run ART test suite on Nexus 6.\nChange-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f\n"
    },
    {
      "commit": "87f3fcbd0db352157fc59148e94647ef21b73bce",
      "tree": "5bdeabb246f5de86704333b3fcbccc6e9146d246",
      "parents": [
        "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Apr 28 15:52:11 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jun 21 15:17:38 2016 +0100"
      },
      "message": "Replace String.charAt() with HIR.\n\nReplace String.charAt() with HArrayLength, HBoundsCheck and\nHArrayGet. This allows GVN on the HArrayLength and BCE on\nthe HBoundsCheck as well as using the infrastructure for\nHArrayGet, i.e. better handling of constant indexes than\nthe old intrinsic and using the HArm64IntermediateAddress.\n\nBug: 28330359\nChange-Id: I32bf1da7eeafe82537a60416abf6ac412baa80dc\n"
    },
    {
      "commit": "968056faf5c2cf118321871ebf234fe70db1c3c8",
      "tree": "2f7a6a13a80adfa2b552bf3e3f76919ac4c9ee0a",
      "parents": [
        "6f51d7756a9c66007fe7666b19399e1f60ff6092"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Mar 29 13:54:53 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Mar 30 11:10:45 2016 -0700"
      },
      "message": "Fix arm64 simplifier bug that tries to remove same statement twice.\nWith fail-before/pass-after test (on arm64).\n\nRationale:\nThis visitor removes statement \"forward\", which is a bit unusual, and\nexposes a bug if statement is revisited and qualifies for removal again.\n\nBUG\u003d27851582\n\nChange-Id: Ia8cddba32b4dfe9fd480852deb358eaa977f0e1f\n"
    },
    {
      "commit": "7fc6350f6f1ab04b52b9cd7542e0790528296cbe",
      "tree": "26a33ef7bb2e49a9b7c7d9436194a92cb447b317",
      "parents": [
        "b7f257f353b1eb2db2732939a0404c118316891d"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Feb 09 17:15:29 2016 +0000"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Mar 11 12:49:27 2016 +0000"
      },
      "message": "Integrate BitwiseNegated into shared framework.\n\nShare implementation between arm and arm64.\n\nChange-Id: I0dd12e772cb23b4c181fd0b1e2a447470b1d8702\n"
    },
    {
      "commit": "9ff0d205fd60cba6753a91f613b198ca2d67f04d",
      "tree": "86689672064d66d2c473045f934f948211ba0389",
      "parents": [
        "950d063395c7cecbbe372fd607468018d661a35c"
      ],
      "author": {
        "name": "Kevin Brodsky",
        "email": "kevin.brodsky@linaro.org",
        "time": "Mon Jan 11 13:43:31 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Feb 25 16:26:13 2016 +0000"
      },
      "message": "Optimizing: ARM64 negated bitwise operations simplification\n\nUse negated instructions on ARM64 to replace [bitwise operation + not]\npatterns, that is:\na \u0026 ~b (BIC)\na | ~b (ORN)\na ^ ~b (EON)\n\nThe simplification only happens if the Not is only used by the bitwise\noperation. It does not happen if both inputs are Not\u0027s (this should be\nhandled by a generic simplification applying De Morgan\u0027s laws).\n\nChange-Id: I0e112b23fd8b8e10f09bfeff5994508a8ff96e9c\n"
    },
    {
      "commit": "4a0dad67867f389e01a5a6c0fe381d210f687c0d",
      "tree": "91f1e70f4a2d0bd32aa7eb51e546f5330d72f772",
      "parents": [
        "d15ede2df7d157ea5480614fd18c2bf0d37a6c2a"
      ],
      "author": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Tue Jan 26 12:28:31 2016 +0300"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Feb 25 10:14:30 2016 +0000"
      },
      "message": "Revert \"Revert \"ARM/ARM64: Extend support of instruction combining.\"\"\n\nThis reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.\n\nChange-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6\n"
    },
    {
      "commit": "6b5afdd144d2bb3bf994240797834b5666b2cf98",
      "tree": "d536cd7b3aaf55c563e82c2c522521a91b2bb953",
      "parents": [
        "debeb98aaa8950caf1a19df490f2ac9bf563075b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "message": "Revert \"ARM/ARM64: Extend support of instruction combining.\"\n\nThe test fails its checker parts.\n\nThis reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.\n\nChange-Id: I49929e15950c7814da6c411ecd2b640d12de80df\n"
    },
    {
      "commit": "debeb98aaa8950caf1a19df490f2ac9bf563075b",
      "tree": "b2a7a7cc6fb2f56d4bcc6cecaa80035668f38dc4",
      "parents": [
        "6aadaef35ea52506db61e463910c2520b702ca5e"
      ],
      "author": {
        "name": "Ilmir Usmanov",
        "email": "i.usmanov@samsung.com",
        "time": "Fri Dec 11 11:39:44 2015 +0300"
      },
      "committer": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Thu Jan 21 11:07:38 2016 +0300"
      },
      "message": "ARM/ARM64: Extend support of instruction combining.\n\nCombine multiply instructions in the following way:\nARM64:\nMUL/NEG -\u003e MNEG\nARM32 (32-bit integers only):\nMUL/ADD -\u003e MLA\nMUL/SUB -\u003e MLS\n\nChange-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb\n"
    },
    {
      "commit": "8626b741716390a0119ffeb88b5b9fcf08e13010",
      "tree": "28d261dbb8fa3018cba8a5d829319604508ea0a1",
      "parents": [
        "0c32fdeaeda2a1e388e280da12662d1d18c834a2"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Nov 25 16:28:08 2015 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Nov 25 16:28:08 2015 +0000"
      },
      "message": "ARM64: Use the shifter operands.\n\nThis introduces architecture-specific instruction simplification.\nOn ARM64 we try to merge shifts and sign-extension operations into\narithmetic and logical instructions.\n\nFor example for the Java code\n\n    int res \u003d a + (b \u003c\u003c 5);\n\nwe would generate\n\n    lsl w3, w2, #5\n    add w0, w1, w3\n\nand we now generate\n\n    add w0, w1, w2, lsl #5\n\nChange-Id: Ic03bdff44a1c12e21ddff1b0513bd32a730742b7\n"
    },
    {
      "commit": "418318f4d50e0cfc2d54330d7623ee030d4d727d",
      "tree": "46afabf57409a5208be4eebf31e1dcbf63dc8fde",
      "parents": [
        "60c4c6ad2b892bb00a6016a147b1cc089ba6bcb5"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Nov 20 15:55:47 2015 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Nov 20 15:55:47 2015 +0000"
      },
      "message": "ARM64: Add support for multiply-accumulate.\n\nChange-Id: I88dc313df520480f3fd16bbabda27f9435d25368\n"
    },
    {
      "commit": "e6dbf48d7a549e58a3d798bbbdc391e4d091b432",
      "tree": "e9edbb884c0143a38e0b32350119999bc11b4dee",
      "parents": [
        "45513eb694fe55cf02ca6e8f0884621a6c3f6268"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Oct 19 10:10:41 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Oct 19 10:10:41 2015 +0100"
      },
      "message": "ARM64: Instruction simplification for array accesses.\n\nHArrayGet and HArraySet with variable indexes generate two\ninstructions on arm64, like\n\n    add temp, obj, #data_offset\n    ldr out, [temp, index LSL #shift_amount]\n\nWhen we have multiple accesses to the same array, the initial `add`\ninstruction is redundant.\n\nThis patch introduces the first instruction simplification in the\narm64-specific instruction simplification pass. It splits HArrayGet\nand HArraySet using the new arm64-specific IR HIntermediateAddress.\nAfter that we run GVN again to squash the multiple occurrences of\nHIntermediateAddress.\n\nChange-Id: I2e3d12fbb07fed07b2cb2f3f47f99f5a032f8312\n"
    },
    {
      "commit": "44b9cf937836bb33139123e15ca8b586b5853268",
      "tree": "a4fe52cb53133522069f41083d118fb6abca9336",
      "parents": [
        "32f264e67afa8654a5570d38b627515fb73fc333"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Aug 19 15:39:06 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Aug 19 15:39:06 2015 +0100"
      },
      "message": "Put in place the ARM64 instruction simplification framework.\n\nThis commit introduces and runs the empty InstructionSimplifierArm64\npass. Further commits will introduce arm64-specific transformations in\nthat pass.\n\nChange-Id: I458f8a2b15470297b87fc1f7ff85bd52155d93ef\n"
    }
  ]
}