)]}' { "log": [ { "commit": "55ab7e84c4682c492b6fa18375b87ffc5d0b23bb", "tree": "5fcc2567a1a4e6ae73dead2f70c69bc03b0a64bb", "parents": [ "ac27ac01490f53f9e2413dc9b66fbb2880904c96" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 27 21:02:28 2020 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Fri Feb 05 11:34:38 2021 +0000" }, "message": "ARM64: Support SVE VL other than 128-bit.\n\nArm SVE register size is not fixed and can be a\nmultiple of 128 bits. To support that the patch\nremoves explicit assumptions on the SIMD register\nsize to be 128 bit from the vectorizer and code\ngenerators and enables configurable SVE vector\nlength autovectorization, e.g. extends SIMD register\nsave/restore routines.\n\nTest: art SIMD tests on VIXL simulator.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n with FVP arg:\n -C SVE.ScalableVectorExtension.veclen\u003d[2,4]\n (SVE vector [128,256] bits wide)\n\nChange-Id: Icb46e7eb17f21d3bd38b16dd50f735c29b316427\n" }, { "commit": "8ba4de1a5684686447a578bdc425321fd3bccca6", "tree": "20c24450b24950266ccc235306e3ad2109c57497", "parents": [ "32bf6d39bc020cacfc655ce60630f4a0da3b45cf" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Dec 04 21:10:23 2019 +0000" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Thu Feb 04 06:16:33 2021 +0000" }, "message": "ART: Implement predicated SIMD vectorization.\n\nThis CL brings support for predicated execution for\nauto-vectorizer and implements arm64 SVE vector backend.\n\nThis version passes all the VIXL simulator-runnable tests in\nSVE mode with checker off (as all VecOp CHECKs need to be\nadjusted for an extra input) and all tests in NEON mode.\n\nTest: art SIMD tests on VIXL simulator.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n\nChange-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f\n" }, { "commit": "a07de551da5147f3635c665a31f262cf65647118", "tree": "d6f8199cc45ab8b6ef779f97ef0e8f0d04520ef8", "parents": [ "4483d2a4ed7e6c018e304c234484940ec0476039" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Sun Nov 01 22:42:43 2020 +0000" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Mon Nov 16 14:31:54 2020 +0000" }, "message": "Revert^2 \"ART: Fix breaking changes from recent VIXL update.\"\n\nThis reverts commit eeaf47f7c9bbad29afab84a0f199a5751d9c616b.\n\nAlso fixes the gtest failure when VIXL simulator stack\nwas overflown.\n\nTest: test-art-target, test-art-host.\nTest: ART_USE_READ_BARRIER\u003dfalse \\\n SANITIZE_HOST\u003daddress \\\n ASAN_OPTIONS\u003d\u0027detect_leaks\u003d0\u0027 \\\n SOONG_ALLOW_MISSING_DEPENDENCIES\u003dtrue \\\n ART_HEAP_POISONING\u003dtrue m test-art-host-gtest\n\nChange-Id: Ibc1f21204940083879f767d6993127bdde8326af\n" }, { "commit": "eeaf47f7c9bbad29afab84a0f199a5751d9c616b", "tree": "3b1572bd8c3cd89dbe060b52d1760bd857e999ed", "parents": [ "1f3612f93759823d630e117be5216f694e0702e9" ], "author": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Wed Oct 28 15:59:29 2020 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Oct 28 17:42:50 2020 +0000" }, "message": "Revert \"ART: Fix breaking changes from recent VIXL update.\"\n\nRevert submission 1331125-VIXL_UPDATE_SVE\n\nReason for revert: broken build git_master-art-host/art-gtest-heap-poisoning @ 6936943\nReverted Changes:\nIc10af84a0:Merge remote-tracking branch \u0027aosp/upstream-master...\nI752a0b0ba:ART: Fix breaking changes from recent VIXL update....\n\nBug: 171879890\nChange-Id: Idb0d5c2e88948d799a4ef2c828be2828ea2270ea\n" }, { "commit": "4955036617ff4940bd35fa8ce63f0728c1042902", "tree": "20ebe9c047b9ed5e21e99f2f0a00a3946fa731e8", "parents": [ "036b0708c12a33469db4a5adde9ded152b5eb700" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Jul 05 18:23:03 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 28 12:03:34 2020 +0000" }, "message": "ART: Fix breaking changes from recent VIXL update.\n\nAlso fixes the vixl-related headers includes.\n\nTest: test-art-target, test-art-host\n\nChange-Id: I752a0b0baf741aa2a0693253155042104c8b3b27\n" }, { "commit": "4f2e0889d10ae930f944c3c3f3d76e920a86c665", "tree": "f376f84b1c0fa5d64948c35a0340ab5fc5d093c2", "parents": [ "a59af8aeaad8fe7d68d8f8de63eab9cf85b6ab31" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Sun Dec 01 09:57:10 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 03 14:32:35 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API (continued (2)).\n\nMove newly added occurrences of `vixl::aarch64::FPRegister` to\n`vixl::aarch64::VRegister` in `compiler/optimizing/common_arm64.h`.\n\nTest: mmma art\nBug: 144490441\nChange-Id: Id343d64fa00373994db7bf11f5e737cca3a4f2fd\n" }, { "commit": "457e9fa3833ef11530056d010f247ad087fd2184", "tree": "54b8a9dcf44646c3e43a9085d581660c5d9a0132", "parents": [ "17a39babb7f42cbe108d6fab2760cbdc68b821a2" ], "author": { "name": "Usama Arif", "email": "usama.arif@linaro.org", "time": "Mon Nov 11 15:29:59 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 28 09:51:05 2019 +0000" }, "message": "ARM64: FP16 greater/less/greaterEquals/lessEquals intrinsics for ARMv8\n\nThis CL implements intrinsics for greater, greaterEquals, less,\nlessEquals methods with ARMv8.2 FP16 instructions. This requires the\nARMv8.2 AArch64 asimd half precision extension.\n\nThe time required in milliseconds to execute the below code for the four\nintrinsics on Pixel3 is (The code below is for FP16.less but is similar\nfor the rest of the intrinsics):\n\n- Java implementation libcore.util.FP16.less():\n - big cluster only: 19876\n - little cluster only: 47525\n- arm64 Intrinisic implementationi for less:\n - big cluster only: 14526 (~27% faster)\n - little cluster only: 45815 (~4% faster)\n\n- Java implementation libcore.util.FP16.lessEquals():\n - big cluster only: 19856\n - little cluster only: 47419\n- arm64 Intrinisic implementation for lessEquals:\n - big cluster only: 14469 (~27% faster)\n - little cluster only: 45762 (~4% faster)\n\n- Java implementation libcore.util.FP16.greater():\n - big cluster only: 19854\n - little cluster only: 47623\n- arm64 Intrinisic implementation for greater:\n - big cluster only: 14519 (~27% faster)\n - little cluster only: 45722 (~4% faster)\n\n- Java implementation libcore.util.FP16.greaterEquals():\n - big cluster only: 19865\n - little cluster only: 47216\n- arm64 Intrinisic implementation for greaterEquals:\n - big cluster only: 14485 (~27% faster)\n - little cluster only: 45729 (~4% faster)\n\npublic static boolean benchmarkComparison(){\n boolean ret \u003d false;\n long before \u003d 0;\n long after \u003d 0;\n before \u003d System.currentTimeMillis();\n for(long i \u003d 0; i \u003c 1e9; i++){\n // FP16.toHalf(12.3) \u003d 0x4a26, FP16.toHalf(12.4) \u003d 0x4a33\n // FP16.toHalf(-12.3) \u003d 0xca26, FP16.toHalf(-12.4) \u003d 0xca33\n ret |\u003d FP16.less((short) 0x4a26,(short) 0x4a33);\n ret |\u003d FP16.less((short) 0x4a33,(short) 0x4a26);\n ret |\u003d FP16.less((short) 0xca26,(short) 0xca33);\n ret |\u003d FP16.less((short) 0xca33,(short) 0xca26);\n }\n after \u003d System.currentTimeMillis();\n System.out.println(\"Time of FP16.less (ms): \" + (after - before));\n System.out.println(ret);\n return ret;\n}\n\nTest: 580-fp16\nTest: art/test/testrunner/run_build_test_target.py -j80 art-test-javac\nChange-Id: Id1a2c3e7328c82c798fcaf1fa74f5908a822cd0b\n" }, { "commit": "7d48dcd51db4b950c22ec78ef3caa53fdf4214d3", "tree": "72600968b1daf5682018880f20ca07610e62b8e7", "parents": [ "f05f04b429a63eb036f501866a863109f05b95b2" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Oct 16 12:46:28 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 31 14:56:52 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API\n\nVIXL has had FPRegister as an alias for VRegister for backward\ncompatibility. In the latest upstream VIXL the alias has been removed and all\nFPRegister based API has became VRegister based. As AOSP VIXL is being\nupdated to the latest upstream VIXL all uses of FPRegister based API\nmust be replaced with VRegister based API.\nThis CL moves ART from FPRegister based API to VRegister based API.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I12541c16d0557835ea19c8667ae18c6601359b05\n" }, { "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0", "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f", "parents": [ "e2727154f25e0db9a5bb92af494d8e47b181dfcf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n" }, { "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf", "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8", "parents": [ "c78860b91ae07eed92f86876e7a03132adea6fcd" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 10 10:46:42 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 08:22:00 2019 +0000" }, "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n - before:\n arm: 2396152\n arm64: 3345280\n - after:\n arm: 2016176 (-371KiB, -15.9%)\n arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n" }, { "commit": "f9e90541479502840c19274cf4d5b7ff22e51193", "tree": "a5ba846c0d493aae7db126ee91d635765250a6e9", "parents": [ "a3234e96206a841c83f9f5bf0d4e14fb07b72a5e" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Jun 25 13:43:53 2018 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Jun 27 13:24:35 2018 +0100" }, "message": "ART: Refactor Int64ConstantFrom to use Int64FromConstant; rename it to Int64FromLocation\n\nInt64ConstantFrom function duplicates code of the Int64FromConstant. Its\ncode can be replaced with a call: Int64FromConstant(location.getConstant()).\n\nThe patch removes the duplicating code. It also changes the function name to\nInt64FromLocation to be consistent with its usage.\n\nTest: test-art-host, test-art-target\nChange-Id: I5624259aa72523f97ca8fc132a6152f338425c8e\n" }, { "commit": "2227fe49558c5c5fc4820acb2cf357479e74b518", "tree": "bbfb6546c5da802132405569d2f06b459f12a0c3", "parents": [ "111b895dfaa271d8e9c32d1186615a0b73c106b5" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@linaro.org", "time": "Fri Apr 20 17:12:05 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 14 07:42:40 2018 +0000" }, "message": "Small refactor of MIN/MAX compiler code.\n\nIntegrate instruction code generation and location creation with\nHandleBinaryOp. Code generation has been improved for constant\ninputs 0, 1 and -1.\n\nTest: 679-checker-minmax\nTest: test-art-host, test-art-target.\n\nChange-Id: Ib34eb8a4b29d22a2491d21656e1f64011ef9f986\n" }, { "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92", "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7", "parents": [ "321b3ca9a36d769283c64d4bdee0798db80af524" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 01 14:35:42 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 02 10:11:02 2017 +0000" }, "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n" }, { "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32", "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af", "parents": [ "e1e347dace0ded83774999bb26c37527dcdb1d5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 22:50:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 25 15:45:01 2017 +0100" }, "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n" }, { "commit": "8dfe746dc969b61416a2906bea8c176427457efc", "tree": "3b5d736e7ead08f176514622684f8db7f0b7e40a", "parents": [ "a215c5b2bac883a57e1d35e5490241609ad22e5f" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Jun 01 14:28:48 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 08 13:50:28 2017 +0000" }, "message": "ARM64: Encode constants when it is possible.\n\nSmall optimization which improves HVecReplicateScalar by encoding\nimmediates directly into NEON instruction when possible instead of\ngenerating constant in GPR and transferring it into NEON register.\n\nTest: test-art-target, test-art-host.\nChange-Id: I2113bbd98c0dc8433d2b7048921b9ed7c35ef1c5\n" }, { "commit": "b31f91fd1811c9047591282dd003cf22b54938a1", "tree": "4178afdf3b28f00aa986a5f8392114352fffa87d", "parents": [ "d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Apr 05 11:31:19 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 10 14:53:24 2017 +0100" }, "message": "ARM64: Support vectorization for double and long.\n\nTest: test-art-host, test-art-target\nChange-Id: I1d4db1763b64737766f9756e5d0f85c5736e3522\n" }, { "commit": "d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331", "tree": "2890740d9cab3eee2be223666f528c6707b89f90", "parents": [ "903b8169074c01590ab3f5ad9190d9c7e3fe795b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 03 18:47:32 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 10 11:43:33 2017 +0100" }, "message": "ARM64: Support 128-bit registers for SIMD.\n\nTest: test-art-host, test-art-target\n\nChange-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa\n" }, { "commit": "74234daabb28a4b9c804bf8bf908e7334bd4d400", "tree": "0b60cb00ab117c1a9a4b92983514962198b548bf", "parents": [ "a7e9bfafeb64b1142433a41b05ddc263cadc61e3" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Jan 13 14:42:47 2017 +0000" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Feb 17 14:59:27 2017 +0000" }, "message": "ARM: Merge data-processing instructions and shifts/(un)signed extensions\n\nThis commit mirrors the work that has already been done for ARM64.\n\nTest: m test-art-target-run-test-551-checker-shifter-operand\nChange-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8\n" }, { "commit": "79db99711f6b27f6ced6b7ed52c827f5211010a9", "tree": "f153b68f97eaa8f71e87f5978b82112544af0acf", "parents": [ "e36c51aee58e61e9fc89851b767379c587f050e3" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Thu Jan 19 14:08:42 2017 +0000" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jan 27 10:17:44 2017 +0000" }, "message": "ARM64: VIXL: Fix breaking changes to ternary operator with Register inputs.\n\nTest: mma art\nChange-Id: I33d1e05e47f337f1a9271b35dba9227057cda096\n" }, { "commit": "804b03ffb9b9dc6cc3153e004c2cd38667508b13", "tree": "91c7fd54b5000e041bf9d3d5b233dabce1fad614", "parents": [ "80eb0bc2757274816a014a2997848d288c9ee553" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 14 16:26:36 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 20 14:55:44 2016 +0100" }, "message": "Change remaining slow path throw entrypoints to save everything.\n\nChange DivZeroCheck, BoundsCheck and explicit NullCheck\nslow path entrypoints to conform to kSaveEverything.\n\nOn Nexus 9, AOSP ToT, the boot.oat size reduction is\n prebuilt multi-part boot image:\n - 32-bit boot.oat: -12KiB (-0.04%)\n - 64-bit boot.oat: -24KiB (-0.06%)\n on-device built single boot image:\n - 32-bit boot.oat: -8KiB (-0.03%)\n - 64-bit boot.oat: -16KiB (-0.04%)\n\nTest: Run ART test suite including gcstress on host and Nexus 9.\nTest: Manually disable implicit null checks and test as above.\nChange-Id: If82a8082ea9ae571c5d03b5e545e67fcefafb163\n" }, { "commit": "badf2b2ad6acc01143ed81fa38586aca43400045", "tree": "4a1f5036738f53e60e808605d23883b6c7d3c4db", "parents": [ "9d185da3bef8caf015d3dbf4ad79c520af7ce3b1" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Aug 24 17:08:49 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Sep 06 11:00:45 2016 +0100" }, "message": "Remove unnecessary `static` specifiers in `common_arm64.h`.\n\nAlso fix a whitespace error.\n\nTests: Run ART test-suite on Nexus 5X and host.\n\nChange-Id: Iaf69506e8f667a4598d1105e45dacfc2d09a7fda\n" }, { "commit": "be919d90adf8a5c68e6d4d5eea004a9d5be473d2", "tree": "f6fb545811b724bfc78f34089b866f606c5b9d8a", "parents": [ "7c95b4e22897a6f14ef79ec6e547e2eed686814a" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 23 18:33:36 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 25 13:53:51 2016 +0000" }, "message": "ARM64: Use the zero register for field and array set operations.\n\nTest: Run ART test suite on host and Nexus 9.\nChange-Id: I4e2a81570ecc57530249672df704eb0bb780acce\n" }, { "commit": "af4e42a0d210aa3aa5d52926536b2ca5c2952934", "tree": "b64d683ba6ac11c0b7730df9a579aead2905dfff", "parents": [ "dce74be0c49e8a540affc0b5649a9cf8756b809b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Aug 08 15:11:24 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Aug 12 13:22:34 2016 +0100" }, "message": "ARM64: VIXL: Support a newer version of VIXL.\n\nPlease note that compiling VIXL with -Wshadow is a known VIXL issue.\n\nThis will be resolved in a later version of VIXL, when we can drop\nthe deprecated API for getters and setters.\n\nFor more info take a look at VIXL_DEPRECATED in the VIXL source code.\n\nChange-Id: Iea30b1a7b065f9b16a92c6cc7ebdc50ef068b348\n" }, { "commit": "328429ff48d06e2cad4ebdd3568ab06de916a10a", "tree": "6290ac8afc3e93488382727f6765f548a2cfff04", "parents": [ "79e73245140f4115039a7284b3797d701f368fe6" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 06 16:23:04 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 21 09:16:43 2016 +0000" }, "message": "ARM: Port instr simplification of array accesses.\n\nAfter changing the addressing mode for array accesses (in\nhttps://android-review.googlesource.com/248406) the \u0027add\u0027\ninstruction that calculates the base address for the array can be\nshared across accesses to the same array.\n\nBefore https://android-review.googlesource.com/248406:\n add IP, r[Array], r[Index0], LSL #2\n ldr r0, [IP, #12]\n add IP, r[Array], r[Index1], LSL #2\n ldr r0, [IP, #12]\n\nBefore this CL:\n add IP. r[Array], #12\n ldr r0, [IP, r[Index0], LSL #2]\n add IP. r[Array], #12\n ldr r0, [IP, r[Index1], LSL #2]\n\nAfter this CL:\n add IP. r[Array], #12\n ldr r0, [IP, r[Index0], LSL #2]\n ldr r0, [IP, r[Index1], LSL #2]\n\nLink to the original optimization:\n https://android-review.googlesource.com/#/c/127310/\n\nTest: Run ART test suite on Nexus 6.\nChange-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f\n" }, { "commit": "97c72b76cf776228196c6abd33973ef751de61ad", "tree": "7a78a2b19b0847281f8cf69af735b30b15732fa8", "parents": [ "1fd347303275a424d114c9833f954e8e27812554" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jun 24 16:19:36 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jul 15 09:48:07 2016 +0100" }, "message": "Fixes to build against new VIXL interface.\n\n- Fix namespace usage and use of deprecated functions.\n- Link all dependants to new libvixl-arm64 target for now.\n\nChange-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509\n" }, { "commit": "46817b876ab00d6b78905b80ed12b4344c522b6c", "tree": "6715bee60b0682a10437866c9617cb442146aa2f", "parents": [ "f59149a151ee694484e21da7b3b207920dead5a6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 29 12:21:58 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 19 18:33:06 2016 +0100" }, "message": "Use iterators \"before\" the use node in HUserRecord\u003c\u003e.\n\nCreate a new template class IntrusiveForwardList\u003c\u003e that\nmimicks std::forward_list\u003c\u003e except that all allocations\nare handled externally. This is essentially the same as\nboost::intrusive::slist\u003c\u003e but since we\u0027re not using Boost\nwe have to reinvent the wheel.\n\nUse the new container to replace the HUseList and use the\niterators to \"before\" use nodes in HUserRecord\u003c\u003e to avoid\nthe extra pointer to the previous node which was used\nexclusively for removing nodes from the list. This reduces\nthe size of the HUseListNode by 25%, 32B to 24B in 64-bit\ncompiler, 16B to 12B in 32-bit compiler. This translates\ndirectly to overall memory savings for the 64-bit compiler\nbut due to rounding up of the arena allocations to 8B, we\ndo not get any improvement in the 32-bit compiler.\n\nCompiling the Nexus 5 boot image with the 64-bit dex2oat\non host this CL reduces the memory used for compiling the\nmost hungry method, BatteryStats.dumpLocked(), by ~3.3MiB:\n\nBefore:\n MEM: used: 47829200, allocated: 48769120, lost: 939920\n Number of arenas allocated: 345,\n Number of allocations: 815492, avg size: 58\n ...\n UseListNode 13744640\n ...\nAfter:\n MEM: used: 44393040, allocated: 45361248, lost: 968208\n Number of arenas allocated: 319,\n Number of allocations: 815492, avg size: 54\n ...\n UseListNode 10308480\n ...\n\nNote that while we do not ship the 64-bit dex2oat to the\ndevice, the JIT compilation for 64-bit processes is using\nthe 64-bit libart-compiler.\n\nBug: 28173563\nChange-Id: I985eabd4816f845372d8aaa825a1489cf9569208\n" }, { "commit": "3a448e4af9595392c1a2308f59c084842c955e3e", "tree": "0fa1cdf37049487b61fc2f34f02d9477c55d8805", "parents": [ "cbfa10557ab6e2669747a1e21a87adf212ec44c2" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 01 18:37:46 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 01 18:37:46 2016 +0100" }, "message": "Improve debugging in art/compiler/optimizing/common_arm64.h.\n\nChange-Id: I44ff2cb64c1fd45390ed4a6517af2488fdbdaf41\n" }, { "commit": "22c4922c6b31e154a6814c4abe9015d9ba156911", "tree": "8e871f67e327322d24d0c2e4588b165005414077", "parents": [ "0205b58a0d7a9ce5832393857c19c086c78996e9" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Mar 18 14:04:28 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Mar 18 14:04:28 2016 +0000" }, "message": "Ensure art::HRor support boolean, byte, short and char inputs.\n\nAlso extend tests covering the IntegerRotateLeft,\nLongRotateLeft, IntegerRotateRight and LongRotateRight\nintrinsics and their translation into an art::HRor\ninstruction.\n\nBug: 27682579\nChange-Id: I89f6ea6a7315659a172482bf09875cfb7e7422a1\n" }, { "commit": "40a04bf64e5837fa48aceaffe970c9984c94084a", "tree": "27aeff3b9492b396050155734d81aba3c57ffbb7", "parents": [ "763fd2d3d131898cad6295a19ae9a30e22ce5f2a" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Dec 11 09:50:36 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Dec 11 16:13:44 2015 +0000" }, "message": "Replace rotate patterns and invokes with HRor IR.\n\nReplace constant and register version bitfield rotate patterns, and\nrotateRight/Left intrinsic invokes, with new HRor IR.\n\nWhere k is constant and r is a register, with the UShr and Shl on\neither side of a |, +, or ^, the following patterns are replaced:\n\n x \u003e\u003e\u003e #k OP x \u003c\u003c #(reg_size - k)\n x \u003e\u003e\u003e #k OP x \u003c\u003c #-k\n\n x \u003e\u003e\u003e r OP x \u003c\u003c (#reg_size - r)\n x \u003e\u003e\u003e (#reg_size - r) OP x \u003c\u003c r\n\n x \u003e\u003e\u003e r OP x \u003c\u003c -r\n x \u003e\u003e\u003e -r OP x \u003c\u003c r\n\nImplemented for ARM/ARM64 \u0026 X86/X86_64.\n\nTests changed to not be inlined to prevent optimization from folding\nthem out. Additional tests added for constant rotate amounts.\n\nChange-Id: I5847d104c0a0348e5792be6c5072ce5090ca2c34\n" }, { "commit": "8626b741716390a0119ffeb88b5b9fcf08e13010", "tree": "28d261dbb8fa3018cba8a5d829319604508ea0a1", "parents": [ "0c32fdeaeda2a1e388e280da12662d1d18c834a2" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Nov 25 16:28:08 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Nov 25 16:28:08 2015 +0000" }, "message": "ARM64: Use the shifter operands.\n\nThis introduces architecture-specific instruction simplification.\nOn ARM64 we try to merge shifts and sign-extension operations into\narithmetic and logical instructions.\n\nFor example for the Java code\n\n int res \u003d a + (b \u003c\u003c 5);\n\nwe would generate\n\n lsl w3, w2, #5\n add w0, w1, w3\n\nand we now generate\n\n add w0, w1, w2, lsl #5\n\nChange-Id: Ic03bdff44a1c12e21ddff1b0513bd32a730742b7\n" }, { "commit": "e6dbf48d7a549e58a3d798bbbdc391e4d091b432", "tree": "e9edbb884c0143a38e0b32350119999bc11b4dee", "parents": [ "45513eb694fe55cf02ca6e8f0884621a6c3f6268" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Oct 19 10:10:41 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Oct 19 10:10:41 2015 +0100" }, "message": "ARM64: Instruction simplification for array accesses.\n\nHArrayGet and HArraySet with variable indexes generate two\ninstructions on arm64, like\n\n add temp, obj, #data_offset\n ldr out, [temp, index LSL #shift_amount]\n\nWhen we have multiple accesses to the same array, the initial `add`\ninstruction is redundant.\n\nThis patch introduces the first instruction simplification in the\narm64-specific instruction simplification pass. It splits HArrayGet\nand HArraySet using the new arm64-specific IR HIntermediateAddress.\nAfter that we run GVN again to squash the multiple occurrences of\nHIntermediateAddress.\n\nChange-Id: I2e3d12fbb07fed07b2cb2f3f47f99f5a032f8312\n" }, { "commit": "b69fbfb5e43e404270e63b7a35dc5645b29b759c", "tree": "b41c69a226238e75bbb497930f86d5463dda31a5", "parents": [ "28c34f886521f422424768fe245b98b7b83c6bd7" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Oct 16 09:08:46 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Oct 16 09:08:46 2015 +0100" }, "message": "ARM64: Better recognition of constants encodable as immediates.\n\nWhen the right-hand side input is a constant, VIXL will automatically\nswitch between add and sub (or between similar pairs of instructions).\n\nChange-Id: Icf05237b8653c409618f44e45049df87baf0f4c6\n" }, { "commit": "82000b0cf9bb32fc55cdb125bf37c884d44a8671", "tree": "e94afb4ff819998a15c411fff967e666adecadf0", "parents": [ "4a305daf77a9b80d6abb7817a836aa59d2db521d" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jul 07 11:34:16 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jul 07 11:34:16 2015 +0100" }, "message": "Improve code generation for ARM64 VisitArrayGet/Set.\n\nWe prefer the code sequence\n add temp, obj, #offset\n ldr out, [temp, index LSL #shift_amount]\nto\n add temp, obj, index LSL #shift_amount\n ldr out, [temp, #offset]\n\nChange-Id: I98f51a1b5a5ecd84c677d6dbd4c4bfc0f157f5e2\n" }, { "commit": "da40309f61f98c16d7d58e4c34cc0f5eef626f93", "tree": "7525c544dc9acae0e1041757149be2eabb733dc8", "parents": [ "021190bf584662e75b269ef47cd48e2044e34fe4" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 24 17:35:39 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 24 17:38:13 2015 +0800" }, "message": "Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.\n\nIt should be a bit faster than load/store single registers and reduce\nthe code size.\n\nChange-Id: I67b8302adf6174b7bb728f7c2afd2c237e34ffde\n" }, { "commit": "760d8efd535764e54500bf65a944ed3f2a54c123", "tree": "70038c0f55dc41f833b24f6528daedddf0f72e34", "parents": [ "fc67542a93be3381f9c6cf226a6c5a6f30ed6e82" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sat Mar 28 18:09:56 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Apr 02 17:27:02 2015 +0100" }, "message": "Opt Compiler: ARM64 goodness\n\nThis patch:\n* Switches on PreferAcquireRelease() (used to decide if load/store\nvolatile should use acquire release-semantics or explicit memory\nbarriers). Note that for ARMv8 CPUs we should always prefer this\n(as proved by synthetic benchmarks on A53, A57 and Denver).\n\n* Enables the use of constants for HBoundsCheck\n\nChange-Id: I42524451772c05a1c74af73e97a59a95f49ba6d4\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "82e52ce8364e3e1c644d0d3b3b4f61364bf7089a", "tree": "d26020cbee67645a46838c57747d2ba1533ba5d1", "parents": [ "ebbb1e322d8c89e69424a543faa03402e5b63673" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Mar 26 16:50:57 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Mar 31 15:53:57 2015 +0100" }, "message": "ARM64: Update to VIXL 1.9.\n\nUpdate VIXL\u0027s interface to VIXL 1.9.\n\nChange-Id: Iebae947539cbad65488b7195aaf01de284b71cbb\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "2d35d9d7490ef3880ee366ccbf8f6e791f398c47", "tree": "5e512b5da7d7c290d69e4437436feb15ccad5ffc", "parents": [ "8fff8c66738b35bafc5318e408afa21c34c57ff3" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sun Feb 22 22:08:01 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Mar 17 10:47:51 2015 +0000" }, "message": "Opt Compiler: Materialise constants that cannot be encoded\n\nThe VIXL MacroAssembler deals gracefully with any immediate. However\nwhen the constant has multiple uses and cannot be encoded in the\ninstruction\u0027s immediate field we are better off using a register for\nthe constant and thus sharing the constant generation between multiple\nuses.\n\nEg:\n var +\u003d #Const; // #Const cannot be encoded.\n var +\u003d #Const;\n\nBefore: After:\n mov wip0, #Const mov w4, #Const\n add w0, w0, wip0 add w0, w0, w4\n mov wip0, #Const add w0, w0, w4\n add w0, w0, wip0\n\nChange-Id: Ied8577c879845777e52867aced16b2b45e06ac6c\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "3ce57abd8fe50a0a772d14e033a9e7c34beff6cb", "tree": "4be0ac5a10e6fd0c1d9e52feb169e89b1f77206c", "parents": [ "758c2f65805564e0c51cccaacf8307e52a9e312b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 12 11:06:03 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 12 11:06:03 2015 +0000" }, "message": "Revert \"Opt Compiler: Materialise constants that cannot be encoded\"\n\nFails building the core image.\n\nThis reverts commit 758c2f65805564e0c51cccaacf8307e52a9e312b.\n\nChange-Id: Ic3ebd8a08a3d17a513d820035b430f6de4125866\n" }, { "commit": "758c2f65805564e0c51cccaacf8307e52a9e312b", "tree": "ec8bbbe69fa3f263dd91763fe1bef81cf090f468", "parents": [ "637455782147a41fbde2e284c49ca5e02d3444c2" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sun Feb 22 22:08:01 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Wed Mar 11 17:45:09 2015 +0000" }, "message": "Opt Compiler: Materialise constants that cannot be encoded\n\nThe VIXL MacroAssembler deals gracefully with any immediate. However\nwhen the constant has multiple uses and cannot be encoded in the\ninstruction\u0027s immediate field we are better off using a register for\nthe constant and thus sharing the constant generation between multiple\nuses.\n\nEg:\n var +\u003d #Const; // #Const cannot be encoded.\n var +\u003d #Const;\n\nBefore: After:\n mov wip0, #Const mov w4, #Const\n add w0, w0, wip0 add w0, w0, w4\n mov wip0, #Const add w0, w0, w4\n add w0, w0, wip0\n\nChange-Id: I8d1f620872d1241cf582fb4f3b45b5091b790146\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "de0eb6f59853f08d94fe42088d959b88f8448123", "tree": "f3756060991a216202201890f11cb63bfd2ec205", "parents": [ "44d95a22b2d9127f9b803a70dbe00d0816e922ad" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 04 10:28:04 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 04 10:28:04 2015 +0000" }, "message": "Fix arm64 build.\n\nChange-Id: Ib6babc1c6e8f2e78badc93cfcf89950e53f71bbb\n" }, { "commit": "542361f6e9ff05e3ca1f56c94c88bc3efeddd9c4", "tree": "f9c914c1ca168d1c93148b95bec7f3e8b0659542", "parents": [ "c9ff6b112d25657128f9a7251e253b1382b0f1b9" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Jan 29 16:57:31 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Jan 29 16:57:31 2015 +0000" }, "message": "Introduce primitive type helpers.\n\nChange-Id: I81e909a185787f109c0afafa27b4335050a0dcdf\n" }, { "commit": "878d58cbaf6b17a9e3dcab790754527f3ebc69e5", "tree": "1c1af4ef938ad06a783da51e2c6276d6b0628da6", "parents": [ "b80c3154d3b6359d8ad4ce50d3a6a68224400cdd" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 23:24:00 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 28 15:32:40 2015 -0800" }, "message": "ART: Arm64 optimizing compiler intrinsics\n\nImplement most intrinsics for the optimizing compiler for Arm64.\n\nChange-Id: Idb459be09f0524cb9aeab7a5c7fccb1c6b65a707\n" } ] }