)]}' { "log": [ { "commit": "54f4fbd1a6834f06dc9b644b865423fdc03afb15", "tree": "4f55b2a196453a8a197a1787a688cc299682e55d", "parents": [ "2d3de3a40015af07f7645a298f77b398af0c6c2c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 12 10:52:22 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Feb 13 09:14:02 2020 +0000" }, "message": "Remove MIPS support from Optimizing.\n\nTest: aosp_taimen-userdebug boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 147346243\nChange-Id: I97fdc15e568ae3fe390efb1da690343025f84944\n" }, { "commit": "715f43e1553330bc804cea2951be195473dc343d", "tree": "55e143005efe10e8448c91eff6b88a635af2a3f6", "parents": [ "9e842d3e7d6102d964178e36e5d596ca91895147" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 23 11:00:32 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 23 11:00:32 2017 -0700" }, "message": "MIPS32: Improve stack alignment, use sdc1/ldc1, where possible.\n\n- Ensure that SP is a multiple of 16 at all times, and\n- Use ldc1/sdc1 to load/store FPU registers from/to 8-byte-aligned\n locations wherever possible.\n\nUse `export ART_MIPS32_CHECK_ALIGNMENT\u003dtrue` when building Android\nto enable the new runtime alignment checks.\n\nTest: Boot \u0026 run tests on 32-bit version of QEMU, and CI-20.\nTest: test/testrunner/testrunner.py --target --optimizing --32\nTest: test-art-host-gtest\nTest: test-art-target-gtest\n\nChange-Id: Ia667004573f419fd006098fcfadf5834239cb485\n" }, { "commit": "0cab65610a6a984a94ef4c3f232fe0273e78d95b", "tree": "669fa607f4cd9ad8eef9223bb124fb72265a06b3", "parents": [ "2e53f8f69f8c4175085e337445ec42aa045a2f7f" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jul 25 15:19:36 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Jul 30 20:09:26 2017 -0700" }, "message": "MIPS: Eliminate hard-coded offsets in branches\n\nThe bulk of the change is in the assemblers and their\ntests.\n\nThe main goal is to introduce \"bare\" branches to labels\n(as opposed to the existing bare branches with relative\noffsets, whose direct use we want to eliminate).\nThese branches\u0027 delay/forbidden slots are filled\nmanually and these branches do not promote to long (the\nbranch target must be within reach of the individual\nbranch instruction).\n\nThe secondary goal is to add more branch tests (mainly\nfor bare vs non-bare branches and a few extra) and\nrefactor and reorganize the branch test code a bit.\n\nThe third goal is to improve idiom recognition in the\ndisassembler, including branch idioms and a few others.\n\nFurther details:\n- introduce bare branches (R2 and R6) to labels, making\n R2 branches available for use on R6\n- make use of the above in the code generators\n- align beqz/bnez with their GNU assembler encoding to\n simplify and shorten the test code\n- update the CFI test because of the above\n- add trivial tests for bare and non-bare branches\n (addressing existing debt as well)\n- add MIPS32R6 tests for long beqc/beqzc/bc (debt)\n- add MIPS64R6 long beqzc test (debt)\n- group branch tests together\n- group constant/literal/address-loading tests together\n- make the disassembler recognize:\n - b/beqz/bnez (beq/bne with $zero reg)\n - nal (bltzal with $zero reg)\n - bal/bgezal (bal \u003d bgezal with $zero reg)\n - move (or with $zero reg)\n - li (ori/addiu with $zero reg)\n - dli (daddiu with $zero reg)\n- disassemble 16-bit immediate operands (in andi, ori,\n xori, li, dli) as signed or unsigned as appropriate\n- drop unused instructions (bltzl, bltzall, addi) from\n the disassembler as there are no plans to use them\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I62b74a6c00ce0651528114806ba24a59ba564a73\n" }, { "commit": "9983e302384c12a975c8d2d5ae239f79fd8e1996", "tree": "4e4d269fe1a3d4f0f1b93cd972adab9f17aab8e0", "parents": [ "bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 14:34:22 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 17:25:39 2017 +0100" }, "message": "Remove the old ARM code generator from ART\u0027s Optimizing compiler.\n\nThe AArch32 VIXL-based code generator has been the default\nARM code generator in ART for some time now. The old ARM\ncode generator does not compile anymore; retiring it.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db\n" }, { "commit": "97c46466aea25ab63a99b3d1afc558f0d9f55abb", "tree": "afd225f51d28a77329bc2590a025400e088f260c", "parents": [ "00cca3a275562d110a8b35094b9b12fac37f67ab" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu May 11 14:04:03 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 11 17:43:27 2017 +0100" }, "message": "Introduce a Marking Register in ARM64 code generation.\n\nWhen generating code for ARM64, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register X20,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test\nBug: 37707231\nChange-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b\n" }, { "commit": "e104d6e48fba004658f94a81ffd1211b6d2a5bff", "tree": "f3e1d464610c52c73647a2397053d16f7dcaab75", "parents": [ "bfb438a330e887b7e63e659a890098eb05420a10" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Mar 21 20:16:05 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Mar 23 13:27:57 2017 -0700" }, "message": "MIPS64: Improve method entry/exit code\n\nImprovements:\n- the stack frame is (de)allocated in one step instead of two\n- the return address register, RA, is restored early for better\n instruction scheduling\n- eliminate unused delay slot\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R2) in QEMU\n\nChange-Id: I55172bd167ed1baced82bc1d542213b93b13c2ce\n" }, { "commit": "467d94a3d926620b01b034eff68fdcaf2b5fb579", "tree": "64f16e96e416902e5a203eb94fb33e09f9d3a4e8", "parents": [ "25275bef429dc6a48b79411e0d0b32207294523b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 16 10:24:17 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 16 10:24:17 2017 +0000" }, "message": "Revert \"Revert \"ARM: VIXL32: Use VIXL backend by default.\"\"\n\nbug:35977033\n\nThis reverts commit 25275bef429dc6a48b79411e0d0b32207294523b.\n\nChange-Id: I440bf8415e2bf550607595499701fb3e7c33b37e\n" }, { "commit": "25275bef429dc6a48b79411e0d0b32207294523b", "tree": "90a96d151b5f01c5fd5961a67b2368175074c091", "parents": [ "e6316892821287b1d1906b9962eae129fbdc37be" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 14 08:57:02 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 14 08:57:02 2017 +0000" }, "message": "Revert \"ARM: VIXL32: Use VIXL backend by default.\"\n\nRevert while investigating.\n\nbug:35977033\n\nThis reverts commit e6316892821287b1d1906b9962eae129fbdc37be.\n\nChange-Id: I51e24a6e539072a6d0d470dfe41855a4847f3e96\n" }, { "commit": "e6316892821287b1d1906b9962eae129fbdc37be", "tree": "64f16e96e416902e5a203eb94fb33e09f9d3a4e8", "parents": [ "dfe9c30c7214c0874edacfd3bb602df86369c7e0" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Tue Dec 20 15:46:34 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 21 09:39:32 2017 +0000" }, "message": "ARM: VIXL32: Use VIXL backend by default.\n\nexport ART_USE_OLD_ARM_BACKEND\u003dtrue to use the previous backend.\n\nTest: mma test-art-host \u0026\u0026 mma test-art-target\n\nChange-Id: I4024a4ea15fa8ce1269c0837f6ea001b6c809df5\n" }, { "commit": "90ab673133ce97c8aa4260b45ab943900bb9b52d", "tree": "6d7751d4570c575f4d6e7e8494e4bd8f7e692315", "parents": [ "c836b5a8a5ea00b0cd332d5e60c9ec10ae1e74fb" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Thu Dec 08 10:25:03 2016 +0000" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Mon Dec 12 14:11:21 2016 +0000" }, "message": "ARM: VIXL32: Test both current and new assemblers with optimizing_cfi_test.\n\nTest: m test-art-host\n\nChange-Id: I71b97113d9bc3ad5abe5f5f89a0d94c243c8f2e2\n" }, { "commit": "9989b167ce5726950ab4c52f87a428eea7493bd6", "tree": "6e43803fcd7b6faf7c0466ac9d8b6277bee9a25a", "parents": [ "68f1128b3f98886ebe28c36e8a75f7a254db5431" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 13 13:42:30 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 13 14:40:10 2016 +0100" }, "message": "Fix optimizing_cfi_test and arm64 code generation.\n\nChange https://android-review.googlesource.com/#/c/287582/ broke it.\n\ntest: m test-art-host-gtest-optimizing_cfi_test\ntest: m test-art-target on angler\nChange-Id: I7fc74a87ffa0b26b8e103b87a2ac1179bea2145a\n" }, { "commit": "57eb0f58419e0e6773f69cf6e0c78e5fed0464cd", "tree": "5104bb1c1ad04f9f6a04fcac5d497d54ed0c97ab", "parents": [ "d7eabc2cc1a88c1f7f927da61246ae65aab0626c" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Jul 29 22:04:46 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Aug 30 16:50:28 2016 -0700" }, "message": "MIPS32: Fill branch delay slots\n\nTest: booted MIPS32 in QEMU\nTest: test-art-host-gtest\nTest: test-art-target-gtest\nTest: test-art-target-run-test-optimizing on CI20\n\nChange-Id: I727e80753395ab99fff004cb5d2e0a06409150d7\n" }, { "commit": "bde6ae1c6e1bc0ea1c8d80e3b0ec401517c6d7f7", "tree": "b8b358dbab45a235af3413b6750db13419d81dc2", "parents": [ "47fe36d8dea0309e5ff08fc77244a371ba10d9db" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Jun 10 17:46:12 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Tue Jun 28 11:07:24 2016 +0100" }, "message": "ARM64: Ensure stricter alignment when loading and storing register pairs\n\nThe impetus for this change is the fact that loads that cross a 64 byte\nboundary and stores that cross a 16 byte boundary are a performance issue\non Cortex-A57 and A72.\n\nChange-Id: I81263dc72272192ad2d190b741a955f175880461\n" }, { "commit": "73296a7c547e97ec4ea4a7e7622ed0cf49870462", "tree": "6b5e588aa7e611d1c41b8cb65c2bc61532aff631", "parents": [ "d27fd40d5353141660c033156492efd639c4d048" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Jun 03 22:51:46 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Jun 04 02:31:23 2016 -0700" }, "message": "MIPS32: Improve method entry/exit code\n\nImprovements:\n- the stack frame is (de)allocated in one step instead of two\n- callee-saved FPU registers are 8-byte aligned within the frame,\n allowing a single ldc1/sdc1 instruction to load/store an FPU\n register without causing exceptions due to misaligned accesses\n- the return address register, RA, is restored early for better\n instruction scheduling\n\nChange-Id: I556b139c62839490a9fdbce8c5e6e3e2d1cc7bb7\n" }, { "commit": "ba70200c03f0481543877b218a8626c107edfbf6", "tree": "e684332612c43e63b2af2799f2a28b0e9d2c95d5", "parents": [ "85fdcda926fbab0e5a7b3e8b3541f5d225b2bcdb" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Feb 01 18:15:29 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 02 17:18:59 2016 +0000" }, "message": "Add MIPS floating point register mapping to DWARF.\n\nChange-Id: I88508461412bc166549843744a3c6a4ee925b2c7\n" }, { "commit": "a0e87b0a97fadd54540ec7e8331b61bebd82d378", "tree": "c1027e65fd859cf59f295ff3a5630404e3724db3", "parents": [ "d83b9042d67f2a7d5ca5a1f63819c97940033336" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Sep 24 22:57:20 2015 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Nov 21 22:18:50 2015 -0800" }, "message": "MIPS64: Support short and long branches\n\nChange-Id: I618c960bd211048166d9fde78d4106bd3ca42b3a\n" }, { "commit": "10ef6941648aad04d54527d4a7a6070bf7065e88", "tree": "50fe6b50a3020ec7d25fbd5e4393db1c04452ce7", "parents": [ "c74e69f831608964f89ac7a641fbcc09156eefaa" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 22 15:25:54 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 04 14:54:23 2015 +0000" }, "message": "Delay emitting CFI PC adjustments until after Thumb2/Mips fixup.\n\nOn Mips also take into account out-of-order CFI data emitted\nfrom EmitBranches().\n\nChange-Id: I03b0b0b4c2b1ea31a02699ef5fa1c55aa42c23c3\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "9bd88b0933a372e6a7b64b850868e6a7998567e2", "tree": "bcd275674c1234842b757ea8e100c4030f9ac6fe", "parents": [ "01cb410f4ad23135671d821ba36c269f8c82affa" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Apr 22 16:24:46 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri May 22 12:01:07 2015 +0100" }, "message": "ARM64: Move xSELF from x18 to x19.\n\nThis patch moves xSELF to callee saved x19 and removes support for\nETR (external thread register), previously used across native calls.\n\nChange-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "c6b4dd8980350aaf250f0185f73e9c42ec17cd57", "tree": "ef8d73e37abc04aecb430072a8bc463c73398fee", "parents": [ "dd97393aca1a3ff2abec4dc4f78d7724300971bc" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:32:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 16:47:50 2015 +0100" }, "message": "Implement CFI for Optimizing.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2\n" } ] }