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gerrit.witaqua.org / art / 2498d855f80171d825ce1b98428cb05c8a504f84 / test / 411-checker-hdiv-hrem-const
  1. 10a312c Regenerate ART test files (2021-10-30). by Roland Levillain · 4 years, 7 months ago
  2. 87531a6 Aesthetic changes in generated ART run-test Blueprint files. by Roland Levillain · 5 years ago
  3. 9150de6 [LSC] Add LOCAL_LICENSE_KINDS to art by Bob Badour · 5 years ago
  4. b15e879 Verify ART run-tests' standard output and standard error separately. by Roland Levillain · 6 years ago
  5. a073f46 Rename ART run-tests `expected.txt` files as `expected-stdout.txt`. by Roland Levillain · 6 years ago
  6. 4258f9e Only tag supported ART run-tests as part of `art-target-run-test`. by Roland Levillain · 6 years ago
  7. 1e20e51 Build system support for Checker tests in Tradefed by Daniil Riazanovskiy · 6 years ago
  8. c679fe3 ARM: Optimize div/rem when dividend is compared with a non-negative by Evgeny Astigeevich · 6 years ago
  9. 6b0b2e7 Rename the expected-output text file in built TradeFed ART run-tests. by Roland Levillain · 6 years ago
  10. 01e5698 Add Soong module definitions for ART run-tests with default build rules. by Roland Levillain · 6 years ago
  11. f938841 ARM: Optimize Div/Rem by positive const for non-negative dividends by Evgeny Astigeevich · 6 years ago
  12. 0ddb338 ARM64: Combine LSR+ADD into ADD_shift for Int32 HDiv/HRem by Evgeny Astigeevich · 6 years ago
  13. 1439e57 ART: Optimize ADD/SUB+ADD_shift into ADDS/SUBS+CINC for HDiv/HRem by Evgeny Astigeevich · 6 years ago
  14. 968db3c ARM64: Combine LSR+ASR into ASR for Int32 HDiv/HRem by Evgeny Astigeevich · 6 years ago