)]}'
{
  "log": [
    {
      "commit": "2558abeb7acd49b7de357ca43b0c34354c20a3a0",
      "tree": "dad63d4e0153765d2edd155ac2c78473a40b4a77",
      "parents": [
        "60e29745625405654fb968ba2572ebddd8a0211d"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Oct 14 18:01:37 2020 +0100"
      },
      "committer": {
        "name": "Ulyana Trafimovich",
        "email": "skvadrik@google.com",
        "time": "Thu Feb 11 15:44:16 2021 +0000"
      },
      "message": "ARM64: Adjust SIMD checker tests for SVE.\n\nAdds SVE-specific checker line for SIMD tests\nusing isaHasFeature() function.\n\nTest: test-art-target with Neon.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n      with FVP arg:\n      -C SVE.ScalableVectorExtension.veclen\u003d[2,4]\n      (SVE vector [128,256] bits wide)\n\nChange-Id: I8f2134861b47437823797da48a3ffb680bafc544\n"
    },
    {
      "commit": "54f4fbd1a6834f06dc9b644b865423fdc03afb15",
      "tree": "4f55b2a196453a8a197a1787a688cc299682e55d",
      "parents": [
        "2d3de3a40015af07f7645a298f77b398af0c6c2c"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Feb 12 10:52:22 2020 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Feb 13 09:14:02 2020 +0000"
      },
      "message": "Remove MIPS support from Optimizing.\n\nTest: aosp_taimen-userdebug boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 147346243\nChange-Id: I97fdc15e568ae3fe390efb1da690343025f84944\n"
    },
    {
      "commit": "d935af9786dc3de5bf01a7705b94a7950569732e",
      "tree": "04f9a6c08943b52e9a1014b96aadaf739264820e",
      "parents": [
        "6390c90291b160af0c1febf303c6afe58d56134a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jun 20 14:32:54 2019 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Jun 21 08:38:58 2019 +0000"
      },
      "message": "Consolidate SIMD hadd tests.\n\nTest: testrunner.py --host --optimizing -t 646\nTest: testrunner.py --target --optimizing -t 646\nChange-Id: Id9ffbdaf15d1a664b3b0671220dff17f2e98c3ed\n"
    },
    {
      "commit": "d4f60386f3220ac0fa5b6dd566cec54db1b085fb",
      "tree": "44f268c7423c8736f3bd104ed00b7678163d3af8",
      "parents": [
        "1e739fa94947147953c53e92964e0e9e1eac0526"
      ],
      "author": {
        "name": "Tamas Kenez",
        "email": "tamaskenez@google.com",
        "time": "Thu Jun 14 16:33:53 2018 +0200"
      },
      "committer": {
        "name": "Tamas Kenez",
        "email": "tamaskenez@google.com",
        "time": "Thu Jun 14 16:33:53 2018 +0200"
      },
      "message": "ART-tests: Remove DX dependency from 646-checker-hadd(-alt)?-(short|char)\n\nThese tests had two issues with D8: (1) And operands swapped and (2) due\nto unfortunate register-allocation the live ranges of certain registers\nescaped into environment. This CL updates the CHECKS to match the D8-\ngenerated code and refactors a few expressions which results in\nshorter live ranges.\n\nTest: art/test.py -r -b --host -t 646-checker-hadd-alt-char\nTest: art/test.py -r -b --host -t 646-checker-hadd-alt-short\nTest: art/test.py -r -b --host -t 646-checker-hadd-char\nTest: art/test.py -r -b --host -t 646-checker-hadd-short\nBug: 65168732\nChange-Id: Iaa41853123f57ac4d996527414b2f434faa7c4f0\n"
    },
    {
      "commit": "9cb7fe4daf872fd0cb312489af263ebc622033a8",
      "tree": "ebd0f593fc06460232e9935e496c1a83d43aa8ca",
      "parents": [
        "f057d5d38dc812dcbe385890ccabf38674ae0d5d"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Nov 30 11:46:45 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Dec 05 11:41:20 2017 -0800"
      },
      "message": "Exploited CHECK-START-{x,y,z} syntax.\n\nRationale:\nPrevious CL introduced new check syntax\nto define multiple target architectures.\nThis CL exploits the new feature.\n\nBug: 62352954\n\nTest: test-art-host test-art-target\n\nChange-Id: Ia2b9f210b0c1483e96e1df2d3d5e27f24420245d\n"
    },
    {
      "commit": "8c6c3575668831c752820ba4174b07ee407f7a4f",
      "tree": "cf58b62f52ce6e4e78e139aa0f117191a0c11f2a",
      "parents": [
        "31275df5ea1b91ed668618d6ec64a76d67cee73c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Oct 25 11:48:48 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Oct 25 15:37:43 2017 -0700"
      },
      "message": "Make SIMD checker tests more robust.\n\nRationale:\nWith more and more peeling and cleanup loops coming up,\nsome of our checker tests were a bit fragile testing for\nthe first Phi occurrence. This CL fixes that. Also fixes\na few omissions found during the refactoring.\n\nTest: test-art-host test-art-target\nChange-Id: I9b27237cf048981ca2b5a18057e09211b7002486\n"
    },
    {
      "commit": "61b922847403ac0e74b6477114c81a28ac2e01a0",
      "tree": "02674602fb2592f758f51389b3c7b276ab4df3ee",
      "parents": [
        "6783118d2ad9d759f0617b1219a9e29a10a569f7"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 11 13:23:17 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 18 15:52:51 2017 +0100"
      },
      "message": "ART: Introduce Uint8 loads in compiled code.\n\nSome vectorization patterns are not recognized anymore.\nThis shall be fixed later.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --target --optimizing on Nexus 5X\nTest: Nexus 5X boots.\nBug: 23964345\nBug: 67935418\nChange-Id: I587a328d4799529949c86fa8045c6df21e3a8617\n"
    },
    {
      "commit": "d5d2f2ce627aa0f6920d7ae05197abd1a396e035",
      "tree": "e8e780780c832e3614a22438a23fb60ee4960ca3",
      "parents": [
        "efac0df8c738764823c637deeca1f3be33912064"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 26 12:37:26 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 10:40:51 2017 +0100"
      },
      "message": "ART: Introduce Uint8 compiler data type.\n\nThis CL adds all the necessary codegen for the Uint8 type\nbut does not add code transformations that use that code.\nVectorization codegens are modified to use Uint8 as the\npacked type when appropriate. The side effects are now\ndisconnected from the instruction\u0027s type after the graph has\nbeen built to allow changing HArrayGet/H*FieldGet/HVecLoad\nto use a type different from the underlying field or array.\n\nNote: HArrayGet for String.charAt() is modified to have\nno side effects whatsoever; Strings are immutable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --target --optimizing on Nexus 6P\nTest: Nexus 6P boots.\nBug: 23964345\nChange-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0\n"
    },
    {
      "commit": "8f7c41044bdb7a36913444a3437bf2b946f7efe9",
      "tree": "cdfcc8dae149617f6270198e15101b329f821ebd",
      "parents": [
        "a4811cd3496eb28295fe61057844c53793f3023e"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jun 21 11:21:37 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Jun 30 11:52:24 2017 +0100"
      },
      "message": "ARM: ART Vectorizer (64-bit vectors).\n\nBasic vectorization support with 64-bit vector length on ARM 32-bit\nplatforms (128-bit vectors require massive changes in register\nallocator).\n\nTest: test-art-target, test-art-host\n\nChange-Id: I1d740146c3f00170fc033ae5fd69d59321ddcbf4\n"
    },
    {
      "commit": "19680d3655433e98582983ed0a6d44d6b4822951",
      "tree": "15113506e75b1480c5c1d3cfdf9df4480f30eae8",
      "parents": [
        "0a5ace58e973da278049f837bf2cdbaf7b44849c"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Thu May 11 10:38:36 2017 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Mon May 29 17:57:39 2017 +0200"
      },
      "message": "MIPS64: ART Vectorizer\n\nMIPS64 implementation which uses MSA extension. Also extended all\nrelevant checker tests to test MIPS64 implementation.\n\nTest: booted MIPS64R6 in QEMU\nTest: ./testrunner.py --target --optimizing -j1 in QEMU\n\nChange-Id: I8b8a2f601076bca1925e21213db8ed1d41d79b52\n"
    },
    {
      "commit": "f3e61ee363fe7f82ef56704f06d753e2034a67dd",
      "tree": "a00f1fce4a2e284b0a03f941f530afc5b5c56b59",
      "parents": [
        "741a81af441cbcb7255229bf250bc009d2894e92"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 12 17:09:20 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 19 10:30:57 2017 -0700"
      },
      "message": "Implement halving add idiom (with checker tests).\n\nRationale:\nFirst of several idioms that map to very efficient SIMD instructions.\nNote that the is-zero-ext and is-sign-ext are general-purpose utilities\nthat will be widely used in the vectorizer to detect low precision\nidioms, so expect that code to be shared with many CLs to come.\n\nTest: test-art-host, test-art-target\nChange-Id: If7dc2926c72a2e4b5cea15c44ef68cf5503e9be9\n"
    }
  ]
}