)]}'
{
  "log": [
    {
      "commit": "40a04bf64e5837fa48aceaffe970c9984c94084a",
      "tree": "27aeff3b9492b396050155734d81aba3c57ffbb7",
      "parents": [
        "763fd2d3d131898cad6295a19ae9a30e22ce5f2a"
      ],
      "author": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Fri Dec 11 09:50:36 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Dec 11 16:13:44 2015 +0000"
      },
      "message": "Replace rotate patterns and invokes with HRor IR.\n\nReplace constant and register version bitfield rotate patterns, and\nrotateRight/Left intrinsic invokes, with new HRor IR.\n\nWhere k is constant and r is a register, with the UShr and Shl on\neither side of a |, +, or ^, the following patterns are replaced:\n\n  x \u003e\u003e\u003e #k OP x \u003c\u003c #(reg_size - k)\n  x \u003e\u003e\u003e #k OP x \u003c\u003c #-k\n\n  x \u003e\u003e\u003e r OP x \u003c\u003c (#reg_size - r)\n  x \u003e\u003e\u003e (#reg_size - r) OP x \u003c\u003c r\n\n  x \u003e\u003e\u003e r OP x \u003c\u003c -r\n  x \u003e\u003e\u003e -r OP x \u003c\u003c r\n\nImplemented for ARM/ARM64 \u0026 X86/X86_64.\n\nTests changed to not be inlined to prevent optimization from folding\nthem out. Additional tests added for constant rotate amounts.\n\nChange-Id: I5847d104c0a0348e5792be6c5072ce5090ca2c34\n"
    },
    {
      "commit": "8626b741716390a0119ffeb88b5b9fcf08e13010",
      "tree": "28d261dbb8fa3018cba8a5d829319604508ea0a1",
      "parents": [
        "0c32fdeaeda2a1e388e280da12662d1d18c834a2"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Nov 25 16:28:08 2015 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Nov 25 16:28:08 2015 +0000"
      },
      "message": "ARM64: Use the shifter operands.\n\nThis introduces architecture-specific instruction simplification.\nOn ARM64 we try to merge shifts and sign-extension operations into\narithmetic and logical instructions.\n\nFor example for the Java code\n\n    int res \u003d a + (b \u003c\u003c 5);\n\nwe would generate\n\n    lsl w3, w2, #5\n    add w0, w1, w3\n\nand we now generate\n\n    add w0, w1, w2, lsl #5\n\nChange-Id: Ic03bdff44a1c12e21ddff1b0513bd32a730742b7\n"
    },
    {
      "commit": "418318f4d50e0cfc2d54330d7623ee030d4d727d",
      "tree": "46afabf57409a5208be4eebf31e1dcbf63dc8fde",
      "parents": [
        "60c4c6ad2b892bb00a6016a147b1cc089ba6bcb5"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Nov 20 15:55:47 2015 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Nov 20 15:55:47 2015 +0000"
      },
      "message": "ARM64: Add support for multiply-accumulate.\n\nChange-Id: I88dc313df520480f3fd16bbabda27f9435d25368\n"
    },
    {
      "commit": "e6dbf48d7a549e58a3d798bbbdc391e4d091b432",
      "tree": "e9edbb884c0143a38e0b32350119999bc11b4dee",
      "parents": [
        "45513eb694fe55cf02ca6e8f0884621a6c3f6268"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Oct 19 10:10:41 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Oct 19 10:10:41 2015 +0100"
      },
      "message": "ARM64: Instruction simplification for array accesses.\n\nHArrayGet and HArraySet with variable indexes generate two\ninstructions on arm64, like\n\n    add temp, obj, #data_offset\n    ldr out, [temp, index LSL #shift_amount]\n\nWhen we have multiple accesses to the same array, the initial `add`\ninstruction is redundant.\n\nThis patch introduces the first instruction simplification in the\narm64-specific instruction simplification pass. It splits HArrayGet\nand HArraySet using the new arm64-specific IR HIntermediateAddress.\nAfter that we run GVN again to squash the multiple occurrences of\nHIntermediateAddress.\n\nChange-Id: I2e3d12fbb07fed07b2cb2f3f47f99f5a032f8312\n"
    }
  ]
}