)]}' { "log": [ { "commit": "296bd60423e0630d8152b99fb7afb20fbff5a18a", "tree": "384aa7659763bb77a038a67c27f7cf6059632570", "parents": [ "57b4d1c44e246dfd4aaef2d23b20a696a0c5e57e" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Oct 06 16:47:28 2014 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Nov 03 16:16:50 2014 -0800" }, "message": "Some improvement to reg alloc.\n\nChange-Id: If579a37791278500a7e5bc763f144c241f261920\n" }, { "commit": "1f897b98e19a9b0192a373ee9d3c2fcb4a9463f4", "tree": "d857ca02dec553b30a6fd8d5d39ca88b2ece95ab", "parents": [ "4ff20eba94a2519e5bac57b5f92e04741ea90141" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 17:14:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 17:14:05 2014 +0100" }, "message": "Fix register_allocator_test after reg alloc changes.\n\nChange-Id: Ieaf5daf35efaff6685720a93a442cd7a152f1567\n" }, { "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f", "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a", "parents": [ "a3c4d72210de174552f47b2d117b1946f274af1e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 11:47:51 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 14:42:13 2014 +0100" }, "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n" }, { "commit": "01ef345767ea609417fc511e42007705c9667546", "tree": "8a3cf1b5a576caf212ef31db966b97b6d23aaf98", "parents": [ "a9f2904263581f606a5704f2bb74efcecf7e9f97" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 01 11:32:17 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 21:25:27 2014 +0100" }, "message": "Add trivial register hints to the register allocator.\n\n- Add hints for phis, same as first input, and expected registers.\n- Make the if instruction accept non-condition instructions.\n\nChange-Id: I34fa68393f0d0c19c68128f017b7a05be556fbe5\n" }, { "commit": "fd680d8c8b3ab7cf162bae2d322f6327d05ef23f", "tree": "16415bde6d075b7dee49cec908e7c7c1971a18e7", "parents": [ "eb1d22bf405f0edaeb34f78905d75f167e88b868" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Sep 29 09:46:03 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Sep 29 09:46:42 2014 +0100" }, "message": "Fix test now that instructions can die at instruction entry.\n\nChange-Id: I816279c55d12de8e69ac0b6c88730bd676c03335\n" }, { "commit": "aac0f39a3501a7f7dd04b2342c2a16961969f139", "tree": "ef71b73a7d95de726d36883e6c88f7c8cbcfaaf6", "parents": [ "56369897d662ea63ea5ed57ae36af0ae0fa1452d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 16 14:11:14 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 16 14:15:22 2014 +0100" }, "message": "Fix a bug in the register allocator.\n\nWe need to take the live interval that starts first to know\nuntil when a register is free, instead of using the live interval\nthat is last in the inactive list.\n\nChange-Id: I2c9f87481ff1b4fc7b9948db7559b8d3b11d84ce\n" }, { "commit": "8a16d97fb8f031822b206e65f9109a071da40563", "tree": "9dbbf5feaac15d2e4f54fbfc3c204fcdd6e8317a", "parents": [ "c7f6b86c269727fe031146b9c18652d40916d46f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 11 10:30:02 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 11 10:32:12 2014 +0100" }, "message": "Fix valgrind errors.\n\nFor now just stack allocate the code generator. Will think\nabout cleaning up the root problem later (CodeGenerator being an\narena object).\n\nChange-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7\n" }, { "commit": "3946844c34ad965515f677084b07d663d70ad1b8", "tree": "0d85bfba2ff69c34a2897351d1e50a1464509305", "parents": [ "e2c23739c6395a83b30ece38f8a2e9e1bf7cf3ce" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 02 15:17:15 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Sep 08 12:15:07 2014 +0100" }, "message": "Runtime support for the new stack maps for the opt compiler.\n\nNow most of the methods supported by the compiler can be optimized,\ninstead of using the baseline.\n\nChange-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa\n" }, { "commit": "3ac17fcce8773388512ce72cb491b202872ca1c1", "tree": "475c779c2ee973cf51a0a63c9d010c59c4b2d022", "parents": [ "269c3360f8e69e9faf8bc8a51fd87ae7adadfb59" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Aug 06 23:02:54 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 07 00:02:31 2014 +0100" }, "message": "Fix SsaDeadPhiElimination in the presence of dependent phis.\n\nThis fixes the problem of having a dead loop phi taking as back-edge\ninput a phi that also has this loop phi as input. Walking backwards\ndoes not solve the problem because the loop phi will be visited last.\n\nMost of the time, dex removes dead locals like this.\n\nChange-Id: I797198cf9c15f8faa6585cca157810e23aaa4940\n" }, { "commit": "de025a7d90603d58c62b8fd91393f13d8826a7ac", "tree": "232d9bb31e75d76093352f2771d774991965ffdf", "parents": [ "b5dc9444777bb027b070d3ff3fcf7a2a3fb7e3dc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 19 17:06:46 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 25 14:12:33 2014 +0100" }, "message": "Fix a bug in LiveInterval::FirstRegisterUseAfter.\n\nSince the use list is shared amongst siblings, we must stop looking\nfor the user once we have reached the end position of the current\ninterval. The next uses are for the next sibling.\n\nChange-Id: Ibba180161e94a705e2034abd0b95a29347950257\n" }, { "commit": "86dbb9a12119273039ce272b41c809fa548b37b6", "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5", "parents": [ "c936622863a50bdda9b10062515dfc02a8c8b652" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 04 11:12:39 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 12 10:02:06 2014 +0100" }, "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n inputs/output to be at a specific location, and the allocator\n needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n" }, { "commit": "31d76b42ef5165351499da3f8ee0ac147428c5ed", "tree": "4f9cf307923c72f73e4a814662a26406f155c38c", "parents": [ "7eb3fa1e03b070c55ecbc814e2e3ae4409cf7b1e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 09 15:02:22 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 10 10:48:50 2014 +0100" }, "message": "Plug code generator into liveness analysis.\n\nAlso implement spill slot support.\n\nChange-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc\n" }, { "commit": "a7062e05e6048c7f817d784a5b94e3122e25b1ec", "tree": "a5d6b64ae6d5352f761fc2547bda863281adbe40", "parents": [ "8b5b1e5593ffa77c393e4172b71a3d5a821d2ed8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 22 12:50:17 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 26 11:31:38 2014 +0100" }, "message": "Add a linear scan register allocator to the optimizing compiler.\n\nThis is a \"by-the-book\" implementation. It currently only deals\nwith allocating registers, with no hint optimizations.\n\nThe changes remaining to make it functional are:\n- Allocate spill slots.\n- Resolution and placements of Move instructions.\n- Connect it to the code generator.\n\nChange-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4\n" } ] }