)]}'
{
  "log": [
    {
      "commit": "29aa08219ff72409e9f10ae2a5da4e6e604baad1",
      "tree": "2ccde97263f82b6a2f1a83d5b674f46c412c2909",
      "parents": [
        "8e68c6c85ad188e306cd66f8b620350f996fe242"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Mar 08 11:28:00 2018 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Mar 15 09:49:18 2018 -0700"
      },
      "message": "Vectorization of saturation arithmetic.\n\nRationale:\nBecause faster is better.\n\nBug: b/74026074\n\nTest: test-art-host,target\n\nChange-Id: Ifa970a62cef1c0b8bb1c593f629d8c724f1ffe0e\n"
    },
    {
      "commit": "1f8d51bc03cbc607ae32fadf3a90f385adeffb95",
      "tree": "70e18902051ce47e0d524525b83709efbe6f250f",
      "parents": [
        "7a02c66fd9ed174fc2e49ccc9f582dd661b7de9e"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Feb 15 10:42:37 2018 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Mar 07 09:22:09 2018 -0800"
      },
      "message": "Introduce MIN/MAX/ABS as HIR nodes.\n\nRationale:\nHaving explicit MIN/MAX/ABS operations (in contrast\nwith intrinsics) simplifies recognition and optimization\nof these common operations (e.g. constant folding, hoisting,\ndetection of saturation arithmetic). Furthermore, mapping\nconditionals, selectors, intrinsics, etc. (some still TBD)\nonto these operations generalizes the way they are optimized\ndownstream substantially.\n\nBug: b/65164101\n\nTest: test-art-host,target\n\nChange-Id: I69240683339356e5a012802f179298f0b04c6726\n"
    },
    {
      "commit": "3b2a595f7781a5a6064c5d635454dd42fe130833",
      "tree": "cd2cc5b497b4af83aea893aa3e82aeb10ad4ea2f",
      "parents": [
        "f46f46cf5bd32788d5252b7107628a66594a5e98"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Mar 05 13:55:28 2018 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Mar 05 13:55:28 2018 -0800"
      },
      "message": "Introduce ABS as HIR nodes (missing file).\n\nNOTE: includes a file that should have been there.\n\nBug: b/65164101\nTest: test-art-host,target\nChange-Id: Ic786b84b2635ea8f5909ad77196857f6de65bf26\n"
    },
    {
      "commit": "66c158ef6b2a16257f1590b3ace78848a7c2407b",
      "tree": "f17f7eee70aa43711c7eb764c1789f4ec17aef37",
      "parents": [
        "92d0c8b68c24a2fa21f95d63a1ff2fb00fdb9aaf"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jan 31 12:55:04 2018 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Feb 01 13:26:03 2018 -0800"
      },
      "message": "Clean up signed/unsigned in vectorizer.\n\nRationale:\nCurrently we have some remaining ugliness around signed and unsigned\nSIMD operations due to lack of kUint32 and kUint64 in the HIR. By\n\"softly\" introducing these types, ABS/MIN/MAX/HALVING_ADD/SAD_ACCUMULATE\noperations can solely rely on the packed data types to distinguish\nbetween signed and unsigned operations. Cleaner, and also allows for\nsome code removal in the current loop optimizer.\n\nBug: 72709770\n\nTest: test-art-host test-art-target\nChange-Id: I68e4cdfba325f622a7256adbe649735569cab2a3\n"
    },
    {
      "commit": "2dd7b672ea0afd7ea4448b43d24829e9886de3af",
      "tree": "fd7e3c48f5ac17fc238bff68bf33e5868d1386dc",
      "parents": [
        "718173b7705ebc7f4a15aaaa4c074f9e5d907b31"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Dec 07 11:11:22 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Dec 07 15:43:33 2017 -0800"
      },
      "message": "Fixed spilling bug (visible on ARM64): missed SIMD type.\n\nTest: test-art-host test-art-target\nChange-Id: I6f321446f54943e02f250732ec9da729f633c3a9\n"
    },
    {
      "commit": "2ca10eb3f47ef3c2535c137853f7a63d10bb908b",
      "tree": "3684d1d5ef4791795b64620e97f952896c5a2011",
      "parents": [
        "02f41015a0933f146b886c62bb5b02c322ddf882"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Nov 15 15:17:53 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Nov 20 10:38:26 2017 -0800"
      },
      "message": "Refactored optimization passes setup.\n\nRationale:\nRefactors the way we set up optimization passes\nin the compiler into a more centralized approach.\nThe refactoring also found some \"holes\" in the\nexisting mechanism (missing string lookup in\nthe debugging mechanism, or inablity to set\nalternative name for optimizations that may repeat).\n\nBug: 64538565\n\nTest: test-art-host test-art-target\nChange-Id: Ie5e0b70f67ac5acc706db91f64612dff0e561f83\n"
    },
    {
      "commit": "38e380b3c5139c0993495a7a0f040bfe8aa1e9e9",
      "tree": "6dec57248cda239cd79c81bb44037ed2783a9e48",
      "parents": [
        "1121e0a658be73c5bc494df99ceb84513a65c8a8"
      ],
      "author": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Mon Oct 30 16:17:10 2017 +0100"
      },
      "committer": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@mips.com",
        "time": "Wed Nov 15 10:23:29 2017 +0100"
      },
      "message": "MIPS: Implement Sum-of-Abs-Differences\n\nTest: test-art-host test-art-target\n\nChange-Id: I32a3e21f96cdcbab2e108d71746670408deb901a\n"
    },
    {
      "commit": "2ffb703bf431d74326c88266b4ddaf225eb3c6ad",
      "tree": "0552c3c76a42b18f9e7460d501fb71a6dc2e7f33",
      "parents": [
        "c4b6f3116f15c8e4fdf2e4f604ababdee12d8923"
      ],
      "author": {
        "name": "Igor Murashkin",
        "email": "iam@google.com",
        "time": "Wed Nov 08 13:35:21 2017 -0800"
      },
      "committer": {
        "name": "Igor Murashkin",
        "email": "iam@google.com",
        "time": "Wed Nov 08 15:15:52 2017 -0800"
      },
      "message": "cpplint: Cleanup errors\n\nCleanup errors from upstream cpplint in preparation\nfor moving art\u0027s cpplint fork to upstream tip-of-tree cpplint.\n\nTest: cd art \u0026\u0026 mm\nBug: 68951293\nChange-Id: I15faed4594cbcb8399850f8bdee39d42c0c5b956\n"
    },
    {
      "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92",
      "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7",
      "parents": [
        "321b3ca9a36d769283c64d4bdee0798db80af524"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 01 14:35:42 2017 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 02 10:11:02 2017 +0000"
      },
      "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n"
    },
    {
      "commit": "13e6f2935d67742e9eec14b412d33bf71b20697b",
      "tree": "a2edd43e564e04f7b948a11e17c9025a0cd82f54",
      "parents": [
        "5804e35269ec247ba794567debdfc7a0c623d919",
        "38a3f21959d5c68d3034d4d3cef0cc231ebce78a"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Nov 01 18:16:30 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Nov 01 18:16:30 2017 +0000"
      },
      "message": "Merge \"Alignment optimizations in vectorizer.\""
    },
    {
      "commit": "38a3f21959d5c68d3034d4d3cef0cc231ebce78a",
      "tree": "fae9ab2b683bd2494a1480c7453e1beeace0e836",
      "parents": [
        "df12b6fbd98883cc1714f731847b7628f2fb7f11"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Oct 20 17:02:21 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Oct 27 10:50:36 2017 -0700"
      },
      "message": "Alignment optimizations in vectorizer.\n\nRationale:\nSince aligned data access is generally better (enables more efficient\naligned moves and prevents nasty cache line splits), computing and/or\nenforcing alignment has been added to the vectorizer:\n\n  (1) If the initial alignment is known completely and suffices,\n      then a static peeling factor enforces proper alignment.\n  (2) If (1) fails, but the base alignment allows, dynamically peeling\n      until total offset is aligned forces proper aligned access patterns.\n\nBy using ART conventions only, any forced alignment is preserved\nover suspends checks where data may move.\n\nNote 1:\nCurrent allocation convention is just 8 byte alignment on arrays/strings,\nso only ARM32 benefits. However, all optimizations are implemented in\na general way, so moving to a 16 byte alignment will immediately\ntake advantage of any new convention!!\n\nNote 2:\nThis CL also exposes how bad the choice of 12 byte offset of arrays\nreally is. Even though the new optimizations fix the misaligned, it\nrequires peeling for the most common case: 0 indexed loops. Therefore,\nwe may even consider moving to a 16 byte offset. Again the optimizations\nin this CL will immediately take advantage of that new convention!!\n\nTest: test-art-host test-art-target\n\nChange-Id: Ib6cc0fb68c9433d3771bee573603e64a3a9423ee\n"
    },
    {
      "commit": "e434c4f47e30a6440834d14ee060f2879cbc18aa",
      "tree": "fd7ef3045089da9da5671e830edf55114aaf8bf1",
      "parents": [
        "5751dc831ffd8acb089c2aff2e2ddf18f89da975"
      ],
      "author": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Mon Oct 23 16:40:22 2017 +0200"
      },
      "committer": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Fri Oct 27 12:34:58 2017 +0200"
      },
      "message": "MIPS: Basic SIMD reduction support.\n\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs for MIPS.\n\nNote: Testing is done with checker parts of tests 661 and 665,\n      locally changed to cover MIPS32 cases. These changes can\u0027t\n      be included in this patch since MSA is not a default option.\n\nTest: test-art-host test-art-target\nChange-Id: Ia3b3646afecb76c2f00996a30923ca70302be57e\n"
    },
    {
      "commit": "4d1a9d4b01ef0bbea3b7dfa9f31420d6e1d0ac83",
      "tree": "dd60bed0d302987c2a8f766d58fc855f510183c5",
      "parents": [
        "758aeab86b79369f9dfc6ae5d3bd98232f5b9c40"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Oct 19 14:40:55 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Oct 20 11:10:52 2017 -0700"
      },
      "message": "Improve sign and zero extension analysis.\n\nRationale:\nThis was needed to fix the regression introduced by\na prior type based cl. With the new type system ramping\nup, however, this is actually more  simplification (remove\nthe And recognition for example) than new code!\n\nTest: test-art-host test-art-target\n\nBug: 67935418\nChange-Id: I4284f8f29f3d26e4033a3014d0c697677cc0d795\n"
    },
    {
      "commit": "89b8df04fb1a2f10ab011e0b7d813098e095fbb9",
      "tree": "0b3f39060d69ab0d6409a57b29a632f9ed44b917",
      "parents": [
        "e478ed98446bff1ede5084c755313ee84afc036f"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Fri Oct 13 08:33:17 2017 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Fri Oct 13 08:35:24 2017 +0200"
      },
      "message": "Fix min/max SIMD reduction\n\nUse HVecReplicateScalar instead of HVecSetScalars when creating an\ninitial vector for min/max. This way we are preventing that zeroes\nfrom the initial vector are taken into account for min/max\ncalculations. Otherwise, min(MAX_INT, x[0],.., x[n-1]) \u003d 0 if each\nx[i] is positive which is incorrect.\n\nAdded regression test cases in 661-checker-simd-reduc.\n\nTest: ./testrunner.py --target --optimizing in QEMU (arm64)\n\nChange-Id: I1779eefc7f2ab9971dec561b2e1fbf262652410e\n"
    },
    {
      "commit": "6e9b137f0439b3ceedb8114bd93fa9fb746e42fa",
      "tree": "1fc138f4f0727fe4e78141fb2979c665d1fe157b",
      "parents": [
        "4c3682649ebcaef4ab237f523f8e39ebd65e4f8d"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Oct 05 16:48:30 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Oct 12 18:04:48 2017 +0100"
      },
      "message": "ARM: Support SIMD reduction for 32-bit backend.\n\nSupport SIMD reduction (add, min, max) and SAD (for int-\u003eint only)\nidioms for arm (32-bit) backend.\n\nTest: test-art-target, test-art-host\nTest: 661-checker-simd-reduc, 660-checker-simd-sad-int\n\nChange-Id: Ic6121f5d781a9bcedc33041b6c4ecafad9b0420a\n"
    },
    {
      "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1",
      "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07",
      "parents": [
        "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 14:49:14 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Oct 06 17:53:50 2017 +0100"
      },
      "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n"
    },
    {
      "commit": "46b6dbcd18df0cb5915ca906fefd9f0b0a1af6a2",
      "tree": "723856081b9d0abcc017b323672e4b1cc99cad16",
      "parents": [
        "844a4edc7f72e33a3b328c3d53ef710909d2273d"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Oct 03 11:37:37 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Oct 05 10:42:13 2017 -0700"
      },
      "message": "Try to preserve dex pc better in vector code.\n\nAlso improves a few comment and uses new data\ntype method to test type consistency.\n\nTest: test-art-host\n\nChange-Id: I4a17f9d5bc458a091a259dd45ebcdc6531abbf84\n"
    },
    {
      "commit": "d5d2f2ce627aa0f6920d7ae05197abd1a396e035",
      "tree": "e8e780780c832e3614a22438a23fb60ee4960ca3",
      "parents": [
        "efac0df8c738764823c637deeca1f3be33912064"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 26 12:37:26 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 10:40:51 2017 +0100"
      },
      "message": "ART: Introduce Uint8 compiler data type.\n\nThis CL adds all the necessary codegen for the Uint8 type\nbut does not add code transformations that use that code.\nVectorization codegens are modified to use Uint8 as the\npacked type when appropriate. The side effects are now\ndisconnected from the instruction\u0027s type after the graph has\nbeen built to allow changing HArrayGet/H*FieldGet/HVecLoad\nto use a type different from the underlying field or array.\n\nNote: HArrayGet for String.charAt() is modified to have\nno side effects whatsoever; Strings are immutable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --target --optimizing on Nexus 6P\nTest: Nexus 6P boots.\nBug: 23964345\nChange-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0\n"
    },
    {
      "commit": "df011c3bc3db8b327f2b2d93e108c3a53a9a4f34",
      "tree": "f1674e28d38bb37d81c3ddb58dbe843974852e46",
      "parents": [
        "9c0a6ce0a41eaf78f3fc3224fc34195601b6e0b3"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Sep 28 12:53:04 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Oct 02 09:54:20 2017 -0700"
      },
      "message": "Generalized zero/sign-ext analysis. Generalized SAD.\n\nRationale:\nThe more, the better. Some of the analysis was\noverly conservative (e.g. extension does not\nneed to happen from terminals only as long\nas vectorized guarantees higher order bits\ndon\u0027t contribute). Also, added hidden-SUB for SAD.\n\nTest: test-art-host test-art-target\n\nBug: 64091002\nChange-Id: I66afd8fb4292ce5cf14f98f9c5ce2bf2b8c98488\n"
    },
    {
      "commit": "68ca702c800d40b3e1f9aecdb6d5385b3492fda1",
      "tree": "c0b0fbf453d3d8198e747fa99b4817504f5c16a8",
      "parents": [
        "e5b35ed787fbfb388d162361310bae5b0e7682a7"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Sep 26 16:44:23 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 27 09:27:05 2017 -0700"
      },
      "message": "Added SAD test. Generalized vector analysis of narrow type.\n\nRationale:\nThe new example shows that scalar type of array reference does not\nreflect signed-ness or unsigned-ness of vector operation. Instead\nthe vectorizer\u0027s analysis looks at zero or sign extension to determine\nwhat operation is required and passes this as explicit or implicit\nattribute to the code generator. So don\u0027t use packed data type to\ndecide what operation to perform. This become relevant while switching\nto explicit signed and unsigned data types, where we want to pass the\nright type to make this decision in the future\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: I49a8827a13dd703910effcb5a5ebc4b9646cd1e8\n"
    },
    {
      "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32",
      "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af",
      "parents": [
        "e1e347dace0ded83774999bb26c37527dcdb1d5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 21 22:50:39 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 25 15:45:01 2017 +0100"
      },
      "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n"
    },
    {
      "commit": "dbbac8f812a866b1b53f3007721f66038d208549",
      "tree": "05cecd927afccd33fc1c14b39ada47e86873f560",
      "parents": [
        "2406bf17998e15bd40677a907beb3e9c41facce4"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Sep 01 13:06:08 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Sep 21 10:20:55 2017 -0700"
      },
      "message": "Implement Sum-of-Abs-Differences idiom recognition.\n\nRationale:\nCurrently just on ARM64 (x86 lacks proper support),\nusing the SAD idiom yields great speedup on loops\nthat compute the sum-of-abs-difference operation.\nAlso includes some refinements around type conversions.\n\nSpeedup ExoPlayerAudio (golem run):\n1.3x on ARM64\n1.1x on x86\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: Ia2b711d2bc23609a2ed50493dfe6719eedfe0130\n"
    },
    {
      "commit": "521b50f58f2af8b5a68f821a6c4eac7d86ec01f5",
      "tree": "68e41bad2a2106e27bfd470b627f11706d9b6e92",
      "parents": [
        "d4d11822e349e7e4af0b43cb3fc69e14f1c95475"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Sat Sep 09 10:44:45 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Sep 11 10:02:55 2017 -0700"
      },
      "message": "No unrolling for large loop bodies.\n\nRationale:\nshould yield 1, not 0\n\nTest: test-art-host test-art-target\nChange-Id: I0ca68b2a5a4dba1c3e41248376002d9635716840\n"
    },
    {
      "commit": "f26bb6c74a973fde3d2783ac35324d5ce8def814",
      "tree": "70149908a20503dfaf1276d04d561024f3441c6f",
      "parents": [
        "66e3af9ce5b3aaa43e5ce3bce8233235af139072"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Sep 01 10:59:03 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Sep 07 21:29:41 2017 +0100"
      },
      "message": "ARM64: Tune SIMD loop unrolling factor heuristic.\n\nImprove SIMD loop unrolling factor heuristic for ARM64 by\naccounting for max desired loop size, trip_count, etc. The\nfollowing example shows 21% perf increase:\n\n  for (int i \u003d 0; i \u003c LENGTH; i++) {\n    bc[i] \u003d ba[i];  // Byte arrays\n  }\n\nTest: test-art-host, test-art-target.\nChange-Id: Ic587759c51aa4354df621ffb1c7ce4ebd798dfc1\n"
    },
    {
      "commit": "b92cc33a7a6a827da577627dc274440ac29652a8",
      "tree": "9fbc71433d4ea89be61aec6de0d33d142c11f039",
      "parents": [
        "f56311a966a9e8e476287cd47d615a91a83c1d04"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 06 15:53:17 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 06 15:53:17 2017 -0700"
      },
      "message": "Pass stats into the loop optimization phase.\n\nTest: market scan.\nChange-Id: I58b23b8d254883f30619ea3602d34bf93618d432\n"
    },
    {
      "commit": "21b859210d690d25563423eeed5fd630023d23cc",
      "tree": "61a28428b0375458d8ed83e42cf7d05ad0976630",
      "parents": [
        "ac8a2a76e34d0ec0bfc10e067eafbd8a87ea4446"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 06 13:29:16 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 06 13:29:16 2017 -0700"
      },
      "message": "Added vectorization stats.\n\nRationale:\nProvides a (somewhat crude) quantative way to detect changes in\nloop vectorization and idiom recognition (e.g. by means of market\nscans, or just inspecting the same application before/after a change).\n\nTest: market scan\nChange-Id: Ic85938ba2b33c967de3159742c60301454a152a0\n"
    },
    {
      "commit": "0148de41a5c77c2f61252c219f1a02413c7c4a32",
      "tree": "91736a82a7e98721a44879b6597b5aea386e8e3b",
      "parents": [
        "c101222c854a0c476f5b6ae64e20adbd38126a3c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Sep 05 09:25:01 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Sep 05 10:20:09 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is  a revert   of Icb5d6c805516db0a1d911c3ede9a246ccef89a22\nand thus a revert^2 of I2454778dd0ef1da915c178c7274e1cf33e271d0f\nand thus a revert^3 of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\nand thus a revert^4 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\n\nPS1-2 shows what needed to change\n\nTest: test-art-host test-art-target\n\nBug: 64091002\nChange-Id: I647889e0da0959ca405b70081b79c7d3c9bcb2e9\n"
    },
    {
      "commit": "982334cef17d47ef2477d88a97203a9587a4b86f",
      "tree": "7e65d03a4533f21286cf68e66696bd0a7a54ef54",
      "parents": [
        "cfa59b49cde265dc5329a7e6956445f9f7a75f15"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Sep 02 12:54:16 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Sep 02 12:54:16 2017 +0000"
      },
      "message": "Revert \"Basic SIMD reduction support.\"\n\nFails 530-checker-lse on arm64.\n\nBug: 64091002, 65212948\n\nThis reverts commit cfa59b49cde265dc5329a7e6956445f9f7a75f15.\n\nChange-Id: Icb5d6c805516db0a1d911c3ede9a246ccef89a22\n"
    },
    {
      "commit": "cfa59b49cde265dc5329a7e6956445f9f7a75f15",
      "tree": "eed953f62e796f7e64252520a40d7e77d1f117af",
      "parents": [
        "82a63734d3067ea0c96f8ba15bc40caaf798c625"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Aug 31 09:08:13 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Sep 01 10:32:50 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is a revert^2 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\nand thus a revert  of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n\nPS1-2 shows what needed to change, with regression tests\n\nTest: test-art-host test-art-target\n\nBug: 64091002, 65212948\nChange-Id: I2454778dd0ef1da915c178c7274e1cf33e271d0f\n"
    },
    {
      "commit": "a57b4ee7b15ce6abfb5fa88c8dc8a516fe40e0d9",
      "tree": "c7ed7e8cb7439a8e689e399e34559aa46a97cdbd",
      "parents": [
        "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 21:21:41 2017 +0000"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 21:21:41 2017 +0000"
      },
      "message": "Revert \"Basic SIMD reduction support.\"\n\nThis reverts commit 9879d0eac8fe2aae19ca6a4a2a83222d6383afc2.\n\nGetting these type check failures in some builds. Need time to look at this better, so reverting for now :-(\n\n\ndex2oatd F 08-30 21:14:29 210122 226218 \ncode_generator.cc:115] Check failed: CheckType(instruction-\u003eGetType(), locations-\u003eInAt(0)) PrimDouble C\n\nChange-Id: I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n"
    },
    {
      "commit": "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2",
      "tree": "c75ab69be15630f86824bb202577eaa1ff91c4ee",
      "parents": [
        "60f734443d54d48fad86dce6d80d8cef22a134d0"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Aug 15 10:51:25 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 09:10:40 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: I7880c135aee3ed0a39da9ae5b468cbf80e613766\n"
    },
    {
      "commit": "671e48a4895cc1a0b7a1458d608f8c4f9b5cf85c",
      "tree": "143dbcf6352af8942ae1c6d253dd6561474b6ecf",
      "parents": [
        "1bd8e5a1b2055e0ff7977ba7e149534d2ee0a696"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 09 13:16:56 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Aug 10 11:00:05 2017 -0700"
      },
      "message": "Fix performance regression.\n\nRationale:\nOne \"improvement\" overlooked in the previous CL hoists\na try-test out of the optimization to make sure we don\u0027t\nchange HIR when not needed. However, the try-test may\naffect the outcome of the test, so that was bad, bad!\n\nBug: 64091002\nTest: test-art-host\nChange-Id: Icf5f73e7cbeb209ee5fa5f6c1bef64fe127bb2fd\n"
    },
    {
      "commit": "b29f684b74216e8d652c48ab9f86cc7d1b327e54",
      "tree": "393839a3b0e3d3aa0fde20beaef846303ce098c7",
      "parents": [
        "bf3710ecec95b2716d1c706b5661192dd9ea6c66"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Jul 28 15:58:41 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Aug 08 11:11:00 2017 -0700"
      },
      "message": "Set basic framework for detecting reductions.\n\nRationale:\nRecognize reductions in loops. Note that reductions are *not*\noptimized yet (we would proceed with e.g. unrolling and vectorization).\nThis CL merely sets up the basic detection framework. Also does\na bit of cleanup on loop optimization code.\n\nBug: 64091002\nTest: test-art-host\n\nChange-Id: I0f52bd7ca69936315b03d02e83da743b8ad0ae72\n"
    },
    {
      "commit": "21c7e6fbcabef2f22b467e1e89f4abe1aa43e459",
      "tree": "1a62fe2485d9642ee3d8768c6edd005278b1014f",
      "parents": [
        "2e53f8f69f8c4175085e337445ec42aa045a2f7f"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Jul 27 16:04:42 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Aug 01 11:35:23 2017 +0100"
      },
      "message": "ART: Fix SimplifyInduction for an instruction with HEnvironment.\n\nAfter an instruction is removed during RemoveFromCycle its\nenvironment isn\u0027t properly cleaned: it still has input instructions\npresent and registered (those instructions still hold records for\nthat).\n\nTest: test-art-target, test-art-host.\nChange-Id: Iea315bdf735d75fe477f43671f05b40dfecc63a8\n"
    },
    {
      "commit": "8cf9cb386cd9286d67e879f1ee501ec00d72a4e1",
      "tree": "88e86e214b425e444760fe4e0ffeee677e1558a2",
      "parents": [
        "914b7b6a6c9f399b26b41e9160e9871ef749e0db"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Jul 19 09:28:38 2017 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Jul 24 16:07:10 2017 -0700"
      },
      "message": "ART: Include cleanup\n\nLet clang-format reorder the header includes.\n\nDerived with:\n\n* .clang-format:\n BasedOnStyle: Google\n IncludeIsMainRegex: \u0027(_test|-inl)?$\u0027\n\n* Steps:\n find . -name \u0027*.cc\u0027 -o -name \u0027*.h\u0027 | xargs sed -i.bak -e \u0027s/^#include/ #include/\u0027 ; git commit -a -m \u0027ART: Include cleanup\u0027\n git-clang-format -style\u003dfile HEAD^\n manual inspection\n git commit -a --amend\n\nTest: mmma art\nChange-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02\n"
    },
    {
      "commit": "51765b098301fff1897361b2d1a21af356d9d6d8",
      "tree": "5d35468c9ecd428803fe7e4339fb8e251b6ed926",
      "parents": [
        "e63a91111d13f33028c2988ded53a4659140ca2e"
      ],
      "author": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Thu Jun 22 13:49:59 2017 +0200"
      },
      "committer": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Thu Jul 13 10:34:27 2017 +0200"
      },
      "message": "MIPS32: ART Vectorizer\n\nMIPS32 implementation which uses MSA extension.\n\nNote: Testing is done with checker parts of tests 640, 645, 646 and\n      651, locally changed to cover MIPS32 cases. These changes can\u0027t\n      be included in this patch since MSA is not a default option.\n\nTest: ./testrunner.py --target --optimizing -j1 in QEMU (mips32r6)\nChange-Id: Ieba28f94c48c943d5444017bede9a5d409149762\n"
    },
    {
      "commit": "e128af51eb0d1a882b9bc37cd213639d0c3a63e7",
      "tree": "cce9394c1892680e9d731df24475fca35decaf59",
      "parents": [
        "dfcf10b92330164f8af6c82c8232e85cfff1ae3c",
        "8f7c41044bdb7a36913444a3437bf2b946f7efe9"
      ],
      "author": {
        "name": "Treehugger Robot",
        "email": "treehugger-gerrit@google.com",
        "time": "Fri Jun 30 18:18:06 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Jun 30 18:18:06 2017 +0000"
      },
      "message": "Merge \"ARM: ART Vectorizer (64-bit vectors).\""
    },
    {
      "commit": "8f7c41044bdb7a36913444a3437bf2b946f7efe9",
      "tree": "cdfcc8dae149617f6270198e15101b329f821ebd",
      "parents": [
        "a4811cd3496eb28295fe61057844c53793f3023e"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jun 21 11:21:37 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Jun 30 11:52:24 2017 +0100"
      },
      "message": "ARM: ART Vectorizer (64-bit vectors).\n\nBasic vectorization support with 64-bit vector length on ARM 32-bit\nplatforms (128-bit vectors require massive changes in register\nallocator).\n\nTest: test-art-target, test-art-host\n\nChange-Id: I1d740146c3f00170fc033ae5fd69d59321ddcbf4\n"
    },
    {
      "commit": "37dc4df47fec811ea52f7180880961565f013434",
      "tree": "eac308a6c7ef8b7d53f64889ff0a93740a2dc62a",
      "parents": [
        "76754cc816af46b41a8d1f419a38334b5db59b6e"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jun 28 14:08:00 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jun 29 11:20:56 2017 -0700"
      },
      "message": "Improved subscript and data dependence analysis.\n\nRationale:\nWe missed vectorizing a simple stencil operation\ndue to inaccurate unit stride analysis and failure\nto detect single runtime data dependence test.\n\nTest: test-art-host, test-art-target\nChange-Id: I07ba03455bfb1c0aff371c1244a1328f885d0916\n"
    },
    {
      "commit": "76754cc816af46b41a8d1f419a38334b5db59b6e",
      "tree": "9a04d4a9811c5f196b29c144875a57818e8815d9",
      "parents": [
        "3dc94c4763ecab28c0053d5d07e332c61a3f781b",
        "f57c1ae3682f95e6d7ce08ae4c241d04b09de658"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jun 28 22:33:32 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Jun 28 22:33:32 2017 +0000"
      },
      "message": "Merge \"Prevent loop optimization in debuggable mode.\""
    },
    {
      "commit": "f57c1ae3682f95e6d7ce08ae4c241d04b09de658",
      "tree": "bf12e0e19626c28edd933fb31c5652e7f974bf1d",
      "parents": [
        "0ca1ae25d33dc8b92d9eecd585657f74cbb313e9"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 28 17:40:18 2017 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 28 21:10:13 2017 +0100"
      },
      "message": "Prevent loop optimization in debuggable mode.\n\nbug: 33775412\nTest: no scanner crash (torn on whether I should spend some time working on a smali test)\n\nChange-Id: I8b94725ce57171b592bede4bf55cd0a9626a8a10\n"
    },
    {
      "commit": "14a68b4aa9620e4fd58907255b049fb5c18bd1ec",
      "tree": "692319b6a9344d84a2e8916c388be954d8878c41",
      "parents": [
        "afdcd847498abc0f4e295bece443afabf8aaf868"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jun 08 14:06:58 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Jun 27 11:29:07 2017 -0700"
      },
      "message": "Unrolling and dynamic loop peeling framework in vectorizer.\n\nRationale:\nThis CL introduces the basic framework for dynamically peeling\n(to obtain aligned access) and unrolling the vector loop (to reduce\nlooping overhead and allow more target specific optimizations\non e.g. SIMD loads and stores).\n\nNOTE:\nThe current heuristics are \"bogus\" and merely meant to exercise\nthe new framework. This CL focuses on introducing correct code for\nthe vectorizer. Heuristics and the memory computations for alignment\nare to be implemented later.\n\nTest: test-art-target, test-art-host\n\nChange-Id: I010af1475f42f92fd1daa6a967d7a85922beace8\n"
    },
    {
      "commit": "1a0a519c82044ec3e6d3910ff0602b11292de47a",
      "tree": "342691a82a58ddb0660b9111622b2ff67d92f898",
      "parents": [
        "8979f71079ec18fa8d3c0915549ec03ee1fbadf5"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 22 11:56:01 2017 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 22 12:09:16 2017 +0100"
      },
      "message": "Fix loop optimization in the presence of environment uses.\n\nWe should not remove instructions that have deoptimize as\nusers, or that have environment uses in a debuggable setup.\n\nbug: 62536525\nbug: 33775412\nTest: 656-loop-deopt\nChange-Id: Iaec1a0b6e90c6a0169f18c6985f00fd8baf2dece\n"
    },
    {
      "commit": "13600e9cd7536b7cd8d93c32270f5f08076f5d6d",
      "tree": "3cedd3b9538afb1a7213fea02210c0e7dea6d76d",
      "parents": [
        "a74c04b3c797265ab7923d3690da6166224f3e30",
        "8fea1e18ecce190bbffbc0085f20ad49ca10a8c2"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Jun 09 21:28:37 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Jun 09 21:28:39 2017 +0000"
      },
      "message": "Merge \"MIPS64: Min/max vectorization support\""
    },
    {
      "commit": "f45d61c0866461c9476f17644b27dc0664d507c5",
      "tree": "95d2837a03d451cccd82cad61924980beb5fd0d4",
      "parents": [
        "83b140474aa1759739c8ee4464bf226c4fa0f6d7"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Jun 07 10:29:33 2017 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Jun 08 17:19:51 2017 -0700"
      },
      "message": "ART: Fix or disable some tidy warnings.\n\nAdd a strlcpy shim for the host, so we can use strlcpy instead of\nstrcpy everywhere.\n\nFixed warnings include unused-decls, (some) unreachable code, use\nafter std::move, string char append, leaks, (some) excessive padding.\n\nDisable some warnings we cannot or do not want to avoid.\n\nBug: 32619234\nTest: m\nTest: m test-art-host\nChange-Id: Ie191985eebb160d94b988b41735d4f0a1fa1b54e\n"
    },
    {
      "commit": "8fea1e18ecce190bbffbc0085f20ad49ca10a8c2",
      "tree": "e026d33cc0928a977118faff46fdbbb50ff0967e",
      "parents": [
        "11d72c608e0565fabcf6b2d6c13fbc85c560a608"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Tue Jun 06 13:28:42 2017 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Wed Jun 07 09:45:18 2017 +0200"
      },
      "message": "MIPS64: Min/max vectorization support\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target --64 in QEMU\n\nChange-Id: I60dc9c97c2b6470414fa64750e7c9824e70bfb4e\n"
    },
    {
      "commit": "6e92fb33dea9846ad03bd538d02d055fa96f5240",
      "tree": "91c359d459a99f2c7f847c2e4d73a28a681612f7",
      "parents": [
        "81c769436a89b25c781eb2da882f11fd8d11f84d"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Jun 05 14:05:09 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Jun 05 14:05:09 2017 -0700"
      },
      "message": "Pass through inputs beyond arguments in invoke.\n\nRationale:\nRefinement requested by vmarko.\n\nTest: test-art-host\nChange-Id: I850466ebd5ad99bb617bc71c279159862e18e6ec\n"
    },
    {
      "commit": "19680d3655433e98582983ed0a6d44d6b4822951",
      "tree": "15113506e75b1480c5c1d3cfdf9df4480f30eae8",
      "parents": [
        "0a5ace58e973da278049f837bf2cdbaf7b44849c"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Thu May 11 10:38:36 2017 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Mon May 29 17:57:39 2017 +0200"
      },
      "message": "MIPS64: ART Vectorizer\n\nMIPS64 implementation which uses MSA extension. Also extended all\nrelevant checker tests to test MIPS64 implementation.\n\nTest: booted MIPS64R6 in QEMU\nTest: ./testrunner.py --target --optimizing -j1 in QEMU\n\nChange-Id: I8b8a2f601076bca1925e21213db8ed1d41d79b52\n"
    },
    {
      "commit": "304c8a5dfe92d5677e9561270b19313d3e450c59",
      "tree": "a5345d8d3467dde5f509dcc5dd0b3b170b021e60",
      "parents": [
        "14538fb50832ac20445af5a92003bc250f486c22"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue May 23 11:01:13 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed May 24 15:56:14 2017 +0000"
      },
      "message": "Support for narrow operands in \"dangerous\" operations.\n\nThis is a revert^2 of commit 636e870d55c1739e2318c2180fac349683dbfa97.\n\nRationale:\nUnder strict conditions, even operations that are sensitive\nto higher order bits can vectorize by inspecting the operands\ncarefully. This enables more vectorization, as demonstrated\nby the removal of quite a few TODOs.\n\nTest: test-art-target, test-art-host\nChange-Id: Ic2684f771d2e36df10432286198533284acaf472\n"
    },
    {
      "commit": "9231690d586ecf45d5d9481bc5df5a5ad2628c89",
      "tree": "d48bf8b22461f6488821be6117ff2da4cc176093",
      "parents": [
        "636e870d55c1739e2318c2180fac349683dbfa97"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue May 23 08:06:07 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue May 23 08:06:07 2017 +0000"
      },
      "message": "Revert \"Support for narrow operands in \"dangerous\" operations.\"\n\nFails on armv8 / speed-profile\n\nThis reverts commit 636e870d55c1739e2318c2180fac349683dbfa97.\n\nChange-Id: Ib2a09b3adeba994c6b095672a1e08b32d3871872\n"
    },
    {
      "commit": "636e870d55c1739e2318c2180fac349683dbfa97",
      "tree": "6c726b0b918e26aba5b5f9ec1bc900045ef2c3e3",
      "parents": [
        "de31d084f7d64c94911aef927798559d39759f95"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu May 18 14:45:27 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu May 18 17:18:24 2017 -0700"
      },
      "message": "Support for narrow operands in \"dangerous\" operations.\n\nRationale:\nUnder strict conditions, even operations that are sensitive\nto higher order bits can vectorize by inspecting the operands\ncarefully. This enables more vectorization, as demonstrated\nby the removal of quite a few TODOs.\n\nTest: test-art-target, test-art-host\nChange-Id: I2b0fda6a182da9aed9ce1708a53eaf0b7e1c9146\n"
    },
    {
      "commit": "5f80500bba3df590f0bfffea2ebe2adee7c40763",
      "tree": "ed18a25cc6dd29acea8641069295d81c3390d88d",
      "parents": [
        "536e54a6af85127d7f17037360deb08e0a7dc4eb"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue May 16 16:42:41 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu May 18 09:30:36 2017 -0700"
      },
      "message": "Made idiom recognition more robust.\n\nRationale:\nRecognition is now more robust with respect to\noperation order or even cancelling constants.\n\nTest: test-art-target, test-art-host\nChange-Id: I4e920150e20e1453bb081e3f0ddcda8f1c605672\n"
    },
    {
      "commit": "c8e93c736c149ce41be073dd24324fb08afb9ae4",
      "tree": "8e7154cf1bbcee8f5837ee9cb930174e2516ac03",
      "parents": [
        "92f4672f811a4eccdc596f7c2235804abd196fde"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@ajcbik2.mtv.corp.google.com",
        "time": "Wed May 10 10:49:22 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 15 11:44:58 2017 -0700"
      },
      "message": "Min/max SIMDization support.\n\nRationale:\nThe more vectorized, the better!\n\nTest: test-art-target, test-art-host\n\nChange-Id: I758becca5beaa5b97fab2ab70f2e00cb53458703\n"
    },
    {
      "commit": "50e20d54670aecf1a4fdcf37ef1606d5ca990559",
      "tree": "cb61312693cd392c3f9a569153a55c3eef936714",
      "parents": [
        "e22445fba0e5747ea787429ac64577a9a62aded3"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri May 05 14:07:29 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue May 09 10:41:39 2017 -0700"
      },
      "message": "Moved knowledge on masking shift operands to simplifier.\n\nRationale:\nIt is better to have a single place that simplifies shift\nfactors outside the 32-bit or 64-bit distance range, so\nthat other phases (induction variable analysis, loop optimizations,\netc.) do not have to know about that.\n\nTest: test-art-target, test-art-host\nChange-Id: Idfd90259cca085426cc3055eccb90f3c0976036b\n"
    },
    {
      "commit": "65ffd8ef044465c47d4f97ab2556310f9ee30a01",
      "tree": "b520b0071f80d6c6f9c4cc649a079969ef3e0d20",
      "parents": [
        "c009d14ce52bca0de34b441f8a575b0d36c1d69e"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 01 16:50:45 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 01 16:50:45 2017 -0700"
      },
      "message": "Bug fix on shift that exceeds \"lane width\".\n\nRationale:\nARM is a bit less forgiving on shifting more than\nthe lane width of the SIMD instruction (rejecting\nsuch cases is no loss, since it yields 0 anyway\nand should be optimized differently).\n\nBug: 37776122\nTest: test-art-target, test-art-host\nChange-Id: I22d04afbfce82b4593f17c2f48c1fd5a0805d305\n"
    },
    {
      "commit": "472821b210a7fc7a4d2e3d45762c7b5b9628a35b",
      "tree": "d3dad427cdfcf4ebe8d324bcd3b7618ed42d14dd",
      "parents": [
        "70940dfe99df0084a3f3fed1a88255ec976a60e3"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 27 17:23:51 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 28 09:49:26 2017 -0700"
      },
      "message": "Enable string \"array get\" vectorization.\n\nRationale:\nLike its scalar counterpart, the SIMD implementation of array get from\na string needs to deal with compressed and uncompressed cases.\nMicro benchmarks shows 2x to 3x speedup for just copying data!\n\nTest: test-art-target, test-art-host\nChange-Id: I2fd714e50715b263123c215cd181f19194456d2b\n"
    },
    {
      "commit": "db14fcf45effb7dd4b3febd697ff5f0541119835",
      "tree": "4197a7be031e7206b1c4f55a51821e9b273b1b36",
      "parents": [
        "06660db82d6b3d59080584431addf3797a468a70"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 25 15:53:58 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 25 16:13:55 2017 -0700"
      },
      "message": "Pack booleans in the already existing bit field.\n\nAlso adds is_string_char_at boolean in preparation of\n[un]compressed string vectorization support.\n\nTest: test-art-target, test-art-host\nChange-Id: Ia99b28564727bf91b3d5cfc49f6d40a4dd1ffd3b\n"
    },
    {
      "commit": "f3e61ee363fe7f82ef56704f06d753e2034a67dd",
      "tree": "a00f1fce4a2e284b0a03f941f530afc5b5c56b59",
      "parents": [
        "741a81af441cbcb7255229bf250bc009d2894e92"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 12 17:09:20 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 19 10:30:57 2017 -0700"
      },
      "message": "Implement halving add idiom (with checker tests).\n\nRationale:\nFirst of several idioms that map to very efficient SIMD instructions.\nNote that the is-zero-ext and is-sign-ext are general-purpose utilities\nthat will be widely used in the vectorizer to detect low precision\nidioms, so expect that code to be shared with many CLs to come.\n\nTest: test-art-host, test-art-target\nChange-Id: If7dc2926c72a2e4b5cea15c44ef68cf5503e9be9\n"
    },
    {
      "commit": "27fb1dc467effbd8df43e6207743fdb7bcee4044",
      "tree": "8fbac3e292fe9cdb0f30e28a1bc9007d503827cf",
      "parents": [
        "35fc819cd95fbd25eef5d729b81976987a8c6c7d",
        "d86c08555905dbc42233a506683e3995446fc113"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Apr 17 16:34:52 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Apr 17 16:34:54 2017 +0000"
      },
      "message": "Merge \"Fixed bug on pending environment use of termination condition. With regression test.\""
    },
    {
      "commit": "d86c08555905dbc42233a506683e3995446fc113",
      "tree": "1cc9187dbbcd9b8082b1ffc8a063094303945321",
      "parents": [
        "66e226ac2fb525c7a7cbbb21a9cbbe347f531a1c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 14 12:00:15 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 14 12:00:15 2017 -0700"
      },
      "message": "Fixed bug on pending environment use of termination condition.\nWith regression test.\n\nTest: test-art-host\nBug: 37247891\nChange-Id: I55b06939d465d3ddb736d1ba659b1df179a5c390\n"
    },
    {
      "commit": "4766f2cd27c3de80eb74c302a9eb4cc7c97e5de1",
      "tree": "3d48ecee6d98502c25fba27e854c89ae02e169b7",
      "parents": [
        "279fbab663f3d9f58047fd57197a710e08e4c693",
        "b31f91fd1811c9047591282dd003cf22b54938a1"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 12 15:52:08 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Apr 12 15:52:08 2017 +0000"
      },
      "message": "Merge changes I1d4db176,Ifb931a99\n\n* changes:\n  ARM64: Support vectorization for double and long.\n  ARM64: Support 128-bit registers for SIMD.\n"
    },
    {
      "commit": "3101e58114b21876f77940d716385c54f697761b",
      "tree": "d0435faf4d2763e24b45fe402aa2155b7d450788",
      "parents": [
        "921c5f9479c83bd1f046213377faf1d2be14e26b"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 11 10:15:44 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 11 10:58:04 2017 -0700"
      },
      "message": "Fix bug in vectorization of charAt, with regression test\n\nRationale:\nString array get instruction cannot be vectorized\nin a straightforward way, since compression has\nto be dealt with. So rejected for now.\n\nTest: test-art-target, test-art-host\nBug: 37151445\nChange-Id: I16112cb8b1be30babd8ec07af5976db0369f8c28\n"
    },
    {
      "commit": "9899026fcba9bb57dc8adac5df3f5069782eb418",
      "tree": "351ac2735f708b062a65da8bf99a11560280f5bc",
      "parents": [
        "8aaa601d88660d4653d64ea822197e72a43bf768"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Apr 10 13:15:57 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Apr 10 23:51:49 2017 +0000"
      },
      "message": "Add checker part of test, fix intrinsic copying\n\nRationale:\nI forgot to add the check test part of this test,\nand incidentally found an omission: intrinsic\ninformation should be set in the scalar loop\n(to get best code there too, not just a lib call).\n\nTest: test-art-host, test-art-target\nChange-Id: I94aa4cdf042f72690d10efee3a9dc7c476d5c5e0\n"
    },
    {
      "commit": "b31f91fd1811c9047591282dd003cf22b54938a1",
      "tree": "4178afdf3b28f00aa986a5f8392114352fffa87d",
      "parents": [
        "d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Apr 05 11:31:19 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 14:53:24 2017 +0100"
      },
      "message": "ARM64: Support vectorization for double and long.\n\nTest: test-art-host, test-art-target\nChange-Id: I1d4db1763b64737766f9756e5d0f85c5736e3522\n"
    },
    {
      "commit": "d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331",
      "tree": "2890740d9cab3eee2be223666f528c6707b89f90",
      "parents": [
        "903b8169074c01590ab3f5ad9190d9c7e3fe795b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 03 18:47:32 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 11:43:33 2017 +0100"
      },
      "message": "ARM64: Support 128-bit registers for SIMD.\n\nTest: test-art-host, test-art-target\n\nChange-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa\n"
    },
    {
      "commit": "fa76296bc624bc2c879167c260ad6925238efb3d",
      "tree": "045c4488fec66806982a62aa4cfd7d3a2183e958",
      "parents": [
        "6f005931d0a0db65128db803df38d59d205dd218"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 07 11:33:37 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 07 23:03:42 2017 +0000"
      },
      "message": "Fixed missing context while detecting unit strides.\n\nWith regression test (found by fuzz testing).\n\nBug: 37033123\nTest: test-art-target\nChange-Id: Id738b2a3a353985c3d0bf3beeb581a31f1fcbc3f\n"
    },
    {
      "commit": "24b905f4c4b3fd6eff6ba55e33ed4f81073e5327",
      "tree": "93e03e0c84976f84072fbc2f78a284183515af58",
      "parents": [
        "6bca1c6389bb002d44f1c0cabf7641de8c935c4b"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 06 09:59:06 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 06 10:11:40 2017 -0700"
      },
      "message": "Fix a few comments in vectorization code that were incorrect or incomplete.\n\nTest: test-art-target\nChange-Id: I7c6a5a2d29edd0b2782abc303d8d8cb09c1c2f91\n"
    },
    {
      "commit": "6bca1c6389bb002d44f1c0cabf7641de8c935c4b",
      "tree": "b06aba0e2b2c8e183b6ccc76497483110904abe5",
      "parents": [
        "30b262c298fe7bd08f28d2f0f23a97cb1a1eb2fe",
        "b07d1bcf055d3eb8c6b4c45b359ad8ef30909af7"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 06 00:02:23 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 06 00:02:23 2017 +0000"
      },
      "message": "Merge \"Ensure environment is ready when populating loop.\""
    },
    {
      "commit": "b07d1bcf055d3eb8c6b4c45b359ad8ef30909af7",
      "tree": "e925d6df31a3da17757c5d3f1b4f32c341847ce5",
      "parents": [
        "f6e11e9e218e5e70463b5b3a94c89309936601d7"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 05 10:03:15 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 05 10:03:15 2017 -0700"
      },
      "message": "Ensure environment is ready when populating loop.\n\nRationale:\nOSR requires the suspend check to already have an environment,\nalbeit just for testing irreducible loops. This CL fixes the\nomission. Note, the error is spurious on OSR and writing a\nunit or regression test for this is hard.\n\nTest: test-art-host\nBug: 36950873\nChange-Id: Ica89e18e10deb438dead79e2cc40dd00a60b529f\n"
    },
    {
      "commit": "6daebeba6ceab4e7dff5a3d65929eeac9a334004",
      "tree": "6aa2948896c6a731531451840a9a8bb26854cdd8",
      "parents": [
        "7cd18fb5a7ce83d98b1bbc3c55583fc5f93dc16f"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Apr 03 14:35:41 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 05 09:24:01 2017 -0700"
      },
      "message": "Implemented ABS vectorization.\n\nRationale:\nThis CL adds the concept of vectorizing intrinsics\nto the ART vectorizer. More can follow (MIN, MAX, etc).\n\nTest: test-art-host, test-art-target (angler)\nChange-Id: Ieed8aa83ec64c1250ac0578570249cce338b5d36\n"
    },
    {
      "commit": "f8f5a16ed7bad1e18179e38453e59c96a944de10",
      "tree": "53369083a97103563467cc5910a439a1864dd0b1",
      "parents": [
        "7298b1ae3e9af5fdb46d168302a26cfbf5d475f5"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Feb 06 15:35:29 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Mar 31 10:58:11 2017 -0700"
      },
      "message": "ART vectorizer.\n\nRationale:\nMake SIMD great again with a retargetable and easily extendable vectorizer.\n\nProvides a full x86/x86_64 and a proof-of-concept ARM implementation. Sample\nimprovement (without any perf tuning yet) for Linpack on x86 is about 20% to 50%.\n\nTest: test-art-host, test-art-target (angler)\nBug: 34083438, 30933338\n\nChange-Id: Ifb77a0f25f690a87cd65bf3d5e9f6be7ea71d6c1\n"
    },
    {
      "commit": "caa348cee1312150a957bd308ce77ad406f3eb64",
      "tree": "575f0b062f8adb1b8fc7ebc5f6ef18bea5ae1db7",
      "parents": [
        "c02fe5f31d487765a8c59922c46d459ba6ebf939",
        "01b47b046b01ec68696f8ff61b5326cdd3af348e"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Mar 08 20:29:49 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Mar 08 20:29:51 2017 +0000"
      },
      "message": "Merge \"Inlining a few small methods based on profiling dex2oat with perf.\""
    },
    {
      "commit": "01b47b046b01ec68696f8ff61b5326cdd3af348e",
      "tree": "e526306fc89bf6fb04ff914e24343dde0369e98c",
      "parents": [
        "dcab11d06860ae1e23d03926adb6c31f75404032"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Fri Feb 03 12:09:57 2017 -0800"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Mar 08 10:15:06 2017 -0800"
      },
      "message": "Inlining a few small methods based on profiling dex2oat with perf.\n\nTest: m test-art-host\nChange-Id: I6313158e59592d8d132154523be9c82dda3c7eb8\n"
    },
    {
      "commit": "92685a8a56fba7191612cf210f9c667b5ceda2af",
      "tree": "563009abe4387cb83c63320504148cedfc764bc3",
      "parents": [
        "5c90d0b0f332436f7ca5c028256bf5e91e9023d4"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Mar 06 11:13:43 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Mar 06 15:20:04 2017 -0800"
      },
      "message": "Pass driver to loop opt. Add new side_effects phase.\n\nRationale:\nBreak-out CL of ART Vectorizer: number 3.\nThe purpose is making the original CL smaller\nand easier to review.\n\nBug: 34083438\nTest: test-art-host\nChange-Id: I7cece807ee4f5fcaeae41f1deed33ac263447b77\n"
    },
    {
      "commit": "69d75ffac23fe1e655b7e81f0454c2841280dc1f",
      "tree": "88432364dd096bdd5674f48fb26e77f08cbf0dc6",
      "parents": [
        "d8a16ba050978e4fe1447089002040a0047a5b3a"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Tue Feb 07 13:06:06 2017 -0800"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Fri Feb 17 12:21:46 2017 -0800"
      },
      "message": "Skip loop optimization if there is no loop in the graph.\n\nLinearizeGraph() does quite some allocations.\nAlso add some comments on the possible false positives of\nsome flags.\n\nTest: m test-art-host\nChange-Id: I80ef89a2dc031d601e7621d0b22060cd8c17fae3\n"
    },
    {
      "commit": "6b69e0acb0e4c506ce2587e362c38e36e41e34ab",
      "tree": "976f08c78d3c5efa2dac8ec0409f36fae51456cb",
      "parents": [
        "93939824c7e6e16cf98941cd4724278e87d6259d"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jan 11 10:20:43 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Jan 13 10:04:42 2017 -0800"
      },
      "message": "Complete unrolling of loops with small body and trip count one.\n\nRationale:\nAvoids the unnecessary loop control overhead, suspend check,\nand exposes more opportunities for constant folding in the\nresulting loop body. Fully unrolls loop in execute() of\nthe Dhrystone benchmark (3% to 8% improvements).\n\nTest: test-art-host\n\nChange-Id: If30f38caea9e9f87a929df041dfb7ed1c227aba3\n"
    },
    {
      "commit": "df7822ecf033cecf48d950f3ae34f7043c8df738",
      "tree": "f392a69377e1e281bcd85d811b656c6d14280ab4",
      "parents": [
        "6746874b84a44ab8dff18457eec546a1ebb22e93"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Dec 06 10:05:30 2016 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Dec 09 08:42:18 2016 -0800"
      },
      "message": "Added polynomial induction variables analysis. With tests.\n\nRationale:\nInformation on polynomial sequences is nice to further enhance\nBCE and last-value assignment. In this case, this CL enables more\nloop optimizations for benchpress\u0027 Sum (80 x speedup). Also\nchanged rem-based geometric induction to wrap-around induction.\n\nTest: test-art-host\n\nChange-Id: Ie4d2659edefb814edda2c971c1f70ba400c31111\n"
    },
    {
      "commit": "807868eac75a39e79ee6309ed4cbe038407efa29",
      "tree": "74d9953120599bde842895ab4e7ed33fefb0fa13",
      "parents": [
        "3387b2a9e6ca4e7015c4182eee2f70a746972ca2"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Nov 03 17:51:43 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Nov 04 08:14:23 2016 -0700"
      },
      "message": "Account for early exit loop.\n\nRationale:\nlast value computation is obviously only right if\nthe loop does not have early exits; only needed\nif cycle leaks to outside loop in any way.\n\nBug:32633772\nTest: 623-checker-loop-regressions\nChange-Id: Id60beca4704491cff611ad12a24bfc63c09d32c3\n"
    },
    {
      "commit": "e3dedc5e846d1ea19f7a749214be32eaa04b588a",
      "tree": "669640df7f60f8c7f3e1a1caebd26d910840c067",
      "parents": [
        "4b2cdf8608c36fbf4304065cd17328cf1e99b49b"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Nov 02 17:50:27 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Nov 03 13:46:51 2016 -0700"
      },
      "message": "More loop-body simplifications.\n\nRationale:\nThis removes all dead induction from the CaffeineLogic loop,\ngiving yet the next performance boost  (2700us-\u003e1700us).\nAlso, the runtime is now the same between a DX compiled\nand JACK compiled version, giving confidence that all\nrecent introduced optimizations are generally useful\nand something expected from any optimizing compiler.\nLast, less realistic improvement will pale anything\nseen so far, since it removes the full loop (still TBD).\n\nTest: test-art-host\nChange-Id: Id6b89f74b7d009616821dca195200933cc0eaaf2\n"
    },
    {
      "commit": "cc42be074ed15235426cdbcb34f357ead2be2caf",
      "tree": "d0ac4dca432e1bb26e21634f21ffc3e05db5020e",
      "parents": [
        "a8188191477b7b5b01a3c4426c51c48cd55f6678"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Oct 20 16:14:16 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Oct 24 12:55:48 2016 -0700"
      },
      "message": "Improved induction variable analysis and loop optimizations.\n\nRationale:\nRather than half-baked reconstructing cycles during loop optimizations,\nthis CL passes the SCC computed during induction variable analysis\nto the loop optimizer (trading some memory for more optimizations).\nThis further improves CaffeineLogic from 6000us down to 4200us (dx)\nand 2200us to 1690us (jack). Note that this is on top of prior\nimprovements in previous CLs. Also, some narrowing type concerns\nare taken care of during transfer operations.\n\nTest: test-art-host\nChange-Id: Ice2764811a70073c5014b3a05fb51f39fd2f4c3c\n"
    },
    {
      "commit": "639cc8c7bbb7d8c341173bcf24604ccb4328acb8",
      "tree": "ae8181b94ddd145edaff141a2b351478161f1559",
      "parents": [
        "3941c882ea7b54772dec36a9a1b33e0b8a7474f7"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Oct 18 13:03:31 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Oct 20 14:14:17 2016 -0700"
      },
      "message": "Improve recognition of select-based period induction.\n\nRationale:\nSimilar to the previous CL, this helps to eliminate more dead induction.\nNow, CaffeineLogic, when compiled with dx (rather than jack) improves\nby a 1.5 speedup (9000us -\u003e 6000us).\n\nNote:\nWe need to run the simplifier before induction analysis to trigger\nthe select simplification first. Although a bit of a compile-time hit,\nit seems a good idea to run a simplifier here again anyway.\n\nTest: test-art-host\nChange-Id: I93b91ca40a4d64385c64393028e8d213f0c904a8\n"
    },
    {
      "commit": "9abf894ad0e5a6a1594ee1fa3924965e25e5f86f",
      "tree": "5080bd832d4f2234897404195b5d9865f950f47c",
      "parents": [
        "6e5fa09510c7280168e040382d27dd8b55760d9a"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Oct 14 09:49:42 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Oct 18 09:02:47 2016 -0700"
      },
      "message": "Enable last value generation of periodic sequence.\n\nRationale:\nThis helps to eliminate more dead induction. For example,\nCaffeineLogic when compiled with latest Jack improves with\na 1.3 speedup (2900us -\u003e 2200us) due to eliminating first\nloop (second loop can be removed also, but for a later\ncase). The currently benchmarks.dex has a different construct\nfor the periodics, however, still to be recognized.\n\nTest: test-art-host\nChange-Id: Ia81649a207a2b1f03ead0855436862ed4e4f45e0\n"
    },
    {
      "commit": "482095d3a03892b76f5b835c9e7ea4bc80638501",
      "tree": "642cb6b52f68e4e6d03475e80dc2845c5e4f50f6",
      "parents": [
        "0d7398fd5407938aba75c50bd323af27e83ccb9f"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Oct 10 15:39:10 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Oct 11 10:39:42 2016 -0700"
      },
      "message": "Improved and simplified loop optimizations.\n\nRationale:\nEmpty preheader simplification has been simplified\nto a much more general empty block removal optimization\nstep. Incremental updating of induction variable\nanalysis enables repeated elimination or simplification\nof induction cycles.\n\nThis enabled an extra layer of optimization for\ne.g. Benchpress Loop (17.5us. -\u003e 0.24us. -\u003e 0.08us).\nSo the original 73x speedup is now multiplied\nby another 3x, for a total of about 218x.\n\nTest: 618-checker-induction et al.\nChange-Id: I394699981481cdd5357e0531bce88cd48bd32879\n"
    },
    {
      "commit": "8c4a8542ff5f899f430a65feaa114d6288077224",
      "tree": "8582d2cbab0dcab323b984caa164f4c3bc65613d",
      "parents": [
        "78c6fefdb9008cb6dc9f0014d4616b457009c6c8"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Oct 06 11:36:57 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Oct 07 08:16:16 2016 -0700"
      },
      "message": "Improved and simplified loop optimizations.\n\nRationale:\nThis CL merges some common cases into one, thereby simplifying\nthe code quite a bit. It also prepares for more general induction\ncycles (rather than the simple phi-add currently used). Finally,\nit generalizes the closed form elimination with empty loops.\nAs a result of the latter, elaborate but weird code like:\n\n  private static int waterFall() {\n    int i \u003d 0;\n    for (; i \u003c 10; i++);\n    for (; i \u003c 20; i++);\n    for (; i \u003c 30; i++);\n    for (; i \u003c 40; i++);\n    for (; i \u003c 50; i++);\n    return i;\n  }\n\nnow becomes just this (on x86)!\n\n    mov eax, 50\n    ret\n\nChange-Id: I8d22ce63ce9696918f57bb90f64d9a9303a4791d\nTest: m test-art-host\n"
    },
    {
      "commit": "9620230700d4b451097c2163faa70627c9d8088a",
      "tree": "695b96b9efeaa4c2cb3816e51904e19540fe3883",
      "parents": [
        "4aa6a93c46a959df1ab71ee7a68ad345338046ef"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Oct 04 17:33:56 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Oct 05 11:50:42 2016 -0700"
      },
      "message": "Refactoring of graph linearization and linear order.\n\nRationale:\nOwnership of graph\u0027s linear order and iterators was\na bit unclear now that other phases are using it.\nNew approach allows phases to compute their own\norder, while ssa_liveness is sole owner for graph\n(since it is not mutated afterwards).\n\nAlso shortens lifetime of loop\u0027s arena.\n\nTest: test-art-host\nChange-Id: Ib7137d1203a1e0a12db49868f4117d48a4277f30\n"
    },
    {
      "commit": "5ed20f90acd05e1f8697340f11113f0c61c22492",
      "tree": "470b26b33054a2398bdf115f6592777b1b7698bd",
      "parents": [
        "d3a9ce9d30a59587413310e66ea51c8f7adb0a1d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 05 13:49:44 2016 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 05 13:49:44 2016 +0100"
      },
      "message": "Make it possible to pass an arena allocator to HLoopOptimization.\n\nloop_optimization_test uses memory from HLoopOptimization\u0027s\nallocator, which is scoped by the Run method.\n\nFix is to pass custom allocator.\n\ntest: m test-art-host-gtest\nChange-Id: I359330e22202519f400a26da5403eeb00f0b2db4\n"
    },
    {
      "commit": "ebe167422f6197b9df0698bbeb944a0e4eea5f2d",
      "tree": "60bb0084030cadfed694261c36c5722f4f945869",
      "parents": [
        "2a5c5160771ad528bc9b3ac36ac5785a184c956d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 05 09:55:42 2016 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 05 09:55:42 2016 +0100"
      },
      "message": "Properly scope HLoopOptimization\u0027s allocator.\n\nHOptimization classes do not get their destructor called,\nas they are arena objects. So the scope for the optimization\nallocator needs to be the Run method.\n\nAlso anticipate bisection search breakage by adding\nHLoopOptimization to the list of recognized optimizations.\n\nChange-Id: I7770989c39d5700a3b6b0a20af5d4b874dfde111\n"
    },
    {
      "commit": "281c681a0852c10f5ca99b351650b244e878aea3",
      "tree": "33036cbfb76ee497eedf60e0e5785a2267c9dd02",
      "parents": [
        "a845d07bbd57f8beaea8b4fb47192a3382ef25b2"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Aug 26 11:31:48 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Oct 03 15:15:27 2016 -0700"
      },
      "message": "A first implementation of a loop optimization framework.\n\nRationale:\nWe are planning to add more and more loop related optimizations\nand this framework provides the basis to do so. For starters,\nthe framework optimizes dead induction, induction that can be\nreplaced with a simpler closed-form, and eliminates dead loops\ncompletely (either pre-existing or as a result of induction\nremoval).\n\nSpeedup on e.g. Benchpress Loop is 73x (17.5us. -\u003e 0.24us.)\n[with the potential for more exploiting outer loop too]\n\nTest: 618-checker-induction et al.\n\nChange-Id: If80a809acf943539bf6726b0030dcabd50c9babc\n"
    }
  ]
}