)]}' { "log": [ { "commit": "31b12e32073f458950e96d0d1b44e48508cf67e4", "tree": "b6f818dfa6b45342d6b69283c10e1db9817b8b0e", "parents": [ "038cb84f792501ae01561fe5ea4e8144f1918b7e" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Sep 02 17:11:57 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Sep 07 10:13:48 2016 -0700" }, "message": "Avoid read barrier for image HLoadClass\n\nConcurrent copying baker:\n\nX86_64 core-optimizing-pic.oat: 28583112 -\u003e 27906824 (2.4% smaller)\n\nAround 0.4% of 2.4% is from re-enabling kBootImageLinkTimeAddress,\nkBootImageLinkTimePcRelative, and kBootImageAddress.\n\nN6P boot.oat 32: 73042140 -\u003e 71891956 (1.57% smaller)\nN6P boot.oat 64: 83831608 -\u003e 82531456 (1.55% smaller)\n\nEAAC: 1252 -\u003e 1245 (32 samples)\n\nBug: 29516974\n\nTest: test-art-host CC baker, N6P booting\n\nChange-Id: I9a196cf0157058836981c43c93872e9f0c4919aa\n" }, { "commit": "ba45db072c48783e19a2a73ab4e45ae143c1c7c9", "tree": "d17d8f846f6960195e20143f25f84f776f92dc37", "parents": [ "081e7a16c4fcbdb014441a236e12f58eb89ff99a" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Tue Jul 12 22:53:02 2016 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Aug 31 17:22:49 2016 +0100" }, "message": "Extend the InvokeRuntime() changes to x86 and x86_64.\n\nAlso fix the LocationSummary for intrinsics that call on main\nand slowpath.\n\nTest: test-art-host\n\nChange-Id: I437ffd433ee87b1754dbd8c075ec54f00d7d4ccb\n" }, { "commit": "953437bd51059801d92079295f728d0260efca31", "tree": "b52816b5092a143361ea3878ef0e06d311c4a56f", "parents": [ "c67d22ac6db73aaa9540294c86344bf8021495b3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 08:30:46 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 13:20:32 2016 +0100" }, "message": "Revert \"Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\"\n\nFixed the fault handler recognizing the TEST instruction and\nfault address within the lock word. Added tests to 439-npe.\n\nBug: 29966877\nBug: 12687968\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\n\nThis reverts commit ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15.\n\nChange-Id: I8990def5f719c9205bf6e5fdba32027fa82bec50\n" }, { "commit": "ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15", "tree": "8e271269eb0f3e40388311478fe441bfeb47ab47", "parents": [ "ccf06d8f19a37432de4a3b768747090adfbd18ec" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "message": "Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\n\nFault handler does not recognize the instruction\n F6 /0 ib TEST r/m8, imm8\nso we get crashes instead of NPEs.\n\nBug: 29966877\nBug: 12687968\n\nThis reverts commit ccf06d8f19a37432de4a3b768747090adfbd18ec.\n\nChange-Id: Ib7db3b59f44c0d3ed5e24a20b6c6ee596a89d709\n" }, { "commit": "ccf06d8f19a37432de4a3b768747090adfbd18ec", "tree": "fcb3ba46184db6882e695cecf1cfe495417593ae", "parents": [ "cf834d00de838272cf28f2382ffc26fe716aae5c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 12 13:37:55 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 11:41:44 2016 +0100" }, "message": "x86/x86-64: Avoid temporary for read barrier field load.\n\nAdd TEST instructions for memory and immediate. Use the byte\nversion to avoid a temporary in read barrier field load.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\nBug: 29966877\nBug: 12687968\nChange-Id: Ia415d3c2e1ae1ff6dff11d72bbb7d96d5deed6ee\n" }, { "commit": "0b671c0408e98824e1f92b1ee951b210c090fe7a", "tree": "0bc58c031cd899aa856677fe8c9ffa376228806f", "parents": [ "36bf3a2d281892e7906d3eaf9d7455b0656c9a25" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 12:02:34 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 16:00:09 2016 +0100" }, "message": "Add support for Baker read barriers in SystemArrayCopy intrinsics.\n\nBenchmarks (ARM64) score variations on Nexus 5X with CPU\ncores clamped at 960000 Hz (aosp_bullhead-userdebug build):\n- Ritzperf - average (lower is better): -3.03% (slightly better)\n- CaffeineMark - average (higher is better): +1.26% (slightly better)\n- DeltaBlue (lower is better): -10.50% (better)\n- Richards - average (lower is better): -3.36% (slightly better)\n- SciMark2 - average (higher is better): +0.26% (virtually unchanged)\n\nDetails about Ritzperf benchmarks with meaningful variations\n(lower is better):\n- FormulaEvaluationActions.EvaluateAndApplyChanges: -13.26% (better)\n- FormulaEvaluationActions.EvaluateCascadingSums: -10.94% (better)\n- FormulaEvaluationActions.EvaluateComplexFormulas: -15.50% (better)\n- FormulaEvaluationActions.EvaluateFibonacci: -10.41% (better)\n- FormulaEvaluationActions.EvaluateLargeSums: +6.02% (worse)\n\nBoot image code size variation on Nexus 5X\n(aosp_bullhead-userdebug build):\n- total ARM64 framework Oat files size change:\n 107047632 bytes -\u003e 107154128 bytes (+0.10%)\n- total ARM framework Oat files size change:\n 90932028 bytes -\u003e 91009852 bytes (+0.09%)\n\nTest: ART host and target (ARM, ARM64) tests + Nexus 5X boot.\nBug: 29516905\nBug: 29506760\nBug: 12687968\nChange-Id: I85431368d09965687a0301ae2eb3c991f276ce5d\n" }, { "commit": "542451cc546779f5c67840e105c51205a1b0a8fd", "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a", "parents": [ "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 26 09:02:02 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 18:54:48 2016 -0700" }, "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n" }, { "commit": "26de38bb7f2122417388809f4ff88a7cb5c4af5e", "tree": "878f432e2476f90201dd4695cfc8c3498c2c207f", "parents": [ "9755c262df1be7f5d5b98d038c8fd3734e974f9d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 17:53:11 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 17:56:08 2016 -0700" }, "message": "ART: Delete old compiler_enums.h\n\nHoldover from the Quick days. Move the two enums that are still\nused closer to the actual users (and prune no longer used cases).\n\nTest: m test-art-host\nChange-Id: I88aa49961a54635788cafac570ddc3125aa38262\n" }, { "commit": "dec8f63fdf50815f24efe1c03af64208da15f339", "tree": "36c8dec8c2c93312d17c6d9d1452d4b133212dbd", "parents": [ "41c7e2e6ac0a59da2f3e066e20630b295fbe4661" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 22 17:10:06 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 22 18:54:35 2016 +0100" }, "message": "Do not emit stack maps for runtime calls to ReadBarrierMarkRegX.\n\n* Boot image code size variation on Nexus 5X\n (aosp_bullhead-userdebug build):\n - total ARM64 framework Oat files size change:\n 115584120 bytes -\u003e 109124728 bytes (-5.59%)\n - total ARM framework Oat files size change:\n 97387728 bytes -\u003e 92517584 (-5.00%)\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I979d9fb2b4e09f4c0c7bf33af2cd91750a67f989\n" }, { "commit": "31167a5785f7a5124de96535066db9890559f546", "tree": "3d0ddb1bb390389532b5fc94dd6f2f5c8d648582", "parents": [ "bad21cb538d76105712c967b62d1cf677777a956", "3d31242300c3525e5c85665d9e34acf87002db63" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 24 13:04:36 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 24 13:04:37 2016 +0000" }, "message": "Merge changes I4d8da7ce,I4da5be01,Idfbead82\n\n* changes:\n Re-enable most intrinsics with read barriers.\n Fix ARM \u0026 ARM64 UnsafeGetObject intrinsics with read barriers.\n Fix x86 \u0026 x86-64 UnsafeGetObject intrinsics with read barriers.\n" }, { "commit": "0fcd2b84210db2bcf8b2d7a2b98a1a2bca367cac", "tree": "4619d1fb4bda64c01df3a6588b5c726510a72a1c", "parents": [ "61b370e4559a84910fe5bf0b2b1d7216ce805315" ], "author": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Tue Apr 05 17:12:59 2016 +0800" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 14:05:17 2016 +0100" }, "message": "Fix x86 \u0026 x86-64 UnsafeGetObject intrinsics with read barriers.\n\nThe implementation was incorrectly interpreting the \u0027offset\u0027\ninput as an index in a (4-byte) object reference array,\nwhereas it is a (1-byte) offset to an object reference field\nwithin the \u0027base\u0027 (object) input.\n\nBug: 29516905\nChange-Id: Idfbead8289222b55069816a81284401eff791e85\nTest: Covered by test/004-UnsafeTest.\n" }, { "commit": "dbb7f5bef10138ade0fb202da1d61f562b2df649", "tree": "f0aa4b390c534b215a6e000c865783cdd9852353", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 30 13:23:58 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 15:11:57 2016 +0100" }, "message": "Improve HLoadClass code generation.\n\nFor classes in the boot image, use either direct pointers\nor PC-relative addresses. For other classes, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe type\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -252KiB (-0.3%)\n - 64-bit boot.oat: -412KiB (-0.4%)\n - 32-bit dalvik cache total: -392KiB (-0.4%)\n - 64-bit dalvik-cache total: -2312KiB (-1.0%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -124KiB (-0.2%)\n - 64-bit boot.oat: -420KiB (-0.5%)\n - 32-bit dalvik cache total: -136KiB (-0.1%)\n - 64-bit dalvik-cache total: -1136KiB (-0.5%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 27950288\nChange-Id: I4da991a4b7e53c63c92558b97923d18092acf139\n" }, { "commit": "288c7a8664e516d7486ab85267050e676e84cc39", "tree": "8c117fcb348daf29477e1eb1338de9bc3c1dc706", "parents": [ "fbb0323d801cd14fb04eb4af7e88792d7cca8de3" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Mon May 16 11:53:15 2016 +0600" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Mon May 16 13:32:43 2016 +0600" }, "message": "Revert \"Revert \"ART: Reference.getReferent intrinsic for x86 and x86_64\"\"\n\nThis reverts commit 0997d24e67d78f2146ebae2888eda0d7d254789a.\n\nART_HEAP_POISONING\u003dtrue mode is fixed.\n\nChange-Id: I83f6d5c101ea6a86802753f81b3e4348a263fb21\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "0997d24e67d78f2146ebae2888eda0d7d254789a", "tree": "8b521397c856259c9049b52d86e40bfd2c84f0f4", "parents": [ "afdc97ebcb4e58afb7cf54d846d30314e6499d83" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 13 09:29:01 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 13 09:29:01 2016 +0000" }, "message": "Revert \"ART: Reference.getReferent intrinsic for x86 and x86_64\"\n\nFails heap poisoning configuration.\n\nThis reverts commit afdc97ebcb4e58afb7cf54d846d30314e6499d83.\n\nChange-Id: I50e53756a2b85059b89cfb8950f8c9e2b032743c\n" }, { "commit": "afdc97ebcb4e58afb7cf54d846d30314e6499d83", "tree": "bd7db3f73405d3d302f9f5021ffe2d424a7e8153", "parents": [ "3b62593ba55f6bdb37ca84f64930654ff4f09464" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Thu May 05 13:42:59 2016 +0600" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Tue May 10 11:35:08 2016 +0600" }, "message": "ART: Reference.getReferent intrinsic for x86 and x86_64\n\nChange-Id: I7a7ac9244847dd80d9fa4e4b5ebc5bf451c628ff\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "2efce70e4204e1a52769c63dac43c9d4af105751", "tree": "d812f91e3ca3d64c42d7e0d876b4559e62616406", "parents": [ "70c0f4e15797902e248e8b7aa0e013fe6d426c71", "7aa04a145e2e0d2949a1a1c7fd4c72d08d698587" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Apr 21 19:36:23 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 21 19:36:24 2016 +0000" }, "message": "Merge \"X86/X86_64: Switch to locked add from mfence\"" }, { "commit": "c01a66465a398ad15da90ab2bdc35b7f4a609b17", "tree": "e85cb2aa05be5c1491814fa83b94748439b8394b", "parents": [ "dad35b0762f97ce79ce3b9a35c9df5021b7dbd17" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "message": "Fix: correctly destruct VIXL labels.\n\nBug: 27505766\nChange-Id: I077465e3d308f4331e7a861902e05865f9d99835" }, { "commit": "7aa04a145e2e0d2949a1a1c7fd4c72d08d698587", "tree": "631554549d4b4dbde438fa0e6e636832427fe6c5", "parents": [ "4009bc645e3358d3150b7f94dd90a2c939f0fa51" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 27 22:39:07 2016 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Apr 12 17:25:51 2016 -0400" }, "message": "X86/X86_64: Switch to locked add from mfence\n\nI finally received the answers about the performance of locked add vs.\nmfence for Java memory semantics. Locked add has been faster than\nmfence for all processors since the Pentium 4. Accordingly, I have made\nthe synchronization use locked add at all times, removing it from an\ninstruction set feature.\n\nAlso add support in the optimizing compiler for barrier type\nkNTStoreStore, which is used after non-temporal moves.\n\nChange-Id: Ib47c2fd64c2ff2128ad677f1f39c73444afb8e94\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "dee58d6bb6d567fcd0c4f39d8d690c3acaf0e432", "tree": "5a2f20546ca3c1544c44bee560062580e22dc79c", "parents": [ "391e155a6936a05bd39b171031ec21d2dee62133" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 09:54:26 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 16:03:16 2016 +0000" }, "message": "Revert \"Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\"\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nThis CL fixed an issue with parsing quickened instructions.\n\nBug: 27894376\nBug: 27998571\nBug: 27995065\n\nChange-Id: I20dbe1bf2d0fe296377478db98cb86cba695e694\n" }, { "commit": "60328910cad396589474f8513391ba733d19390b", "tree": "01702f6df5c39925b354a3152dd04289e7d97062", "parents": [ "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "message": "Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\n\nBug: 27995065\nThis reverts commit e3ff7b293be2a6791fe9d135d660c0cffe4bd73f.\n\nChange-Id: I5363c7ce18f47fd422c15eed5423a345a57249d8\n" }, { "commit": "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f", "tree": "d578d27cb78e6d2caef683cd8ac94c9a9752b192", "parents": [ "86ea7eeabe30c98bbe1651a51d03cb89776724e7" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 02 16:48:20 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 11:21:30 2016 +0100" }, "message": "Refactor HGraphBuilder and SsaBuilder to remove HLocals\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nBug: 27894376\nChange-Id: Iefe28d40600c169c5d306fd2c77034ae19476d90\n" }, { "commit": "cac5a7e871f1f346b317894359ad06fa7bd67fba", "tree": "2df7d4892216a7c976dfe848c9893cb5eb8fa6a5", "parents": [ "6f51d7756a9c66007fe7666b19399e1f60ff6092" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 22 10:39:50 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 29 19:27:40 2016 +0100" }, "message": "Optimizing: Improve const-string code generation.\n\nFor strings in the boot image, use either direct pointers\nor pc-relative addresses. For other strings, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe string\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -692KiB (-0.9%)\n - 64-bit boot.oat: -948KiB (-1.1%)\n - 32-bit dalvik cache total: -900KiB (-0.9%)\n - 64-bit dalvik cache total: -3672KiB (-1.5%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -380KiB (-0.5%)\n - 64-bit boot.oat: -928KiB (-1.0%)\n - 32-bit dalvik cache total: -468KiB (-0.4%)\n - 64-bit dalvik cache total: -1928KiB (-0.8%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 26884697\nChange-Id: Iec7266ce67e6fedc107be78fab2e742a8dab2696\n" }, { "commit": "2ae48182573da7087bffc2873730bc758ec29696", "tree": "d6955329ad876aefd477f7ef8905b070b9ab95dd", "parents": [ "6915898b28cea6c9836ca1be6814d87e89cc6d76" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:05:09 2016 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:10:27 2016 +0000" }, "message": "Clean up NullCheck generation and record stats about it.\n\nThis removes redundant code from the generators and allows for easier\nstat recording.\n\nChange-Id: Iccd4368f9e9d87a6fecb863dee4e2145c97851c4\n" }, { "commit": "0e02ee9efbf1dbdde05d2b10f7307bbe191c52f5", "tree": "19c9c3e25a8db4e5b53890fd72193383b5bb73e5", "parents": [ "72ca09cc2dd350adb932ef4a50eff668cca99c5e", "c7098ff991bb4e00a800d315d1c36f52a9cb0149" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:23:50 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Feb 24 10:23:50 2016 +0000" }, "message": "Merge \"Remove HNativeDebugInfo from start of basic blocks.\"" }, { "commit": "c7098ff991bb4e00a800d315d1c36f52a9cb0149", "tree": "3a150e927bc7f4894f5b148ec6f5a2b796cdd80d", "parents": [ "5322e55ab9a15996a197456ca39d9c77488cd5c1" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 14:30:11 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:21:57 2016 +0000" }, "message": "Remove HNativeDebugInfo from start of basic blocks.\n\nWe do not require full environment at the start of basic block.\nThe dex pc contained in basic block is sufficient for line mapping.\n\nChange-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa\n" }, { "commit": "0c5b18edd1308975804ccf29a02a130a7b6f7fa7", "tree": "58f60a2f93973460f1602f007ffdb2c6d7c577bf", "parents": [ "7eca244e79480f2ecea341598524a53273959c2b" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Sat Feb 06 13:58:35 2016 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Feb 16 10:10:44 2016 -0500" }, "message": "Support CMOV for x86 Select\n\nIf possible, generate CMOV to implement HSelect. Tricky cases are a\nlong or FP condition (no single CC generated), FP inputs (no FP CMOV)\nand when the condition is a boolean or not emitted at the use site.\nIn these cases, keep using the existing HSelect code.\n\nChange-Id: I4ff1e152b8ef126fbbabeb3316e9e2b6a6b74aeb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "6e332529c33be4d7dae5dad3609a839f4c0d3bfc", "tree": "cedd2e1beb170fd5821136fe974e3f34adfcddc2", "parents": [ "d3caabd4f85f86dd744da432993e12935d843a83" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Feb 02 16:15:27 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Feb 12 15:17:50 2016 +0000" }, "message": "ART: Remove HTemporary\n\nChange-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03\n" }, { "commit": "a19616e3363276e7f2c471eb2839fb16f1d43f27", "tree": "ad3e7fd0f53229e95fb0443586fc30eedabe6967", "parents": [ "9fba3f67a0792ad5eeb495e489d11a87211c318f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 01 18:57:58 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Feb 05 09:26:21 2016 -0800" }, "message": "Implemented compare/signum intrinsics as HCompare\n(with all code generation for all)\n\nRationale:\nAt HIR level, many more optimizations are possible, while ultimately\ngenerated code can take advantage of full semantics.\n\nChange-Id: I6e2ee0311784e5e336847346f7f3c4faef4fd17e\n" }, { "commit": "2f10a5fb8c236a6786928f0323bd312c3ee9a4cc", "tree": "0dc51717b1f5d9b2c20898c5283467d4feb220e2", "parents": [ "a20748aceb63396c5e09366968bbc71308f745df" ], "author": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Jan 25 14:47:50 2016 +0000" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Feb 04 12:59:22 2016 -0500" }, "message": "Revert \"Revert \"X86: Use the constant area for more operations.\"\"\n\nThis reverts commit cf8d1bb97e193e02b430d707d3b669565fababb4.\n\nHandle the case of an intrinsic where CurrentMethod is still an input.\nThis will be the case when there are unresolved classes in the\nhierarchy.\n\nAdd a test case to confirm that we don\u0027t crash when handling Math.abs,\nwhich wants to add a pointer to the constant area for the bitmask to be\nused to remove the sign bit.\n\nEnhance 565-checker-condition-liveness to check for the case of deeply\nnested EmitAtUseSite chains.\n\nChange-Id: I022e8b96a32f5bf464331d0c318c56b9d0ac3c9a\n" }, { "commit": "cf8d1bb97e193e02b430d707d3b669565fababb4", "tree": "dcdf5e9baaa89b82515652d5abffa2712bc9b3ca", "parents": [ "dc00454f0b9a134f01f79b419200f4044c2af5c6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 25 09:43:30 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 25 09:43:30 2016 +0000" }, "message": "Revert \"X86: Use the constant area for more operations.\"\n\nHits a DCHECK:\n\ndex2oatd F 19461 20411 art/compiler/optimizing/pc_relative_fixups_x86.cc:196] Check failed: !invoke_static_or_direct-\u003eHasCurrentMethodInput() \n\n\nThis reverts commit dc00454f0b9a134f01f79b419200f4044c2af5c6.\n\nChange-Id: Idfcacf12eb9e1dd7e68d95e880fda0f76f90e9ed\n" }, { "commit": "dc00454f0b9a134f01f79b419200f4044c2af5c6", "tree": "49a787e2b617ce5bc69aa2dc4b71653c68ee0375", "parents": [ "2d0582b6c96cf16e18df50158494e32eeede0a95" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Oct 30 09:45:03 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 22 14:54:15 2016 -0500" }, "message": "X86: Use the constant area for more operations.\n\nAllow FP HNeg to use the constant area to hold the constant to flip the\nsign bit.\n\nEnhance some math intrinsics to allow the use of the constant\narea: Abs{Float,Double}, {Min,Max}{FloatFloat,DoubleDouble}.\n\nAllow compares of floats/doubles to constants using the constant area.\n\nThese eliminate almost all uses of loading constants from the stack.\n\nChange-Id: Ic4b831565825cbe9f0801b1b53c1013be7c87ae4\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "95e7ffc28ea4d6deba356e636b16120ae49b62e2", "tree": "f365f762a4ff46042871b86b96c112d6f1c8d624", "parents": [ "c24b8df48be848af1f4cb54e9caef2b7d6afe680" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:57:25 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:57:25 2016 +0000" }, "message": "Improve documentation and assertions of read barrier instrumentation.\n\nFor ARM, x86, x86-64 back ends. The case of the ARM64 back\nend is already handled in\nhttps://android-review.googlesource.com/#/c/197870/.\n\nBug: 12687968\nChange-Id: I6df1128cc100cbdb89020876e1a54de719508be3\n" }, { "commit": "e3f43ac79e50a4693ea4d46acf5cffca64910cee", "tree": "848caf115a3251ffc3c9fc60290549a52765801a", "parents": [ "17ccfff2de292fd2b4a78aef87d79b662381f920" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jan 19 15:07:47 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jan 19 15:07:47 2016 +0000" }, "message": "Some read barrier clean-up in Optimizing.\n\nThese changes make the read barrier compiler instrumentation\ncode more uniform among the ARM, ARM64, x86 and x86-64 back\nends.\n\nBug: 12687968\nChange-Id: I6b1c0cf2bc22ed6cd6b14754136bef4a2a036ea5\n" }, { "commit": "58282f4510961317b8d5a364a6f740a78926716f", "tree": "5d97c0db9fe01dd6e8df2357ef11f614abb853e8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 12:45:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 16:39:30 2016 +0000" }, "message": "ART: Remove Baseline compiler\n\nWe don\u0027t need Baseline any more and it hasn\u0027t been maintained for\na while anyway. Let\u0027s remove it.\n\nChange-Id: I442ed26855527be2df3c79935403a25b1ee55df6\n" }, { "commit": "42249c3602c3d0243396ee3627ffb5906aa77c1e", "tree": "1e822a21c87331246cbde3923eac88fa315fa2cc", "parents": [ "922698ded1e80cad1ecce4c2172a88c76a216373" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 07 15:33:50 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 12 16:39:20 2016 -0800" }, "message": "Reduce code size by sharing slow paths.\n\nRationale:\nSharing identical slow path code reduces code size.\n\nBackground:\nCurrently, slow paths with the same dex-pc, same physical register\nspilling code, and identical stack maps are shared (making this\nonly useful for deopt slow paths). The newly introduced mechanism\nis sufficiently general to allow future improvements by e.g.\nallowing different dex-pc (by passing this to runtime) or even\nthe kind of slow paths (by passing runtime addresses to the slowpath).\n\nChange-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0\n" }, { "commit": "152408f8c2188a7ed950cad04883b2f67dc74e84", "tree": "0fd24e0023060d1eb58eeb0b94e31a2311eefe16", "parents": [ "4bb356123b13ec5f41ea80158766df676ae08679" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 31 12:28:50 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 31 12:28:50 2015 -0500" }, "message": "X86: templatize GenerateTestAndBranch and friends\n\nAllow the use of NearLabel as well as Label. This will be used by the\nHSelect patch.\n\nReplace a couple of Label(s) with NearLabel(s) as well.\n\nChange-Id: I8e674c89e691bcdbccf4a5cdc07ad13b29ec21dd\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "5f7b58ea1adfc0639dd605b65f59198d3763f801", "tree": "04556e673cdd3967cc967ff79931eab49e523956", "parents": [ "1201804d1813d7db0accead9721d67c40b3de564" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 23 19:49:34 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 23 09:59:07 2015 +0000" }, "message": "Rewrite HInstruction::Is/As\u003ctype\u003e().\n\nMake Is\u003ctype\u003e() and As\u003ctype\u003e() non-virtual for concrete\ninstruction types, relying on GetKind(), and mark GetKind()\nas PURE to improve optimization opportunities. This reduces\nthe number of relocations in libart-compiler.so\u0027s .rel.dyn\nsection by ~4K, or ~44%, and in .data.rel.ro by ~18K, or\n~65%. The file is 96KiB smaller for Nexus 5, including 8KiB\nreduction of the .text section.\n\nUnfortunately, the g++/clang++ __attribute__((pure)) is not\nstrong enough to avoid duplicated virtual calls and we would\nneed the C++ [[pure]] attribute proposed in n3744 instead.\nTo work around this deficiency, we introduce an extra\nnon-virtual indirection for GetKind(), so that the compiler\ncan optimize common expressions such as\n instruction-\u003eIsAdd() || instruction-\u003eIsSub()\nor\n instruction-\u003eIsAdd() \u0026\u0026 instruction-\u003eAsAdd()-\u003e...\nwhich contain two virtual calls to GetKind() after inlining.\n\nChange-Id: I83787de0671a5cb9f5b0a5f4a536cef239d5b401\n" }, { "commit": "570a920d0a4a01e159a1be46609ff3db4aedc221", "tree": "d959ea022b6ef33d4c9aefef0f02756384e2769d", "parents": [ "fae1db92d8433d0f75258c190bcf2c940731f036", "17077d888a6752a2e5f8161eee1b2c3285783d12" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Dec 17 23:28:06 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 17 23:28:06 2015 +0000" }, "message": "Merge \"Revert \"Revert \"X86: Use locked add rather than mfence\"\"\"" }, { "commit": "14c4e90f67e71430dade7d4f20920e6352be386e", "tree": "2d376e0d6f833bb87348faae12ad7ed3bf15b95b", "parents": [ "6132a3884a912a704010f22ea2991f3d9d432af2", "f3e0ee27f46aa6434b900ab33f12cd3157578234" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Dec 17 16:46:19 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 17 16:46:19 2015 +0000" }, "message": "Merge \"Revert \"Revert \"ART: Reduce the instructions generated by packed switch.\"\"\"" }, { "commit": "f3e0ee27f46aa6434b900ab33f12cd3157578234", "tree": "83d5a75bf26238ff1789569de62e4b72fb348119", "parents": [ "b4c137630fd2226ad07dfd178ab15725374220f1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Dec 17 15:23:13 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Dec 17 15:23:13 2015 +0000" }, "message": "Revert \"Revert \"ART: Reduce the instructions generated by packed switch.\"\"\n\nThis reverts commit b4c137630fd2226ad07dfd178ab15725374220f1.\n\nThe underlying issue was fixed by https://android-review.googlesource.com/188271 .\n\nBug: 26121945\nChange-Id: I58b08eb1a9f0a5c861f8cda93522af64bcf63920\n" }, { "commit": "17077d888a6752a2e5f8161eee1b2c3285783d12", "tree": "15b869f7ed0a8273814b628cd277a6d5d779b24d", "parents": [ "d16bb3f0dc17d77db7022150d0710fcbb8b6fd9d" ], "author": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 16 19:15:59 2015 +0000" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 16 20:17:48 2015 -0500" }, "message": "Revert \"Revert \"X86: Use locked add rather than mfence\"\"\n\nThis reverts commit 0da3b9117706760e8722029f407da6d0297cc943.\n\nFix a compilation failure that slipped in somehow.\n\nChange-Id: Ide8681cdc921febb296ea47aa282cc195f154049\n" }, { "commit": "1c70f18dce7705ff70147ddebf65a97f66df8d5c", "tree": "7fa76545c1b91499b86f840cdb8c53050e9c761c", "parents": [ "1f312652e138e05328b9c4c738d3ecbab2d09ae9", "0da3b9117706760e8722029f407da6d0297cc943" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Dec 16 19:11:38 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Dec 16 19:11:38 2015 +0000" }, "message": "Merge \"Revert \"X86: Use locked add rather than mfence\"\"" }, { "commit": "0da3b9117706760e8722029f407da6d0297cc943", "tree": "84ad42399e1055f3596d7df6f786d9f7b8605ee3", "parents": [ "7b3e4f99b25c31048a33a08688557b133ad345ab" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Dec 16 19:06:17 2015 +0000" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Dec 16 19:06:17 2015 +0000" }, "message": "Revert \"X86: Use locked add rather than mfence\"\n\nThis reverts commit 7b3e4f99b25c31048a33a08688557b133ad345ab.\n\nReason: build error on sdk (linux) in git_mirror-aosp-master-with-vendor , please fix first\n\nart/compiler/optimizing/code_generator_x86_64.cc:4032:7: error: use of\nundeclared identifier \u0027codegen_\u0027\n codegen_-\u003eMemoryFence();\n\nChange-Id: I91f8542cfd944b7425d1981c35872dcdcb901e18\n" }, { "commit": "c3ca1e6543ef5e717183c059e68ac34597be7022", "tree": "ee7032d33c1dc8962a767d81321a142e9f4d173d", "parents": [ "9ddcbf69cfa807790e324f7f54e1931bc66d0f5c", "7b3e4f99b25c31048a33a08688557b133ad345ab" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Dec 16 18:47:07 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Dec 16 18:47:07 2015 +0000" }, "message": "Merge \"X86: Use locked add rather than mfence\"" }, { "commit": "d7d35383838c369a4a1ff5aa21e952f941718c48", "tree": "7d36f56c834e2b561ebc0359b9d11ad03d150cb2", "parents": [ "6b75bc08e8e2e5516a23350418bacef2cf982bd9", "b4c137630fd2226ad07dfd178ab15725374220f1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 16 12:31:14 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Dec 16 12:31:14 2015 +0000" }, "message": "Merge \"Revert \"ART: Reduce the instructions generated by packed switch.\"\"" }, { "commit": "b4c137630fd2226ad07dfd178ab15725374220f1", "tree": "6f319089980073ffb2c20d36e367a944daa525c4", "parents": [ "59f054d98f519a3efa992b1c688eb97bdd8bbf55" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 16 12:06:39 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 16 12:07:01 2015 +0000" }, "message": "Revert \"ART: Reduce the instructions generated by packed switch.\"\n\nThis reverts commit 59f054d98f519a3efa992b1c688eb97bdd8bbf55.\n\nbug:26121945\n\nChange-Id: I8a5ad7ef1f1de8d44787c27528fa3f7f5c2e9cd3\n" }, { "commit": "7b3e4f99b25c31048a33a08688557b133ad345ab", "tree": "446ce2d9b4684120c35fad9c097ea2f760f0797c", "parents": [ "089ff4886aa9b5e7cec04d2ef5cdeb9d68e5dc43" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Nov 19 14:08:40 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Dec 15 15:48:39 2015 -0500" }, "message": "X86: Use locked add rather than mfence\n\nJava semantics for memory ordering can be satisfied using\n lock addl $0,0(SP)\nrather than mfence. The locked add synchronizes the memory caches, but\ndoesn\u0027t affect device memory.\n\nTiming on a micro benchmark with a mfence or lock add $0,0(sp) in a loop\nwith 600000000 iterations:\ntime ./mfence\nreal 0m5.411s\nuser 0m5.408s\nsys 0m0.000s\n\ntime ./locked_add\nreal 0m3.552s\nuser 0m3.550s\nsys 0m0.000s\n\nImplement this as an instruction-set-feature lock_add. This is off by\ndefault (uses mfence), and enabled for atom \u0026 silvermont variants.\nGeneration of mfence can be forced by a parameter to MemoryFence.\n\nChange-Id: I5cb4fded61f4cbbd7b7db42a1b6902e43e458911\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "7c1559a06041c9c299d5ab514d54b2102f204a84", "tree": "c50b54bf82f457f44dbf0741947d836749d4a96a", "parents": [ "7cd230c8f74a227ea04f1dd93c8d855aa81fc1fe" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Dec 15 10:55:36 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Dec 15 11:45:56 2015 +0000" }, "message": "x86 Baker\u0027s read barrier fast path implementation.\n\nIntroduce an x86 fast path implementation in Optimizing for\nBaker\u0027s read barriers (for both heap reference loads and GC\nroot loads). The marking phase of the read barrier is\nperformed by a slow path, invoking a new runtime entry point\n(artReadBarrierMark).\n\nOther read barrier algorithms continue to use the original\nslow path based implementation, which has been renamed as\nGenerateReadBarrierSlow/GenerateReadBarrierForRootSlow.\n\nBug: 12687968\nChange-Id: Ie610c4befc19ff22378a8cba38b422dcacb54320\n" }, { "commit": "59f054d98f519a3efa992b1c688eb97bdd8bbf55", "tree": "83d5a75bf26238ff1789569de62e4b72fb348119", "parents": [ "763fd2d3d131898cad6295a19ae9a30e22ce5f2a" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@linaro.org", "time": "Mon Dec 07 17:17:03 2015 +0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Dec 08 13:14:10 2015 -0500" }, "message": "ART: Reduce the instructions generated by packed switch.\n\nImplement Vladimir Marko\u0027s suggestion. The new compare/jump series\nreduce the number of instructions from (2*n+1) to (1.5*n+3).\n\nGenerate normal compare/jump series when numEntries \u003c\u003d 3.\nGenerate optimal compare/jump series when numEntries \u003c\u003d threshold.\nGenerate jump tables otherwise.\n\nChange-Id: I425547b6787057c7fa84e71f17c145b63b208633\n" }, { "commit": "0debae7bc89eb05f7a2bf7dccd223318fad7c88d", "tree": "3da9656dc77d271b12c1b02793e7d713ae3da790", "parents": [ "991842a5273d20695dd5f35eb9a9e28c386c5b4b" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Nov 12 18:37:00 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Nov 17 15:12:00 2015 +0000" }, "message": "ART: Refactor GenerateTestAndBranch\n\nEach code generator implements a method for generating condition\nevaluation and branching to arbitrary labels. This patch refactors\nit for better clarity but also to generate fewer jumps when the true\nbranch is the fallthrough successor.\n\nThis is preliminary work for implementing HSelect.\n\nChange-Id: Iaa545a5ecbacb761c5aa241fa69140cf6eb5952f\n" }, { "commit": "0d5a281c671444bfa75d63caf1427a8c0e6e1177", "tree": "fd9bbe0f1c581bcc7c05bbfb2643ffe0b1fb014e", "parents": [ "dd4cbcc924c8ba2a578914a4a366996693bdcd74" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Nov 13 10:07:31 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Sun Nov 15 12:16:41 2015 +0000" }, "message": "x86/x86-64 read barrier support for concurrent GC in Optimizing.\n\nThis first implementation uses slow paths to instrument heap\nreference loads and GC root loads for the concurrent copying\ncollector, respectively calling the artReadBarrierSlow and\nartReadBarrierForRootSlow (new) runtime entry points.\n\nNotes:\n- This implementation does not instrument HInvokeVirtual\n nor HInvokeInterface instructions (for class reference\n loads), as the corresponding read barriers are not stricly\n required with the current concurrent copying collector.\n- Intrinsics which may eventually call (on slow path) are\n disabled when read barriers are enabled, as the current\n slow path infrastructure does not support this case.\n- When read barriers are enabled, the code generated for a\n HArraySet instruction always go into the array set slow\n path for object arrays (delegating the operation to the\n runtime), as we are lacking a mechanism to keep a\n temporary register live accross a runtime call (needed for\n the instrumentation of type checking code, which requires\n two successive read barriers).\n\nBug: 12687968\nChange-Id: I14cd6107233c326389120336f93955b28ffbb329\n" }, { "commit": "0f7dca4ca0be8d2f8776794d35edf8b51b5bc997", "tree": "cb2d99a0e9b7c50eb853a64b477268baaa77c11b", "parents": [ "ce0f43b97ffb5e4d14c5df6607d8efb46a5dc9d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 02 14:36:43 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 12 10:43:47 2015 +0000" }, "message": "Optimizing/X86: PC-relative dex cache array addressing.\n\nAdd PC-relative dex cache array addressing for X86 and use\nit for better invoke-static/-direct dispatch. Also delay\nthe initialization to the PC-relative base until needed.\n\nChange-Id: Ib8634d5edce4920cd70172fd13211809cf6948d1\n" }, { "commit": "dc151b2346bb8a4fdeed0c06e54c2fca21d59b5d", "tree": "391d8ccb44ff9e6fc1c8fa8975e534e20cc002ff", "parents": [ "823e693aa946ba75cd047429e1290011a2ed8729" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 15 18:02:30 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 23 14:45:32 2015 +0100" }, "message": "Optimizing: Determine invoke-static/-direct dispatch early.\n\nDetermine the dispatch type of invoke-static/-direct in a\nspecial pass right after the type inference. This allows the\ninliner to pass the \"needs dex cache\" check and inline more.\nIt also allows the code generator to avoid requesting a\nregister location for the ArtMethod* for kDexCachePcRelative\nand direct methods.\n\nThe supported dispatch check handles also situations that\nthe CompilerDriver currently doesn\u0027t allow. The cleanup of\nthe CompilerDriver and required changes to Quick will come\nin a separate change.\n\nChange-Id: I3f8e903a119949e95871d8ab0a995f4731a13a07\n" }, { "commit": "805b3b56c6eb542298db33e0181f135dc9fed3d9", "tree": "664d3ca2039805aa326c9e5e02dfae703ba7e634", "parents": [ "df3456007702b0dea01ffd1adfa74244857712af" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Sep 18 14:10:29 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Oct 14 09:54:31 2015 -0400" }, "message": "X86 jump tables for PackedSwitch\n\nImplement X86PackedSwitch using a jump table of offsets to blocks. The\nX86PackedSwitch version just adds an input to address the constant area.\n\nChange-Id: Id2752a1ee79222493040c6fd0e59aee9a544b76a\nBug: 21119474\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "e460d1df1f789c7c8bb97024a8efbd713ac175e9", "tree": "3511036fb18828dd0ee140d33a8bcd0535ebeab6", "parents": [ "25217af2a7cae96b32ba566aaf697288f3374c99" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 29 04:52:17 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 02 02:25:18 2015 +0100" }, "message": "Revert \"Revert \"Support unresolved fields in optimizing\"\n\nThe CL also changes the calling convetion for 64bit static field set\nto use kArg2 instead of kArg1. This allows optimizing to keep\nthe asumptions:\n- arm pairs are always of form (even_reg, odd_reg)\n- ecx_edx is not used as a register on x86.\n\nThis reverts commit e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1.\n\nChange-Id: I93159917565824084abc96775f31be1a4249f2f3\n" }, { "commit": "225b6464a58ebe11c156144653f11a1c6607f4eb", "tree": "3f1c6067c3841c892edaa1a60a61af9c559cb4e4", "parents": [ "6a9984e62c08bcd78c8e49dd40b1f0f9d53513b7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 28 12:17:40 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 10:49:35 2015 +0100" }, "message": "Optimizing: Tag arena allocations in code generators.\n\nAnd completely remove the deprecated GrowableArray.\n\nReplace GrowableArray with ArenaVector in code generators\nand related classes and tag arena allocations.\n\nLabel arrays use direct allocations from ArenaAllocator\nbecause Label is non-copyable and non-movable and as such\ncannot be really held in a container. The GrowableArray\nnever actually constructed them, instead relying on the\nzero-initialized storage from the arena allocator to be\ncorrect. We now actually construct the labels.\n\nAlso avoid StackMapStream::ComputeDexRegisterMapSize() being\npassed null references, even though unused.\n\nChange-Id: I26a46fdd406b23a3969300a67739d55528df8bf4\n" }, { "commit": "85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d", "tree": "c916b01b1608558a7d8c9d100274c4c6b6706386", "parents": [ "6766eae2d91e894b4ceab9f29cc983900e7bc0c7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 09 13:15:38 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 17 14:41:52 2015 -0700" }, "message": "ART: Refactor intrinsics slow-paths\n\nRefactor slow paths so that there is a default implementation for\ncommon cases (only arm64 with vixl is special). Write a generic\nintrinsic slow-path that can be reused for the specific architectures.\nMove helper functions into CodeGenerator so that they are accessible.\n\nChange-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550\n" }, { "commit": "e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "23a8e35481face09183a24b9d11e505597c75ebb" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "message": "Revert \"Support unresolved fields in optimizing\"\nbreaks debuggable tests.\n\nThis reverts commit 23a8e35481face09183a24b9d11e505597c75ebb.\n\nChange-Id: I8e60b5c8f48525975f25d19e5e8066c1c94bd2e5\n" }, { "commit": "23a8e35481face09183a24b9d11e505597c75ebb", "tree": "bcaafb6ea001349acbf160c2cc89334fab4a38dc", "parents": [ "175dc732c80e6f2afd83209348124df349290ba8" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 08 19:56:31 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:59 2015 +0100" }, "message": "Support unresolved fields in optimizing\n\nChange-Id: I9941fa5fcb6ef0a7a253c7a0b479a44a0210aad4\n" }, { "commit": "175dc732c80e6f2afd83209348124df349290ba8", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "5d01db1aa7634a012109d43e6403451b76de1daa" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Aug 25 15:42:32 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:51 2015 +0100" }, "message": "Support unresolved methods in Optimizing\n\nChange-Id: If2da02b50d2fa668cd58f134a005f1752e7746b1\n" }, { "commit": "fe157012b6d760c275d944ff83e8bea371c59b09", "tree": "a2b013dded6e25cab1d3ff5abf09c426904e142c", "parents": [ "aef880c4b872ccf1a63a3c563cb056ae117fc9c8", "ecc4366670e12b4812ef1653f7c8d52234ca1b1f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "message": "Merge \"Add OptimizingCompilerStats to the CodeGenerator class.\"" }, { "commit": "fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a", "tree": "3528c88e104dac8e58ae5370ab066b8b1dd0218f", "parents": [ "e295be4a95d7861f6ec179edf6565f58cad747cc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 15 10:15:55 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 16 13:21:33 2015 +0100" }, "message": "Optimizing: Tag arena allocations in HGraph.\n\nReplace GrowableArray with ArenaVector in HGraph and related\nclasses HEnvironment, HLoopInformation, HInvoke and HPhi,\nand tag allocations with new arena allocation types.\n\nChange-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d\n" }, { "commit": "b9c79928ff774c8d385ef2db169b447833207a44", "tree": "d9e5e34f1e227fa422e89e6754a7a63e605d45af", "parents": [ "402ae2dc9b94df62859bd9825e5c00f298dc71b2", "bfb5ba90cd6425ce49c2125a87e3b12222cc2601" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 09 16:39:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 09 16:39:16 2015 +0000" }, "message": "Merge \"Revert \"Revert \"Do a second check for testing intrinsic types.\"\"\"" }, { "commit": "bfb5ba90cd6425ce49c2125a87e3b12222cc2601", "tree": "6280171d451642dc70c87894d553f76c6c12db0a", "parents": [ "e6576390f957c82c2aede438834d028066757368" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 01 15:45:02 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 08 20:36:09 2015 -0700" }, "message": "Revert \"Revert \"Do a second check for testing intrinsic types.\"\"\n\nThis reverts commit a14b9fef395b94fa9a32147862c198fe7c22e3d7.\n\nWhen an intrinsic with invoke-type virtual is recognized, replace\nthe instruction with a new HInvokeStaticOrDirect.\n\nMinimal update for dex-cache rework. Fix includes.\n\nChange-Id: I1c8e735a2fa7cda4419f76ca0717125ef236d332\n" }, { "commit": "0616ae081e648f4b9b64b33e2624a943c5fce977", "tree": "20db99d802277cce68f88eda918ae7646383ff14", "parents": [ "e6576390f957c82c2aede438834d028066757368" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 17 12:49:27 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 08 17:01:05 2015 -0400" }, "message": "[optimizing] Add support for x86 constant area\n\nUse the Quick trick of finding the address of the method by calling the\nnext instruction and popping the return address into a register. This\ntrick is used because of the lack of PC-relative addressing in 32 bit\nmode on the X86.\n\nAdd a HX86ComputeBaseMethodAddress instruction to trigger generation\nof the method address, which is referenced by instructions needing\naccess to the constant area.\n\nAdd a HX86LoadFromConstantTable instruction that takes a\nHX86ComputeBaseMethodAddress and a HConstant that will be used to load\nthe value when needed.\n\nChange Add/Sub/Mul/Div to detect a HX86LoadFromConstantTable right hand\nside, and generate code that directly references the constant area.\nOther uses will be added later.\n\nChange the inputs to HReturn and HInvoke(s), replacing the FP constants\nwith HX86LoadFromConstantTable instead. This allows values to be\nloaded from the constant area into the right location.\n\nPort the X86_64 assembler constant area handling to the X86.\n\nUse the new per-backend optimization framework to do this conversion.\n\nChange-Id: I6d235a72238262e4f9ec0f3c88319a187f865932\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "ecc4366670e12b4812ef1653f7c8d52234ca1b1f", "tree": "fe7be52b1025b8122547b34d8765248d5959cd3a", "parents": [ "772cc4a2d4f978888d1b1e5a78c1c16a108260ed" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 13 13:33:12 2015 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 27 15:28:25 2015 +0100" }, "message": "Add OptimizingCompilerStats to the CodeGenerator class.\n\nJust refactoring, not yet used, but will be used by the incoming patch\nseries and future CodeGen specific stats.\n\nChange-Id: I7d20489907b82678120518a77bdab9c4cc58f937\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "581550137ee3a068a14224870e71aeee924a0646", "tree": "f62dd0d07c66a8ce4d7d994ee0e9c27bd8014bb1", "parents": [ "32f264e67afa8654a5570d38b627515fb73fc333" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:49:41 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 18:54:36 2015 +0100" }, "message": "Revert \"Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\"\n\nFixed kCallArtMethod to use correct callee location for\nkRecursive. This combination is used when compiling with\ndebuggable flag set.\n\nThis reverts commit b2c431e80e92eb6437788cc544cee6c88c3156df.\n\nChange-Id: Idee0f2a794199ebdf24892c60f8a5dcf057db01c\n" }, { "commit": "b2c431e80e92eb6437788cc544cee6c88c3156df", "tree": "6c0ac5f843845e4b09829eb0fd9f1b3013cf4494", "parents": [ "9b688a095afbae21112df5d495487ac5231b12d0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "message": "Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\n\nReverting due to failing ndebug tests.\n\nThis reverts commit 9b688a095afbae21112df5d495487ac5231b12d0.\n\nChange-Id: Ie4f69da6609df3b7c8443412b6cf7f5c43c2c5d9\n" }, { "commit": "9b688a095afbae21112df5d495487ac5231b12d0", "tree": "e5e881d4d124803e66f1e90c1e0a0e4c90d22e13", "parents": [ "009c34cba875885d9540696f33255a9b355d6e15" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 06 14:12:42 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:23:37 2015 +0100" }, "message": "Optimizing: Better invoke-static/-direct dispatch.\n\nAdd framework for different types of loading ArtMethod*\nand code pointer retrieval. Implement invoke-static and\ninvoke-direct calls the same way as Quick. Document the\ndispatch kinds in HInvokeStaticOrDirect\u0027s new enumerations\nMethodLoadKind and CodePtrLocation.\n\nPC-relative loads from dex cache arrays are used only for\nx86-64 and arm64. The implementation for other architectures\nwill be done in separate CLs.\n\nChange-Id: I468ca4d422dbd14748e1ba6b45289f0d31734d94\n" }, { "commit": "8158f28b6689314213eb4dbbe14166073be71f7e", "tree": "fced445e53f639b2db42cb5a0e96d5aa04750861", "parents": [ "33407564904d2186f536107e1ca8d88f2c760c83" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Aug 07 10:26:17 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Aug 07 10:26:17 2015 +0100" }, "message": "Ensure coherency of call kinds for LocationSummary.\n\nThe coherency is enforced with checks added in the `InvokeRuntime`\nhelper, that we now also use on x86 and x86_64.\n\nChange-Id: I8cb92b042f25dc3c5fd390e9c61a45b477d081f4\n" }, { "commit": "c470193cfc522fc818eb2eaab896aef9caf0c75a", "tree": "9887d434f8d9e33c41b98ca406e7c060c68c9016", "parents": [ "c87c8939ea1bcfbddb954478d527cf1138f4f343" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 10 13:18:51 2015 -0400" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 07 16:49:53 2015 +0100" }, "message": "Fuse long and FP compare \u0026 condition on x86/x86-64 in Optimizing.\n\nThis is a preliminary implementation of fusing long/float/double\ncompares with conditions to avoid materializing the result from the\ncompare and condition.\n\nThe information from a HCompare is transferred to the HCondition if it\nis legal. There must be only a single use of the HCompare, the HCompare\nand HCondition must be in the same block, the HCondition must not need\nmaterialization.\n\nAdded GetOppositeCondition() to HCondition to return the flipped\ncondition.\n\nBug: 21120453\nChange-Id: I1f1db206e6dc336270cd71070ed3232dedc754d6\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "fc6a86ab2b70781e72b807c1798b83829ca7f931", "tree": "90201491e811cf7be0e0469d7a06a828f4384cad", "parents": [ "d3eaade87ac079accca30473ef0a3b38ab600828" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 10:33:45 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 13:49:50 2015 +0100" }, "message": "Revert \"Revert \"ART: Implement try/catch blocks in Builder\"\"\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nThis reverts commit 3e18738bd338e9f8363b26bc895f38c0ec682824.\n\nChange-Id: I4f5ea961848a0b83d8db3673763861633e9bfcfb\n" }, { "commit": "3e18738bd338e9f8363b26bc895f38c0ec682824", "tree": "708013ef06cfb524f040b2b5c494f7f3cb84ac2c", "parents": [ "0b5c7d1994b76090afcc825e737f2b8c546da2f8" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "message": "Revert \"ART: Implement try/catch blocks in Builder\"\n\nCauses OutOfMemory issues, need to investigate.\n\nThis reverts commit 0b5c7d1994b76090afcc825e737f2b8c546da2f8.\n\nChange-Id: I263e6cc4df5f9a56ad2ce44e18932ca51d7e349f\n" }, { "commit": "0b5c7d1994b76090afcc825e737f2b8c546da2f8", "tree": "057eddf8830b1991f02af3c3ce1b63dee90dd2ad", "parents": [ "1dd3136d9f6b1c7d551897a2d96c8314e40f7324" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 11 11:17:49 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 25 16:58:08 2015 +0100" }, "message": "ART: Implement try/catch blocks in Builder\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nChange-Id: I415b985596d5bebb7b1bb358a46e08b7b04bb53a\n" }, { "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907", "tree": "a0a488040883c14cc6cbec3186654137459d44ff", "parents": [ "8ec0e20347e13592539a8c0786b1db1735149800" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 22 11:57:36 2015 +0100" }, "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n" }, { "commit": "ef20f71e16f035a39a329c8524d7e59ca6a11f04", "tree": "a2892ae08f22ccf46baa4c77cea61f32bd07242d", "parents": [ "864a2d955aa85ab989c86d7f1eeacbe0b11f8b0f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jun 09 10:29:30 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Jun 10 10:19:57 2015 +0100" }, "message": "Add boilerplate code for architecture-specific HInstructions.\n\nChange-Id: I2723cd96e5f03012c840863dd38d7b2168117db8\n" }, { "commit": "69aa60163989c33a008115205d39732a76ecc1dc", "tree": "058392dc104a8e7b3594a548239dca2d3ec06cce", "parents": [ "aa77f6e5839b2ad3bf8ca2c06a44ec92e2667af1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 10:34:25 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 16:01:49 2015 +0100" }, "message": "Revert \"Revert \"Pass current method to HNewInstance and HNewArray.\"\"\n\nProblem exposed by this change was fixed in:\nhttps://android-review.googlesource.com/#/c/154031/\n\nThis reverts commit 7b0e353b49ac3f464c662f20e20e240f0231afff.\n\nChange-Id: I680c13dc9db9ba223ab11c7af255222860b4e6d2\n" }, { "commit": "7b0e353b49ac3f464c662f20e20e240f0231afff", "tree": "b5c936df891b08521176065ccaddb1f9e27c9f46", "parents": [ "e21aa42e1341d34250742abafdd83311ad9fa737" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 09:25:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 09:25:50 2015 +0000" }, "message": "Revert \"Pass current method to HNewInstance and HNewArray.\"\n\n082-inline-execute fails on x86.\n\nThis reverts commit e21aa42e1341d34250742abafdd83311ad9fa737.\n\nChange-Id: Ib3fd25faee2e0128001e40d3d51a74f959bc4449\n" }, { "commit": "e21aa42e1341d34250742abafdd83311ad9fa737", "tree": "d2c9f8530e59876588d32f04b4effc25ebc0fa89", "parents": [ "c47908e8c32fd58bc4dc75998a80f706954db1dc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 08 15:35:07 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 08 15:36:27 2015 +0100" }, "message": "Pass current method to HNewInstance and HNewArray.\n\nAlso remove unsed CodeGenerator::LoadCurrentMethod.\n\nChange-Id: I4b8d3f2a30b8e2c76b6b329a72555483c993cb73\n" }, { "commit": "38207af82afb6f99c687f64b15601ed20d82220a", "tree": "f9360949b92e5b6b01c5828c03ac67d01adffe1d", "parents": [ "6a0d5e7fe6dc0c9d3dd941ab991203f2d5d1c354" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 01 15:46:22 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 14:39:06 2015 +0100" }, "message": "Use HCurrentMethod in HInvokeStaticOrDirect.\n\nChange-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66\n" }, { "commit": "fd88f16100cceafbfde1b4f095f17e89444d6fa8", "tree": "fdb6d0520ca419acef9e953e74dcbd7d908bc4dd", "parents": [ "1aebdae18678403bdac078cbbe1f7dd4243c44f3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "message": "Factorize code for common LocationSummary of HInvoke.\n\nThis is one step forward, we could factorize more, but\nI wanted to get this out of the way first.\n\nChange-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "07276db28d654594e0e86e9e467cad393f752e6e", "tree": "6450e07d64045f0c0949b3423501316b672641c7", "parents": [ "17f1bc531ea2f8c1a6fac3def13dee1b901949dd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 14:22:09 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 19:15:52 2015 +0100" }, "message": "Don\u0027t do a null test in MarkGCCard if the value cannot be null.\n\nChange-Id: I45687f6d3505178e2fc3689eac9cb6ab1b2c1e29\n" }, { "commit": "7394569c9252b277710b2d7d3fc35fb0dd48fc4b", "tree": "9ce2241c95d93e873c45416a2d17e2c4084d220b", "parents": [ "8a30bf23bcb1ad8d4ed9060ddbb27edbfd57a897" ], "author": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 29 14:56:17 2015 +0000" }, "committer": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon May 04 14:14:32 2015 +0000" }, "message": "Revert \"Revert \"Revert \"Revert \"[optimizing] Improve x86 shifts\"\"\"\"\n\nThis reverts commit 2a7a1d7808f003bea908023ebd11eb442d2fca39.\n\nFix the problem that a long long \u003e\u003e 63 got the wrong answer. The\nproblem was that a shr was used instead of a sar.\n\nChange-Id: I0327f79c718016ddec9272a605fc50ec15ec4566\n" }, { "commit": "2d27c8e338af7262dbd4aaa66127bb8fa1758b86", "tree": "e01e0bc57359df0bdf00c3da694c5403fb7fc9e6", "parents": [ "3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 15:48:45 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Apr 29 14:09:17 2015 +0100" }, "message": "Refactor InvokeDexCallingConventionVisitor in Optimizing.\n\nChange-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34\n" }, { "commit": "4bb014fd8e0aa45b012d56bc4813f18fa295d2b0", "tree": "ba5fa5beef6e2c4a91ec5bbe7b0ed81b168b4958", "parents": [ "d677de20906067061f262bdd434536a02e7f0dd0", "232ade0b9401404ad4b61b1003551b58b96195a8" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 21 16:09:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 21 16:09:30 2015 +0000" }, "message": "Merge \"Revert \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"\"" }, { "commit": "232ade0b9401404ad4b61b1003551b58b96195a8", "tree": "54fe7cc37674246dead84f883a4c8be2123e7d26", "parents": [ "2e0f89b1b61685f7c322a4c6ec3e3b4839e76d64" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 20 15:14:36 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 20 15:53:12 2015 +0100" }, "message": "Revert \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"\n\nThis reverts commit 386ce406f150645158d6067c4e0a36565aefc44f.\n\nBug: 20413424\nChange-Id: I6e93ff132907f2653f1ae12d6676ff2298f62ca1\n" }, { "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467", "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab", "parents": [ "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:48:56 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:54:08 2015 +0800" }, "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n" }, { "commit": "669d8a1edbb2a78e08731a9cd6d8e815b0ec49db", "tree": "240d26edb4af28ccd7fa65a9fecc39f718d3d603", "parents": [ "ee2da343bb2a54d9d77e29226e0317ccc913c8c1", "e14590bdfed24df30e6b7545fc819ba03ff8bba1" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 16 09:40:38 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 16 09:40:39 2015 +0000" }, "message": "Merge \"Revert \"[optimizing] Improve x86 parallel moves/swaps\"\"" }, { "commit": "e14590bdfed24df30e6b7545fc819ba03ff8bba1", "tree": "1fe89a424c91dae7adc07ebd620dce8297a0854e", "parents": [ "a5c19ce8d200d68a528f2ce0ebff989106c4a933" ], "author": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Wed Apr 15 18:57:27 2015 +0000" }, "committer": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Wed Apr 15 18:57:27 2015 +0000" }, "message": "Revert \"[optimizing] Improve x86 parallel moves/swaps\"\n\nThis reverts commit a5c19ce8d200d68a528f2ce0ebff989106c4a933.\n\nThis commit introduces a performance regression on CaffeineLogic of 30%.\n\nChange-Id: I917e206e249d44e1748537bc1b2d31054ea4959d\n" }, { "commit": "e4e88d7b37c977b4c755485174a54c04aa3de951", "tree": "b25d5be5b8e7320d05f42da549c11cc82d7dbc51", "parents": [ "6cfece6336c86017694758bbc0dc68b62c02de86", "386ce406f150645158d6067c4e0a36565aefc44f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 13 12:53:56 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 13 12:53:57 2015 +0000" }, "message": "Merge \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"" }, { "commit": "386ce406f150645158d6067c4e0a36565aefc44f", "tree": "e350441be38017d6e7555d9e13ca8b975d61451d", "parents": [ "2d45b4df3838d9c0e5a213305ccd1d7009e01437" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 13 12:53:37 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 13 12:53:37 2015 +0000" }, "message": "Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\n\nTest fails on arm.\n\nThis reverts commit 2d45b4df3838d9c0e5a213305ccd1d7009e01437.\n\nChange-Id: Id2864917b52f7ffba459680303a2d15b34f16a4e\n" }, { "commit": "6cfece6336c86017694758bbc0dc68b62c02de86", "tree": "c0cc90f4167aed365c0ebfddd99fec31c473efc2", "parents": [ "095d209342420563becfec6676b46a6c6b839107", "2d45b4df3838d9c0e5a213305ccd1d7009e01437" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 13 11:33:08 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 13 11:33:09 2015 +0000" }, "message": "Merge \"Optimizing: Fix long-to-fp conversion on x86.\"" }, { "commit": "2d45b4df3838d9c0e5a213305ccd1d7009e01437", "tree": "b3893899a540ba9f4c8cd70e69536d0239a9d3ef", "parents": [ "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Tue Apr 07 17:04:50 2015 +0600" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 13 11:30:02 2015 +0000" }, "message": "Optimizing: Fix long-to-fp conversion on x86.\n\nlong-to-fp conversion implemented using SSE loses the precision.\nThe test is included. CL uses FPU to provide the correct result.\n\nChange-Id: I8eaf3c46819a8cb52642a7e7d7c4e3e0edbc88db\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "1b743777e6b6cec3387b0ee347b6a8a03779c345", "tree": "036c42dbf10d8c75de1326e16406a12191c704ce", "parents": [ "cf69f8163d700be29a1732e7e229101c67a51803", "f9aac1e9f442c2486cd54f045d43e15791601205" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Apr 10 21:40:59 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 10 21:41:00 2015 +0000" }, "message": "Merge \"Revert \"[optimizing] Improve x86 shifts\"\"" }, { "commit": "f9aac1e9f442c2486cd54f045d43e15791601205", "tree": "2f3aa65a881020beeb6f4b3313b3366733bbf3f5", "parents": [ "222fcf96c9b73bbb739012575e7e413caf9348ec" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 10 18:12:48 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 10 18:12:48 2015 +0000" }, "message": "Revert \"[optimizing] Improve x86 shifts\"\n\nThis reverts commit 222fcf96c9b73bbb739012575e7e413caf9348ec.\n\nReverting this CL as it is breaking a few tests (see http://build.chromium.org/p/client.art/builders/host-x86/builds/3251/steps/test%20optimizing/logs/stdio). Will investigate ASAP.\n\nChange-Id: Iddd8363e83a24aa49fbdf0f0c9dc12e63b4848de\n" }, { "commit": "27ef3177fb164b5e1a3b8a6fd43d25f3074e586d", "tree": "3717202ea300f60f6df3aa29922b98579b7958d5", "parents": [ "47317b430ee4f0094e58df45b557fe754b29b63b", "b19930c5cba3cf662dce5ee057fcc9829b4cbb9c" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Apr 10 16:15:07 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 10 16:15:07 2015 +0000" }, "message": "Merge \"Follow up of \"div/rem on x86 and x86_64\", to tidy up the code a little.\"" }, { "commit": "a5c19ce8d200d68a528f2ce0ebff989106c4a933", "tree": "4638a8d8e5b1562ec5ed05967490fec1ef7f0d17", "parents": [ "6d80318c382a3490ab605b46fa7cb22c5e823fec" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 12:51:05 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 10 12:08:31 2015 -0400" }, "message": "[optimizing] Improve x86 parallel moves/swaps\n\nAdd a new constructor to ScratchRegisterScope that will supply a\nregister if there is a free one, but not spill to force one. Use this\nto generated alternate code that doesn\u0027t use a temporary, as the\nspill/restore of a register generates extra instructions that aren\u0027t\nnecessary on x86.\n\nHere is the benefit for a 32 bit memory-to-memory exchange with no\nfree registers:\n\u003c 50 \t push eax\n\u003c 53 \t push ebx\n\u003c 8B44244C \t mov eax, [esp + 76]\n\u003c 8B5C246C \t mov ebx, [esp + 108]\n\u003c 8944246C \t mov [esp + 108], eax\n\u003c 895C244C \t mov [esp + 76], ebx\n\u003c 5B \t pop ebx\n\u003c 58 \t pop eax\n---\n\u003e FF742444 \t push [esp + 68]\n\u003e FF742468 \t push [esp + 104]\n\u003e 8F44244C \t pop [esp + 72]\n\u003e 8F442468 \t pop [esp + 100]\n\nAvoid using xchg instruction, as it is slow on smaller processors.\n\nChange-Id: Id29ee3abd998577baaee552d55d23e60ae0c7871\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "222fcf96c9b73bbb739012575e7e413caf9348ec", "tree": "e0441bc484cc8f441685de49c931a030730a3701", "parents": [ "fcfea6324b2913621d5cb642d4315f22c4901368" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Mar 30 14:13:30 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 10 09:33:52 2015 -0400" }, "message": "[optimizing] Improve x86 shifts\n\nSupport memory operands for integer shifts. Generate better code for\nlong shifts by constants.\n\nChange-Id: Icc92fa1b59cc280d4894af6f054e19b01977d5ce\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b19930c5cba3cf662dce5ee057fcc9829b4cbb9c", "tree": "c226f8fffc4522b273072c516507083e2a77c505", "parents": [ "0f88e87085b7cf6544dadff3f555773966a6853e" ], "author": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Thu Apr 09 21:12:15 2015 +0100" }, "committer": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Fri Apr 10 10:28:02 2015 +0100" }, "message": "Follow up of \"div/rem on x86 and x86_64\", to tidy up the code a little.\n\nChange-Id: Ibf39cbc8ac1d773599d70be2cb1e941674b60f1d\n" } ], "next": "96159860fc6c4bf68a51a8a57941971f122685d6" }