)]}'
{
  "log": [
    {
      "commit": "2477320a8d9de58ede68e2645ea53c10f71dcd57",
      "tree": "f428a6856e10d8ebaff0bb2da544a8d41c35ab77",
      "parents": [
        "5a87e19e4bf1b6719c2aad3effde1b38d2c3085c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 26 10:28:51 2018 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 26 10:28:51 2018 -0700"
      },
      "message": "Step 1 of 2: conditional passes.\n\nRationale:\nThe change adds a return value to Run() in preparation of\nconditional pass execution. The value returned by Run() is\nbest effort, returning false means no optimizations were\napplied or no useful information was obtained. I filled\nin a few cases with more exact information, others\nstill just return true. In addition, it integrates inlining\nas a regular pass, avoiding the ugly \"break\" into\noptimizations1 and optimziations2.\n\nBug: b/78171933, b/74026074\n\nTest: test-art-host,target\nChange-Id: Ia39c5c83c01dcd79841e4b623917d61c754cf075\n"
    },
    {
      "commit": "b50b16a68ababbc9acab6102bf0bb63bd5083763",
      "tree": "f440f12f8ab3b14b8c4b02c978561f43356e61b0",
      "parents": [
        "2202d56061941b4fecbdb018d84bcefb05b6c683"
      ],
      "author": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Tue Sep 19 17:43:29 2017 +0100"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Thu Nov 09 15:48:04 2017 -0800"
      },
      "message": "Support VecLoad and VecStore in LSA.\n\nTest: test-art-host\nTest: test-art-target\nTest: load_store_analysis_test\n\nChange-Id: I7d819061ec9ea12f86a926566c3845231fce6e26\n"
    },
    {
      "commit": "016c0f165dc6872d22c12c239d19b094983519f1",
      "tree": "bef8e9912412d02b7aa3913f2750147835454b2e",
      "parents": [
        "d1c983a5bc3ae50eab3af405ae8a415e1f36f532"
      ],
      "author": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Fri May 12 18:16:31 2017 +0100"
      },
      "committer": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Mon Jun 26 11:30:39 2017 +0100"
      },
      "message": "Improve array index analysis in LSA.\n\nThis CL improves analysis on array index in load store analysis.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: m test-art-host-gtest-load_store_analysis_test\n\nChange-Id: Id5e5aa8b396c68e082db95809659494107985fa2\n"
    },
    {
      "commit": "c239a2bb9474a1266c4882638fdb19056370e16d",
      "tree": "57fc8b0ba198cc6a6db65cbf48a600c38d269890",
      "parents": [
        "80dd30abe3fac52f6de4aec0543918d360f7d08a"
      ],
      "author": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Thu Apr 27 15:31:37 2017 +0100"
      },
      "committer": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Fri May 19 17:17:06 2017 +0100"
      },
      "message": "Create load store analysis pass\n\nThis CL separates load store analysis from LSE pass.\n\nThe load and store analysis in LSE pass records information\nabout heap memory accesses for arrays and fields.\nSuch information can also be used in the other optimizations like\ninstruction scheduling pass which can eliminate side-effect\ndependencies between memory accesses to different locations.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: m test-art-host-gtest-load_store_analysis_test\nTest: 530-checker-lse\n\nChange-Id: I353a2b9a03b19bfa0e7ef07716d60bd4254c7ea7\n"
    }
  ]
}