)]}'
{
  "log": [
    {
      "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce",
      "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518",
      "parents": [
        "893e8881e31180721512c1b9e5ffacb03aad2e45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 07 16:01:24 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 08 13:57:51 2015 +0000"
      },
      "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n  (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n  registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n"
    },
    {
      "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c",
      "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955",
      "parents": [
        "776b880f66edb21cb3b4225877e494ec7a9ec1a2"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 10:36:50 2014 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 14:36:14 2014 +0000"
      },
      "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7"
    },
    {
      "commit": "296bd60423e0630d8152b99fb7afb20fbff5a18a",
      "tree": "384aa7659763bb77a038a67c27f7cf6059632570",
      "parents": [
        "57b4d1c44e246dfd4aaef2d23b20a696a0c5e57e"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Oct 06 16:47:28 2014 -0700"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Nov 03 16:16:50 2014 -0800"
      },
      "message": "Some improvement to reg alloc.\n\nChange-Id: If579a37791278500a7e5bc763f144c241f261920\n"
    },
    {
      "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f",
      "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a",
      "parents": [
        "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 15 18:31:05 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 16:03:51 2014 +0100"
      },
      "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n"
    },
    {
      "commit": "6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3",
      "tree": "f7a20779e4d665f948c5fbcd26dac0071dafb8d4",
      "parents": [
        "2df6840f68dd18d7dd8dbf53f8b6181bbfdc4fc4"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Oct 14 17:41:57 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Oct 16 19:27:28 2014 -0700"
      },
      "message": "Make ART compile with GCC -O0 again.\n\nTidy up InstructionSetFeatures so that it has a type hierarchy dependent on\narchitecture.\nAdd to instruction_set_test to warn when InstructionSetFeatures don\u0027t agree\nwith ones from system properties, AT_HWCAP and /proc/cpuinfo.\nClean-up class linker entry point logic to not return entry points but to\ntest whether the passed code is the particular entrypoint. This works around\nimage trampolines that replicate entrypoints.\nBug: 17993736\n\nChange-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23\n"
    },
    {
      "commit": "740475d5f45b8caa2c3c6fc51e657ecf4f3547e5",
      "tree": "81196b753045fa16c13a4c1106031c1f28d9d233",
      "parents": [
        "13c4e8f4ef687f650aa76fb15ab12762d5a85602"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 29 10:33:25 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 29 11:04:07 2014 +0100"
      },
      "message": "Fix a bug in the insertion of parallel move.\n\nTo make sure we do not connect interval siblings in the\nsame parallel move, I added a new field in MoveOperands\nthat tells for which instruction this move is for.\nA parallel move should not contains moves for the same instructions.\n\nThe checks revealed a bug when connecting siblings, where\nwe would choose the wrong parallel move.\n\nChange-Id: I70f27ec120886745c187071453c78da4c47c1dd2\n"
    },
    {
      "commit": "3c04974a90b0e03f4b509010bff49f0b2a3da57f",
      "tree": "52649104e3e80272c3774793350f4d9f260ae732",
      "parents": [
        "c0d36abb12cdbb9469039c1dc153a586bd984015"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 24 18:10:46 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 25 12:23:40 2014 +0100"
      },
      "message": "Optimize suspend checks in optimizing compiler.\n\n- Remove the ones added during graph build (they were added\n  for the baseline code generator).\n- Emit them at loop back edges after phi moves, so that the test\n  can directly jump to the loop header.\n- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.\n\nChange-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a\n"
    },
    {
      "commit": "3bca0df855f0e575c6ee020ed016999fc8f14122",
      "tree": "15e15c8290ad314c29ca608f51d89d4db68fd9ba",
      "parents": [
        "d41491adb23764f28a80cbb7f2bd7af6491cd892"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 19 11:01:00 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 23 13:57:30 2014 +0100"
      },
      "message": "Support for saving and restoring live registers in a slow path.\n\nAnd use it in suspend check slow paths.\n\nChange-Id: I79caf28f334c145a36180c79a6e2fceae3990c31\n"
    },
    {
      "commit": "aac0f39a3501a7f7dd04b2342c2a16961969f139",
      "tree": "ef71b73a7d95de726d36883e6c88f7c8cbcfaaf6",
      "parents": [
        "56369897d662ea63ea5ed57ae36af0ae0fa1452d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 16 14:11:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 16 14:15:22 2014 +0100"
      },
      "message": "Fix a bug in the register allocator.\n\nWe need to take the live interval that starts first to know\nuntil when a register is free, instead of using the live interval\nthat is last in the inactive list.\n\nChange-Id: I2c9f87481ff1b4fc7b9948db7559b8d3b11d84ce\n"
    },
    {
      "commit": "3946844c34ad965515f677084b07d663d70ad1b8",
      "tree": "0d85bfba2ff69c34a2897351d1e50a1464509305",
      "parents": [
        "e2c23739c6395a83b30ece38f8a2e9e1bf7cf3ce"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 02 15:17:15 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 08 12:15:07 2014 +0100"
      },
      "message": "Runtime support for the new stack maps for the opt compiler.\n\nNow most of the methods supported by the compiler can be optimized,\ninstead of using the baseline.\n\nChange-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa\n"
    },
    {
      "commit": "93bedb7a96c8e6f9b6caa66689bf4f3c520bc234",
      "tree": "0f8cf8717de1ca9fa81b6517030d2ffa160377a1",
      "parents": [
        "b2a59010b787bd9d5d9bf36d32682faa5ad8da24"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 18 10:23:59 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 18 10:23:59 2014 +0100"
      },
      "message": "We can also run the linear scan register allocator on thumb.\n\nChange-Id: I5d21b5cbcdd93ff36342111de4ebcaab172034dd\n"
    },
    {
      "commit": "e63db27db913f1a88e2095a1ee8239b2bb9124e8",
      "tree": "893dee6783bca6717259321a6e4ba029c9c123e2",
      "parents": [
        "07b8441303ea82fca3cb85d71ecf8752d73cedd7"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Jul 15 15:36:11 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Jul 15 17:07:49 2014 -0700"
      },
      "message": "Break apart header files.\n\nCreate libart-gtest for common runtime and compiler gtest routines.\nRename CompilerCallbacksImpl that is quick compiler specific.\nRename trace clock source constants to not use the overloaded profiler term.\n\nChange-Id: I4aac4bdc7e7850c68335f81e59a390133b54e933\n"
    },
    {
      "commit": "412f10cfed002ab617c78f2621d68446ca4dd8bd",
      "tree": "bbd9dddd0436da566365ada5deb1840e315e1b11",
      "parents": [
        "d6ab04646d8eec6f24b200f8649f3d942d9ad17e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 19 10:00:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 02 16:00:32 2014 +0100"
      },
      "message": "Support longs in the register allocator for x86_64.\n\nChange-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867\n"
    },
    {
      "commit": "ecb2f9ba57b08ceac4204ddd6a0a88a0524f8741",
      "tree": "0285f887316bc4bb00810bbab1f508a6d2a2df5b",
      "parents": [
        "799605088f51dace7fddaf8493c8c6f3090fdaf6"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jun 13 08:59:59 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 16 09:35:09 2014 +0100"
      },
      "message": "Enable the register allocator on x86_64.\n\nAlso fix an x86_64 assembler bug for movl.\n\nChange-Id: I8d17c68cd35ddd1d8df159f2d6173a013a7c3347\n"
    },
    {
      "commit": "e27f31a81636ad74bd3376ee39cf215941b85c0e",
      "tree": "12dd6a1153b78b831c887f65f0bcef715e89719d",
      "parents": [
        "dfc2091d2fb8a7694f69acf8bd39ce4953e026c2"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 17:53:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 18:05:00 2014 +0100"
      },
      "message": "Enable the register allocator on ARM.\n\n- Also fixes a few bugs/wrong assumptions in code not hit by x86.\n- We need to differentiate between moves due to connecting siblings within\n  a block, and moves due to control flow resolution.\n\nChange-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38\n"
    },
    {
      "commit": "86dbb9a12119273039ce272b41c809fa548b37b6",
      "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5",
      "parents": [
        "c936622863a50bdda9b10062515dfc02a8c8b652"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 04 11:12:39 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 10:02:06 2014 +0100"
      },
      "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n   allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n   inputs/output to be at a specific location, and the allocator\n   needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n"
    },
    {
      "commit": "31d76b42ef5165351499da3f8ee0ac147428c5ed",
      "tree": "4f9cf307923c72f73e4a814662a26406f155c38c",
      "parents": [
        "7eb3fa1e03b070c55ecbc814e2e3ae4409cf7b1e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 09 15:02:22 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 10 10:48:50 2014 +0100"
      },
      "message": "Plug code generator into liveness analysis.\n\nAlso implement spill slot support.\n\nChange-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc\n"
    },
    {
      "commit": "a7062e05e6048c7f817d784a5b94e3122e25b1ec",
      "tree": "a5d6b64ae6d5352f761fc2547bda863281adbe40",
      "parents": [
        "8b5b1e5593ffa77c393e4172b71a3d5a821d2ed8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu May 22 12:50:17 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 26 11:31:38 2014 +0100"
      },
      "message": "Add a linear scan register allocator to the optimizing compiler.\n\nThis is a \"by-the-book\" implementation. It currently only deals\nwith allocating registers, with no hint optimizations.\n\nThe changes remaining to make it functional are:\n- Allocate spill slots.\n- Resolution and placements of Move instructions.\n- Connect it to the code generator.\n\nChange-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4\n"
    }
  ]
}