)]}' { "log": [ { "commit": "48dee04f4e4214b0fdd8acd0587ef6b08d3d2456", "tree": "aa50172b03bce73ba8d3ef535696c7684d047445", "parents": [ "b5bfa96ff20e86316961327dec5c859239dab6a0" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Oct 22 15:54:12 2014 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Oct 22 15:54:12 2014 +0100" }, "message": "Minor fix in codegen tests.\n\nChange-Id: I9b843536353d4f820b969895d5f75ee9b679aff0\n" }, { "commit": "b5bfa96ff20e86316961327dec5c859239dab6a0", "tree": "c37c4260f59a5eb79b33e3a81142eefc7bc49390", "parents": [ "46bf5e0759e80bbe69130d6731a95fd07e10507c" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Oct 21 18:02:24 2014 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Oct 22 15:20:25 2014 +0100" }, "message": "Add multiplication for floats/doubles in optimizing compiler\n\nChange-Id: I61de8ce1d9e37e30db62e776979b3f22dc643894\n" }, { "commit": "a3d05a40de076aabf12ea284c67c99ff28b43dbf", "tree": "acbe183e7637a333bdaaf0910731b053f2be0f26", "parents": [ "2da28f2a9e79a09a4044521dc4d00320fcdcd041" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 20 17:41:32 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 22 13:49:47 2014 +0000" }, "message": "Implement array creation related DEX instructions.\n\nImplement new-array, filled-new-array, and fill-array-data.\n\nChange-Id: I405560d66777a57d881e384265322617ac5d3ce3\n" }, { "commit": "965ac7e0e6b83dc8bfe3f27305d7029d2febac79", "tree": "876ca908761e59807eecdb668902a38e03a7e55f", "parents": [ "70f4b9929048e71c4231d7976080be6277c3374b", "b762d2ebf9dc604561d9915c96b377235c94960c" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 22 09:16:53 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Oct 22 09:16:54 2014 +0000" }, "message": "Merge \"Various fixes related to integer negate operations.\"" }, { "commit": "b762d2ebf9dc604561d9915c96b377235c94960c", "tree": "aa6060b282db511651908d232a6b16ecbb22b755", "parents": [ "4ff20eba94a2519e5bac57b5f92e04741ea90141" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 22 10:11:06 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 22 10:11:06 2014 +0100" }, "message": "Various fixes related to integer negate operations.\n\n- Emit an RSB instruction for HNeg nodes in the ARM code\n generator instead of RSBS, as we do not need to update the\n condition code flags in this case.\n- Simply punt when trying to statically evaluate a long\n unary operation, instead of aborting.\n- Move a test case to the right place.\n\nChange-Id: I35eb8dea58ed35258d4d8df77181159c3ab07b6f\n" }, { "commit": "1f897b98e19a9b0192a373ee9d3c2fcb4a9463f4", "tree": "d857ca02dec553b30a6fd8d5d39ca88b2ece95ab", "parents": [ "4ff20eba94a2519e5bac57b5f92e04741ea90141" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 17:14:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 17:14:05 2014 +0100" }, "message": "Fix register_allocator_test after reg alloc changes.\n\nChange-Id: Ieaf5daf35efaff6685720a93a442cd7a152f1567\n" }, { "commit": "c8147a76ed2f440f38329dc08ff889d393b5c535", "tree": "bc5b83636edd6c7c6fb170dd8bddc776deefe43f", "parents": [ "8d2c23e0a2d1b449448675e0ba822953cee52b18" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 16:06:20 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 16:51:50 2014 +0100" }, "message": "Fix off by one errors in linear scan register allocator.\n\nChange-Id: I65eea3cc125e12106a7160d30cb91c5d173bd405\n" }, { "commit": "8d2c23e0a2d1b449448675e0ba822953cee52b18", "tree": "4c4862774c2af16316e8909285051d607d5f16d9", "parents": [ "f62819347a8416b42070bf8e5ec64e2eac2fee8d", "102cbed1e52b7c5f09458b44903fe97bb3e14d5f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 15:05:44 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 21 15:05:45 2014 +0000" }, "message": "Merge \"Implement register allocator for floating point registers.\"" }, { "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f", "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a", "parents": [ "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 15 18:31:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 16:03:51 2014 +0100" }, "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n" }, { "commit": "f62819347a8416b42070bf8e5ec64e2eac2fee8d", "tree": "a2b5bc49dbc2bb9128aa165289edbae7f98d1018", "parents": [ "a21bf6e7f64f142f371707c9a06aefdb1d383b5a", "a4a3f407edb824d09588f4dbb5111f3a74c160a9" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 21 14:57:14 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 21 14:57:15 2014 +0000" }, "message": "Merge \"Enable generic JNI for x86 and ARM when interpret-only.\"" }, { "commit": "a4a3f407edb824d09588f4dbb5111f3a74c160a9", "tree": "dc128cf8b733e4aa71182c767f30948b7043c954", "parents": [ "e6798a8340fa4a02bf7719f8c45b04635ff4e9dd" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Oct 20 18:10:34 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 21 07:48:40 2014 -0700" }, "message": "Enable generic JNI for x86 and ARM when interpret-only.\n\nChange-Id: I006ce1ce74acd0f0d53d380e28e409d24d772ea3\n" }, { "commit": "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e", "tree": "5d185a5e8c9b9b07e2ec8a9d0048dd12e0df4eff", "parents": [ "fdc31730353f0b3d3064cdf8b6aacabea26eb4f7", "9240d6a2baa9ed1e18ee08744b461fe49a1ee269" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 21 13:34:59 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 21 13:34:59 2014 +0000" }, "message": "Merge \"Constant folding on unary operations in the optimizing compiler.\"" }, { "commit": "fdc31730353f0b3d3064cdf8b6aacabea26eb4f7", "tree": "26a7a5f64a5e82c10ba7536952bbb9841f6b3a54", "parents": [ "41aae699515430c10ab662945657d98c0febd578", "88cb1755e1d6acaed0f66ce65d7a2a4465053342" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 21 13:28:20 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 21 13:28:21 2014 +0000" }, "message": "Merge \"Implement int negate instruction in the optimizing compiler.\"" }, { "commit": "9240d6a2baa9ed1e18ee08744b461fe49a1ee269", "tree": "0adc27979a1c30defa16de4142b1d54fac6f93dc", "parents": [ "88cb1755e1d6acaed0f66ce65d7a2a4465053342" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 20 16:47:04 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 21 13:48:41 2014 +0100" }, "message": "Constant folding on unary operations in the optimizing compiler.\n\nChange-Id: I4b77afa2a89f5ad2eedd4d6c0c6c382585419349\n" }, { "commit": "88cb1755e1d6acaed0f66ce65d7a2a4465053342", "tree": "6ffdd07aa75a38eae9376bd95d0991a789cd624c", "parents": [ "1e642b5e5b2958ffc1653f5f42f2d091bbd8549e" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 20 16:36:47 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 21 13:48:32 2014 +0100" }, "message": "Implement int negate instruction in the optimizing compiler.\n\n- Add support for the neg-int (integer two\u0027s complement\n negate) instruction in the optimizing compiler.\n- Add a HNeg node type for control-flow graphs and an\n intermediate HUnaryOperation base class.\n- Generate ARM, x86 and x86-64 code for integer HNeg nodes.\n\nChange-Id: I72fd3e1e5311a75c38a8cb665a9211a20325a42e\n" }, { "commit": "8e3964b766652a0478e8e0e303e8556c997675f1", "tree": "ebae22017d3d3c872642cbc56610f67ff32a861d", "parents": [ "5830247c351a1c40f37666584d6c390f32c31957" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Oct 17 11:06:38 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 11:47:54 2014 +0100" }, "message": "Remove the notion of dies at entry.\n\n- Instead, explicitly say that the output does not overlap.\n- Inputs that must be in a fixed register do die at entry,\n as we know they have a location that others can not take.\n- There is also no need to differentiate between an input move\n and a connecting sibling move - those can be put in the\n same parallel move instruction.\n\nChange-Id: I1b2b2827906601f822b59fb9d6a21d48e43bae27\n" }, { "commit": "1d8cdbc5202378a5f1a4b3a1fba610675ed4dcd5", "tree": "6a1b0f49aee5a97b513bd0becc734d284aa7fb65", "parents": [ "1c1786f193323d3bd706463894001117f3471595" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Sep 22 22:51:09 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Oct 20 16:01:28 2014 -0700" }, "message": "Refactor quick entrypoints\n\nRemove FinishCalleeSaveFrameSetup.\nAssembly routines write down anchor into TLS as well as placing runtime\nmethod in callee save frame.\nSimplify artSet64InstanceFromCode by not computing the referrer from the\nstack in the C++ code.\nMove assembly offset tests next to constant declaration and tidy arch_test.\n\nChange-Id: Iededeebc05e54a1e2bb7bb3572b8ba012cffa1c8\n" }, { "commit": "1e642b5e5b2958ffc1653f5f42f2d091bbd8549e", "tree": "db47f70ec77ed5389a69c62cf88f9f4e4e5590f5", "parents": [ "570d5dd11b4dbf003e628d3f1890649a02365c02", "6c82d40eb142771086f5531998de2273ba5cc08c" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 20 09:37:45 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Oct 20 09:37:46 2014 +0000" }, "message": "Merge \"Have HInstruction::StrictlyDominates compute strict dominance.\"" }, { "commit": "570d5dd11b4dbf003e628d3f1890649a02365c02", "tree": "07e1a46ea8d0b36947cbcc8cb7c1fb49cffbf414", "parents": [ "8946e41dcce414dc3359c23d93e001f91d186612", "75be28332b278cff9039b54bfb228ac72f539ccc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 20 09:34:08 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Oct 20 09:34:09 2014 +0000" }, "message": "Merge \"Revert \"Revert \"Introduce a class to implement optimization passes.\"\"\"" }, { "commit": "e09c0fc7ce4b522f8b3e981572d6fa4954b95878", "tree": "72317cdc0a2189892317218d4adbcaafc96dadcf", "parents": [ "c6b5c6ce846257b86a49ee4bb78eeada0143c9f3", "37c92df53979f9f6ab83155ab9521d554d717161" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Oct 17 17:03:56 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 17 17:03:57 2014 +0000" }, "message": "Merge \"Rename arm64 `Register` to `XRegister`.\"" }, { "commit": "c6b5c6ce846257b86a49ee4bb78eeada0143c9f3", "tree": "a4527da1479611071fe30267d890ca6f206e848e", "parents": [ "0008a6fac0843bf8b86cfed76872d4a935bc7a9b", "a304f97c97d38af73afe6b49259ac4faf0902123" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Oct 17 16:53:05 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 17 16:53:06 2014 +0000" }, "message": "Merge \"Rework arm64 register codes and fix Arm64ManagedRegister tests.\"" }, { "commit": "6c82d40eb142771086f5531998de2273ba5cc08c", "tree": "31eb699ae915d2c58603417eff8a4b71f585070a", "parents": [ "75be28332b278cff9039b54bfb228ac72f539ccc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 13 16:10:27 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Oct 17 17:11:44 2014 +0100" }, "message": "Have HInstruction::StrictlyDominates compute strict dominance.\n\nChange-Id: I3a4fa133268615fb4ce54a0bcb43e0c2458cc865\n" }, { "commit": "75be28332b278cff9039b54bfb228ac72f539ccc", "tree": "a01829ba0412d0f6637a833b41694f0d757d8f43", "parents": [ "ffb078ee815a38123581e706099a3bed65a6cb24" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Oct 17 17:02:00 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Oct 17 17:11:43 2014 +0100" }, "message": "Revert \"Revert \"Introduce a class to implement optimization passes.\"\"\n\nThis reverts commit 1ddbf6d4b37979a9f11a203c12befd5ae8b65df4.\n\nChange-Id: I110a14668d1564ee0604dc958b91394b40da89fc\n" }, { "commit": "415ac88a6471792a28cf2b457fe4ba9dc099396e", "tree": "1a83ac3a5f224568af19fc4bf148d352a1a4e49c", "parents": [ "02e7d4e802248574cee7224fea3352b6e558e4ee" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 30 18:09:14 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 17 15:16:08 2014 +0100" }, "message": "Quick: In GVN, apply modifications early if outside loop.\n\nTo improve GVN performance, apply modifications to blocks\noutside loops during the initial convergence phase. During\nthe post processing phase, apply modifications only to the\nblocks belonging to loops.\n\nAlso clean up the check whether to run the LVN and add the\ncapability to limit the maximum number of nested loops we\nallow the GVN to process.\n\nChange-Id: Ie7f1254f91a442397c06a325d5d314d8f58e5012\n" }, { "commit": "37c92df53979f9f6ab83155ab9521d554d717161", "tree": "fe9ba081a00719b104184f1f3307b88648e5ead9", "parents": [ "a304f97c97d38af73afe6b49259ac4faf0902123" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Oct 17 14:35:27 2014 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Oct 17 14:35:27 2014 +0100" }, "message": "Rename arm64 `Register` to `XRegister`.\n\nThis will avoid naming conflicts in the arm64 port of\nthe optimizing compiler.\n\nChange-Id: Ie736ddd2ddbd2e299058256de28bad5d41c57d6f\n" }, { "commit": "a304f97c97d38af73afe6b49259ac4faf0902123", "tree": "24057389d7adafc7a3634ce446f35977319a15df", "parents": [ "02e7d4e802248574cee7224fea3352b6e558e4ee" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Oct 17 14:35:27 2014 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Oct 17 14:35:27 2014 +0100" }, "message": "Rework arm64 register codes and fix Arm64ManagedRegister tests.\n\nChange-Id: I81ce3bc8a212c9c35be3a41b182ada87b32391ec\n" }, { "commit": "34bacdf7eb46c0ffbf24ba7aa14a904bc9176fb2", "tree": "e8ed8e40c5f7896a9ac01bf7dcc2e56f40cfc804", "parents": [ "7f758228f7904d2f65f06bfbd2b8ecbb8e8c6a9d" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Oct 07 20:23:36 2014 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 17 11:46:45 2014 +0100" }, "message": "Add multiplication for integral types\n\nThis also fixes an issue where we could allocate a pair register even if\none of its parts was already blocked.\n\nChange-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01\n" }, { "commit": "0b5d8511993145a9eeb978172944704dc621dbe9", "tree": "035c08bc2c3979d436f56b8e32840e583d84796d", "parents": [ "dddb8d891adad3f55308a725658134b6c9f5559b", "d4c4d953035d4418126d36517e402f411d6a87f3" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 17 04:37:54 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 17 04:37:55 2014 +0000" }, "message": "Merge \"Some code clean-up.\"" }, { "commit": "d4c4d953035d4418126d36517e402f411d6a87f3", "tree": "735aacf812bbac7c1ae7c0788c1ca6f58cfa82ee", "parents": [ "6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 16 20:31:53 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 16 21:30:37 2014 -0700" }, "message": "Some code clean-up.\n\nChange-Id: I4b745fd5298cd61c793e3b57514b48347bd66c0e\n" }, { "commit": "dddb8d891adad3f55308a725658134b6c9f5559b", "tree": "b1747dff4f90b9454b48dd6143ccf1ff84c6b4c7", "parents": [ "b3f18cf7466f85e15c6b7f005f544867a4d6847a", "d6dee676acdd1ab0aa4e5ba6834ee7c40a6dd8ab" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Fri Oct 17 03:13:06 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 17 03:13:06 2014 +0000" }, "message": "Merge \"dex2oat: Add a --compile-pic option\"" }, { "commit": "b3f18cf7466f85e15c6b7f005f544867a4d6847a", "tree": "62035f08dc38038b74c9796118ae0bab0e7608fb", "parents": [ "cb142101f29a4f1e097f03a220db3da6d4bd679f", "6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 17 02:29:32 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 17 02:29:32 2014 +0000" }, "message": "Merge \"Make ART compile with GCC -O0 again.\"" }, { "commit": "6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3", "tree": "f7a20779e4d665f948c5fbcd26dac0071dafb8d4", "parents": [ "2df6840f68dd18d7dd8dbf53f8b6181bbfdc4fc4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 14 17:41:57 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 16 19:27:28 2014 -0700" }, "message": "Make ART compile with GCC -O0 again.\n\nTidy up InstructionSetFeatures so that it has a type hierarchy dependent on\narchitecture.\nAdd to instruction_set_test to warn when InstructionSetFeatures don\u0027t agree\nwith ones from system properties, AT_HWCAP and /proc/cpuinfo.\nClean-up class linker entry point logic to not return entry points but to\ntest whether the passed code is the particular entrypoint. This works around\nimage trampolines that replicate entrypoints.\nBug: 17993736\n\nChange-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23\n" }, { "commit": "d6dee676acdd1ab0aa4e5ba6834ee7c40a6dd8ab", "tree": "727a86edd5ecbcdf60639b5dff5490e9573b5b56", "parents": [ "58e51f38e2304a08aa9ec380383e0b3614f96a96" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Thu Oct 16 18:36:16 2014 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Thu Oct 16 18:36:16 2014 -0700" }, "message": "dex2oat: Add a --compile-pic option\n\nChange-Id: I80e03613e3b6ac079bcbc7e068bbaae760c364c9\n" }, { "commit": "4ffed256cfae742e36ee735f806137f0d4a2f4b6", "tree": "06732435d32de36c56bf25dea3f1606bf8e45123", "parents": [ "9ab7816aec7264d79750e93021ab8714822a038f", "aa7b8a329561c6e1f05938ddc5e9c4be795cd8a5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 16 18:02:25 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 16 18:02:26 2014 +0000" }, "message": "Merge \"Quick: Avoid node iteration for passes that don\u0027t need it.\"" }, { "commit": "9ab7816aec7264d79750e93021ab8714822a038f", "tree": "c0639b1942b01af7fc8f2effbeb4151c49adbe1a", "parents": [ "dc43794b146283b2ba588db83d1fac1f8a3af6d3", "a78e66a2c0fb1ce75e3a4edaf0d70c0d1647dbad" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 16 18:01:00 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 16 18:01:01 2014 +0000" }, "message": "Merge \"Quick: Handle kMirOpNullCheck in LVN/GVN.\"" }, { "commit": "dc43794b146283b2ba588db83d1fac1f8a3af6d3", "tree": "7b6befbdfe47071ebfde5b627edae339fe9ab6f3", "parents": [ "ec2ea6ff6e3d7816df889454866a28b58ce6e6f5", "92a73aef279be78e3c2b04db1713076183933436" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 16 14:20:58 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 16 14:20:59 2014 +0000" }, "message": "Merge \"Don\u0027t use assembler classes in code_generator.h.\"" }, { "commit": "92a73aef279be78e3c2b04db1713076183933436", "tree": "e73b214fb7d740588f5d065b2e4ff3eb8c527e34", "parents": [ "5c5efc253507eb43265997c9afcd778f72b6cef4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 16 11:12:52 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 16 15:17:44 2014 +0100" }, "message": "Don\u0027t use assembler classes in code_generator.h.\n\nThe arm64 backend uses its own assembler and does not share\nthe same classes as the other backends. To avoid conflicts\nor unnecessary mappings, just don\u0027t use those classes in the\nshared part of the code generator.\n\nChange-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d\n" }, { "commit": "ec2ea6ff6e3d7816df889454866a28b58ce6e6f5", "tree": "41ec0fcacce25807fbc28965fb5e93d6c176c55e", "parents": [ "c15c4066233b644f3086eef80007a7cf878d4867", "633021e6ff6b9a57a374a994e74cfd69275ce100" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Oct 16 13:26:29 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 16 13:26:29 2014 +0000" }, "message": "Merge \"Implement default traversals in CFG \u0026 SSA graph checkers.\"" }, { "commit": "c15c4066233b644f3086eef80007a7cf878d4867", "tree": "b3829f1cc439ce50024eab22cedf7a25eb42b0f9", "parents": [ "dd36b42837b78876eabe86b136474490e3d016cc", "a8069ce1c3caa4f9b1651988986f3732152c186d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Oct 16 13:12:56 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 16 13:12:57 2014 +0000" }, "message": "Merge \"Improve art::SSAChecker::VisitInstruction.\"" }, { "commit": "dd36b42837b78876eabe86b136474490e3d016cc", "tree": "f23efd27c5f30665c4d826be374b0b8d0aab72d3", "parents": [ "1604027a8a87fc100aa3b8899ad710c2f313ca45", "e161a2a60c0325793f04be42a0f05228955ecfdd" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Oct 16 12:59:34 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 16 12:59:35 2014 +0000" }, "message": "Merge \"Do not remove NullChecks \u0026 BoundsChecks in HDeadCodeElimination.\"" }, { "commit": "1604027a8a87fc100aa3b8899ad710c2f313ca45", "tree": "713e558fd08a9b086e68ab500452d35c0a01e241", "parents": [ "f1eb10024d616c15af3b0cd81acabe59131be918", "3a3fd0f8d3981691aa2331077a8fae5feee08dd1" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Oct 16 12:51:34 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 16 12:51:35 2014 +0000" }, "message": "Merge \"Turn constant conditional jumps into unconditional jumps.\"" }, { "commit": "a78e66a2c0fb1ce75e3a4edaf0d70c0d1647dbad", "tree": "03dbbf020e60a01feb2be07f2a678d86d825f82c", "parents": [ "f1eb10024d616c15af3b0cd81acabe59131be918" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 16 13:38:44 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 16 13:38:44 2014 +0100" }, "message": "Quick: Handle kMirOpNullCheck in LVN/GVN.\n\nChange-Id: I0274e98cc61ccd1dbe0bd3e50deeb7d62bd1cb22\n" }, { "commit": "312eb25273dc0e2f8880d80f00c5b0998febaf7b", "tree": "17e5320af33efc462a38fe907e5b526dec39c388", "parents": [ "7baa6f8783b12bb4b159ed4648145be5912215f2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 07 15:01:57 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 15 18:44:33 2014 +0100" }, "message": "Quick: Improve the BBCombine pass.\n\nEliminate exception edges for insns that cannot throw even\nwhen inside a try-block. Run the BBCombine pass before the\nSSA transformation to reduce the compilation time.\n\nBug: 16398693\nChange-Id: I8e91df593e316c994679b9d482b0ae20700b9499\n" }, { "commit": "7baa6f8783b12bb4b159ed4648145be5912215f2", "tree": "bb8bca51183039dcf5f375efebe3534503e29735", "parents": [ "5c5efc253507eb43265997c9afcd778f72b6cef4" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 09 18:01:24 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 15 17:11:24 2014 +0100" }, "message": "Rewrite null check elimination to work on dalvik regs.\n\nAnd move the null check and class init check elimination\nbefore the SSA transformation. The new pass ordering is in\nanticipation of subsequent changes. (An improved class init\ncheck elimination can benefit special method inlining. An\nimproved block combination pass before SSA transformation\ncan improve compilation time.)\n\nAlso add tests for the NCE.\n\nChange-Id: Ie4fb1880e06334a703295aef454b437d58a3e878\n" }, { "commit": "aa7b8a329561c6e1f05938ddc5e9c4be795cd8a5", "tree": "ddef401bac18e2ae346647651f77a64b08d18f9f", "parents": [ "2df6840f68dd18d7dd8dbf53f8b6181bbfdc4fc4" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 15 11:35:44 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 15 11:35:44 2014 +0100" }, "message": "Quick: Avoid node iteration for passes that don\u0027t need it.\n\nChange-Id: Ic1f6796a29ba861cee37a31193e07b497b84eb3f\n" }, { "commit": "423b137214debfa066522763a8e78511d300c8c9", "tree": "0415a50a74aea055e5b22022a8e3a5868816ee12", "parents": [ "2df6840f68dd18d7dd8dbf53f8b6181bbfdc4fc4" ], "author": { "name": "Yevgeny Rouban", "email": "yevgeny.y.rouban@intel.com", "time": "Wed Oct 15 17:32:25 2014 +0700" }, "committer": { "name": "Yevgeny Rouban", "email": "yevgeny.y.rouban@intel.com", "time": "Wed Oct 15 17:32:25 2014 +0700" }, "message": "ART: NullCheckElimination should converge with MIR_IGNORE_NULL_CHECK\n\nIf the MIRGraph::EliminateNullChecksAndInferTypes() function managed\nto prove that some regs are non-null then it sets the flag\nMIR_IGNORE_NULL_CHECK and resets this flag for all the other regs.\nIf some previous optimizations have already set MIR_IGNORE_NULL_CHECK\nthen it can be reset by EliminateNullChecksAndInferTypes. This way\nNullCheckElimination discards some optimization efforts.\nOptimization passes should not reset MIR_IGNORE_NULL_CHECK unless\nthey 100% sure NullCheck is needed.\n\nThis patch makes the NCE_TypeInference pass merge its own\ncalculated MIR_IGNORE_NULL_CHECK with the one came from previous\noptimizations. Technically NCE_TypeInference calculates the flag\nin a temporary MIR_MARK-th bit by preserving MIR_IGNORE_NULL_CHECK.\nThen at the end of NCE pass MIR_MARK is or-ed with\nMIR_IGNORE_NULL_CHECK.\n\nChange-Id: Ib26997c70ecf2c158f61496dee9b1fe45c812096\nSigned-off-by: Yevgeny Rouban \u003cyevgeny.y.rouban@intel.com\u003e\n" }, { "commit": "6e88ef6b604a7a945a466784580c42e6554c1289", "tree": "1e296564787b51514cf2eca5b732647c1a82912e", "parents": [ "58e51f38e2304a08aa9ec380383e0b3614f96a96" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Oct 14 15:01:24 2014 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Oct 14 15:43:21 2014 -0700" }, "message": "Change MemMap::maps_ to not be global variable\n\nRuntime.exit() was causing globals to get destructed at the same time\nthat another thread was using it for allocating a new mem map.\n\nBug: 17962201\nChange-Id: I400cb7b8141d858f3c08a6fe59a02838c04c6962\n" }, { "commit": "633021e6ff6b9a57a374a994e74cfd69275ce100", "tree": "78755b7e5d90f1374b317cea2193605de9bdd2d9", "parents": [ "a8069ce1c3caa4f9b1651988986f3732152c186d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 01 14:12:25 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 14 14:44:16 2014 +0100" }, "message": "Implement default traversals in CFG \u0026 SSA graph checkers.\n\n- Check CFG graphs using an insertion order traversal.\n- Check SSA form graphs using a reverse post-order traversal.\n\nChange-Id: Ib9062599bdbf3c17b9f213b743274b2d71a9fa90\n" }, { "commit": "a8069ce1c3caa4f9b1651988986f3732152c186d", "tree": "bfeaeefaec1aae17905bb9df72959193a539ca75", "parents": [ "e161a2a60c0325793f04be42a0f05228955ecfdd" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 01 10:48:29 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 14 14:44:16 2014 +0100" }, "message": "Improve art::SSAChecker::VisitInstruction.\n\nActually inspect the uses of an instruction to ensure the\nlatter dominates all of the former, instead of browsing the\ninputs of this instruction (to ensure they dominate the\ninstruction).\n\nAlso check instruction domination with respect to environment\nuses.\n\nChange-Id: I967f34a45f48930607bf9683180d02e7c27b4e06\n" }, { "commit": "e161a2a60c0325793f04be42a0f05228955ecfdd", "tree": "426167496f383ec4343902f01ce0745d4dd1874d", "parents": [ "3a3fd0f8d3981691aa2331077a8fae5feee08dd1" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Oct 03 12:45:18 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 14 14:44:16 2014 +0100" }, "message": "Do not remove NullChecks \u0026 BoundsChecks in HDeadCodeElimination.\n\nRemoving a NullCheck or a BoundsCheck instruction may change\nthe behavior of a program.\n\nChange-Id: Ib2c9beff0cc98c382210e7cc88b1fa9af3c61887\n" }, { "commit": "3a3fd0f8d3981691aa2331077a8fae5feee08dd1", "tree": "7fc5bb817010f0b77c109d8c645c7ec4f6b2e467", "parents": [ "b8f2480853aeca1db33ed623b9a9b2648954906e" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Oct 10 13:56:31 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 14 14:44:16 2014 +0100" }, "message": "Turn constant conditional jumps into unconditional jumps.\n\nIf a condition (input of an art::HIf instruction) is\nconstant (an art::HConstant object), evaluate it at\ncompile time and generate an unconditional branch\ninstruction if it is true (in lieu of a conditional jump).\n\nChange-Id: I262e43ffe66d5c25dbbfa98092a41c8b3c4c75d6\n" }, { "commit": "7cd01f5d496c384874ea8c21eafb2b6479833e6a", "tree": "14850b67072afaa67273c1e9e9b75e8c9c898421", "parents": [ "72ab3cadce5002163783d7b76781b9f26413b773" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 13 18:29:44 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 13 18:29:44 2014 +0100" }, "message": "Add regression test for null check elimination.\n\nPrompted by\n https://android-review.googlesource.com/110090\n\nBug: 17969907\nChange-Id: I938c27cda0681b9431d69baf4eafa7ca2f9b5c9c\n" }, { "commit": "72ab3cadce5002163783d7b76781b9f26413b773", "tree": "987fbbe5317e6a29ecc44e2af88baa1d4488bf4c", "parents": [ "472b1591300912af2430e3299c3b6119624c2849", "cb46ee13a5683c2973244da964887a448e61b6ec" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 13 17:19:04 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Oct 13 17:19:05 2014 +0000" }, "message": "Merge \"Revert \"ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK\"\"" }, { "commit": "cb46ee13a5683c2973244da964887a448e61b6ec", "tree": "ad82945f47b3f5256eb0440e9a398443a6e401a8", "parents": [ "504b7882fbb841787e350f2da54b1fa9171ce82a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 13 15:18:34 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 13 15:18:34 2014 +0000" }, "message": "Revert \"ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK\"\n\nThis reverts commit 504b7882fbb841787e350f2da54b1fa9171ce82a.\n\nChange-Id: I41c7a03c49f7904370a64c6ececc89146ff735c8\n" }, { "commit": "f8e28f575b1382e984edb2e8c9846a27a1bdea10", "tree": "12506af9dc858d842061843570a939e74822b517", "parents": [ "f659bec20db45c809a891ff528fb6aecf2c76149", "476df557fed5f0b3f32f8d11a654674bb403a8f8" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 13 11:36:10 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Oct 13 11:36:11 2014 +0000" }, "message": "Merge \"Use Is*() helpers to shorten code in the optimizing compiler.\"" }, { "commit": "f659bec20db45c809a891ff528fb6aecf2c76149", "tree": "1d51e37668d6dece4668318e7a763ef355152a95", "parents": [ "b71c9d7a6a26070d302b97a95a0fecc0acc73e87", "3d2ec35be5aadecc9d2bbd80394929ba3b36a4bf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 13 10:08:32 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Oct 13 10:08:33 2014 +0000" }, "message": "Merge \"Fix ScopedArenaAllocator::Reset() for Create()d allocators.\"" }, { "commit": "647b1a86f518d8db0331b3d52a96392b7a62504b", "tree": "7370f795ef3c7fbdd2695d23bc6f8171f40f43f1", "parents": [ "acfbbd4df2fc1c79a7102587bebf398f95b5e5de" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 10 11:02:11 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 10 12:26:02 2014 -0700" }, "message": "Fix 2 new sets of clang compiler warnings.\n\nFix issues that are flagged by -Wfloat-equal and -Wmissing-noreturn.\nIn the case of -Wfloat-equal the current cases in regular code are deliberate,\nso the change is to silence the warning. For gtest code the appropriate fix is\nto switch from EXPECT_EQ to EXPECT_(FLOAT|DOUBLE)_EQ.\nThe -Wmissing-noreturn warning isn\u0027t enabled due to a missing noreturn in\ngtest. This issue has been reported to gtest.\n\nChange-Id: Id84c70c21c542716c9ee0c41492e8ff8788c4ef8\n" }, { "commit": "3d2ec35be5aadecc9d2bbd80394929ba3b36a4bf", "tree": "e007e66d240f12782361e998719901145508243f", "parents": [ "acfbbd4df2fc1c79a7102587bebf398f95b5e5de" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 10 15:39:11 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 10 15:40:01 2014 +0100" }, "message": "Fix ScopedArenaAllocator::Reset() for Create()d allocators.\n\nChange-Id: I88cbb329911ed489768772218b49b6f1756ffd86\n" }, { "commit": "71175b7f19a4f6cf9cc264feafd820dbafa371fb", "tree": "5370e7c7c9f7d1edf148a00548cb1334d5118f8d", "parents": [ "b76c5495c4879fcfa0866b1490031a3123baf9ee" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 22:13:55 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Oct 10 11:36:03 2014 +0000" }, "message": "Cleanup baseline register allocator.\n\n- Use three arrays for blocking regsters instead of\n one and computing offsets in that array.]\n- Don\u0027t pass blocked_registers_ to methods, just use the field.\n\nChange-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6\n" }, { "commit": "b76c5495c4879fcfa0866b1490031a3123baf9ee", "tree": "06180f586f6a3de4398091d96cf5d907c4b65a3a", "parents": [ "4471609d86b7e846b26bebe3373707a10c222e71", "360231a056e796c36ffe62348507e904dc9efb9b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Oct 10 11:22:50 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 10 11:22:50 2014 +0000" }, "message": "Merge \"Fix code generation of materialized conditions.\"" }, { "commit": "fc787ecd91127b2c8458afd94e5148e2ae51a1f5", "tree": "ef48c0f511ee9bf4ed85607cc4d530bace7e6cae", "parents": [ "8fa8c904f7c783204a1dc9438429391d256658da" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 21:56:44 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 22:22:46 2014 -0700" }, "message": "Enable -Wimplicit-fallthrough.\n\nFalling through switch cases on a clang build must now annotate the fallthrough\nwith the FALLTHROUGH_INTENDED macro.\nBug: 17731372\n\nChange-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324\n" }, { "commit": "13735955f39b3b304c37d2b2840663c131262c18", "tree": "0a731ac42b8230f9929172fa3e3d8051874e2b18", "parents": [ "25b18bbdaa36ff936eb44f228f0518d4223e9d52" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 08 12:43:28 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 16:05:58 2014 -0700" }, "message": "stdint types all the way!\n\nChange-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08\n" }, { "commit": "bbb1fc6e95f46470979936450b0d3f1e020c5904", "tree": "a967fdce762abfc66109781e7ff01c31250ba5d5", "parents": [ "349e486f5e6c8f8dd482641a27f9e7cce04ea623", "ec1694ddb034c4b86da59e9ba989ac1d8af2845c" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 18:51:11 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 09 18:51:11 2014 +0000" }, "message": "Merge changes Ia0044523,Ieefe83cf\n\n* changes:\n Fix ARM64 build.\n ARM64: Update code after the VIXL 1.6 release.\n" }, { "commit": "d8c3e3608a7b47e82186e4f8118541ef06d9eab2", "tree": "5e3e80e1fc4aa35fb829e869ef10895aadd97ec5", "parents": [ "9e878d50567f624094f3c4940ac3aedbc5eff3b9" ], "author": { "name": "Alexei Zavjalov", "email": "alexei.zavjalov@intel.com", "time": "Wed Oct 08 15:51:59 2014 +0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Oct 09 10:14:58 2014 -0700" }, "message": "ART: X86: GenLongArith should handle overlapped VRs\n\nIn a case, when src and dest VRs are overlapped when we called\nGenLongArith it may cause the incorrect use of regs.\n\nThe solution is to map src to an physical reg and work with this\nreg instead of mem.\n\nRenamed BadOverlap() to PartiallyIntersects() for consistency.\n\nChange-Id: Ia3fc7f741f0a92556e1b2a1b084506662ef04c9d\nSigned-off-by: Katkov, Serguei I \u003cserguei.i.katkov@intel.com\u003e\nSigned-off-by: Alexei Zavjalov \u003calexei.zavjalov@intel.com\u003e\n" }, { "commit": "476df557fed5f0b3f32f8d11a654674bb403a8f8", "tree": "0ca72785e60b3b1152bca0908e6d134c0a30f631", "parents": [ "9e878d50567f624094f3c4940ac3aedbc5eff3b9" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Oct 09 17:51:36 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Oct 09 17:59:50 2014 +0100" }, "message": "Use Is*() helpers to shorten code in the optimizing compiler.\n\nChange-Id: I79f31833bc9a0aa2918381aa3fb0b05d45f75689\n" }, { "commit": "cee7524afa53216fcd13df8122ece495548a829c", "tree": "425ed45eec6823467734e8219b6320f8965e4189", "parents": [ "9e878d50567f624094f3c4940ac3aedbc5eff3b9" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Oct 08 18:41:21 2014 +0100" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 09:21:33 2014 -0700" }, "message": "ARM64: Update code after the VIXL 1.6 release.\n\nWe now leave the assembler buffer management to VIXL.\n\nChange-Id: Ieefe83cf5cf5e1ab8c924b0e7dc03af6a55053ae\n" }, { "commit": "9e878d50567f624094f3c4940ac3aedbc5eff3b9", "tree": "3b4f118d07fcdd8d64308e847e0140c0115448bf", "parents": [ "51205042343fa4852e01919de01fdcf261af510b", "0279ebb3efd653e6bb255470c99d26949c7bcd95" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 15:52:50 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 09 15:52:51 2014 +0000" }, "message": "Merge \"Tidy ELF builder.\"" }, { "commit": "0279ebb3efd653e6bb255470c99d26949c7bcd95", "tree": "d58b29754f7b3c88616e6e4d6c19346821d244ae", "parents": [ "f1f05d303988a5c071c87b760056be8358276c94" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 08 17:27:48 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 08:25:34 2014 -0700" }, "message": "Tidy ELF builder.\n\nDon\u0027t do \"if (ptr)\". Use const. Use DISALLOW_COPY_AND_ASSIGN. Avoid public\nmember variables.\nMove ValueObject to base and use in ELF builder.\nTidy VectorOutputStream to not use non-const reference arguments.\n\nChange-Id: I2c727c3fc61769c3726de7cfb68b2d6eb4477e53\n" }, { "commit": "5229cf17e3240d55f043c0a9308e22d967f897dc", "tree": "ebdce05568bf76a91bcb94dde0f48d2f1ffe11ec", "parents": [ "67c72b8882f539afd1c8643396fce417cadb85d5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 09 14:57:59 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 09 15:28:21 2014 +0100" }, "message": "Quick: Reduce memory usage and improve compile time.\n\nMove the def-block-matrix from Arena to ScopedArena. Remove\nBasicBlockDataFlow::ending_check_v and use a temporary bit\nmatrix instead. Remove unused BasicBlockDataFlow::phi_v.\nAvoid some BitVector::Copy() at the end of null and clinit\ncheck elimination passes when the contents of the source\nBitVector is no longer needed.\n\nChange-Id: I8111b2f8a51e63075aa124b528d61b79b6933274\n" }, { "commit": "67c72b8882f539afd1c8643396fce417cadb85d5", "tree": "44a24ea60e20b4c1cb93d5153dc54ed8c9632ed1", "parents": [ "2072c465cfff077da257bdf14f1f1b2690c946c8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 09 12:26:10 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 09 15:24:51 2014 +0100" }, "message": "Quick: Separate null check elimination and type inference.\n\nChange-Id: I4566ae9354c91ca935481cb4f5b729bba05c1592\n" }, { "commit": "360231a056e796c36ffe62348507e904dc9efb9b", "tree": "a62ff73c11eaa6694649c98e4c2d872e89149b0c", "parents": [ "2072c465cfff077da257bdf14f1f1b2690c946c8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 08 21:07:48 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 15:21:57 2014 +0100" }, "message": "Fix code generation of materialized conditions.\n\nMove the logic for knowing if a condition needs to be materialized\nin an optimization pass (so that the information does not change\nas a side effect of another optimization).\n\nAlso clean-up arm and x86_64 codegen:\n- arm: ldr and str are for power-users when a constant is\n in play. We should use LoadFromOffset and StoreToOffset.\n- x86_64: fix misuses of movq instead of movl.\n\nChange-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3\n" }, { "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f", "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a", "parents": [ "a3c4d72210de174552f47b2d117b1946f274af1e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 11:47:51 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 14:42:13 2014 +0100" }, "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n" }, { "commit": "832336b3c9eb892045a8de1bb12c9361112ca3c5", "tree": "0e8696869a28ee0dee34d130b586b1bf6f072d6e", "parents": [ "f1f05d303988a5c071c87b760056be8358276c94" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 08 15:35:22 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 08 16:00:31 2014 -0700" }, "message": "Don\u0027t copy fill array data to quick literal pool.\n\nCurrently quick copies the fill array data from the dex file to the literal\npool. It then has to go through hoops to pass this PC relative address down\nto out-of-line code. Instead, pass the offset of the table to the out-of-line\ncode and use the CodeItem data associated with the ArtMethod. This reduces\nthe size of oat code while greatly simplifying it.\nUnify the FillArrayData implementation in quick, portable and the interpreters.\n\nChange-Id: I9c6971cf46285fbf197856627368c0185fdc98ca\n" }, { "commit": "7e70b002c4552347ed1af8c002a0e13f08864f20", "tree": "79d5ee5444a5be70130d9a75dd51831c4b15687b", "parents": [ "edc34c88b8f8abd04f9c4668787403608cf0b2d4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 08 11:47:24 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 08 11:57:59 2014 -0700" }, "message": "Header file clean up.\n\nRemove runtime.h from object.h.\nMove TypeStaticIf to its own header file to avoid bringing utils.h into\nallocator.h.\nMove Array::DataOffset into -inl.h as it now has a utils.h dependency.\nFix include issues arising from this.\n\nChange-Id: I4605b1aa4ff5f8dc15706a0132e15df03c7c8ba0\n" }, { "commit": "edc34c88b8f8abd04f9c4668787403608cf0b2d4", "tree": "fac880a131b35baecf0a4582b9ca34a100bcd19b", "parents": [ "254aa0d3f58b56b227077ef32b4606ebc25eaae4", "504b7882fbb841787e350f2da54b1fa9171ce82a" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Wed Oct 08 17:20:31 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Oct 08 17:20:31 2014 +0000" }, "message": "Merge \"ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK\"" }, { "commit": "254aa0d3f58b56b227077ef32b4606ebc25eaae4", "tree": "c8563c3790df02bfcf6442e50e3263f94a39abd1", "parents": [ "1293b6b2adba33e8b5eca5632dd90c9835b2ef42", "8ac41af13c8e48ede6a7c8a3bf2fb1a414326038" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Wed Oct 08 17:20:22 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Oct 08 17:20:23 2014 +0000" }, "message": "Merge \"ART: Fix SelectKind to work with nullptr\"" }, { "commit": "1293b6b2adba33e8b5eca5632dd90c9835b2ef42", "tree": "39ddadb884202293a10c6e95b6d34e420fd67084", "parents": [ "893e855864b7535f7da92f3942d3f88aaa584dd8", "33c17021c74b4e1911851ca89d634d15ed811d8d" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Wed Oct 08 17:19:59 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Oct 08 17:20:00 2014 +0000" }, "message": "Merge \"ART: Fix issues with SplitBlock\"" }, { "commit": "893e855864b7535f7da92f3942d3f88aaa584dd8", "tree": "9e23bad3caab07abe8e09acb6fe0f39e68c889d1", "parents": [ "663796fb14accb722e9b37c4fe8c3d2588680d7e", "9944b3b792103cb72df1953b5502ced9bf128305" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Wed Oct 08 17:19:51 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Oct 08 17:19:52 2014 +0000" }, "message": "Merge \"Fix to MirGraph::GetSSANameWithConst()\"" }, { "commit": "93445689c714e53cabf347da4321ecf3023e926c", "tree": "459c38b3c12b335358278b745f431e68c18d0824", "parents": [ "50940ea8fe668a80c15920d98cae228851ceb990" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Oct 06 19:24:02 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 08 15:25:11 2014 +0100" }, "message": "Fix and improve static evaluation of constant expressions.\n\n- Fix the definition of art::HSub::Evaluate.\n- Qualify Evaluate methods as OVERRIDE.\n- Evaluate comparisons in a deterministic way: if a\n comparison is true, always return 1 (instead of letting\n the compiler return any non-null value).\n- Better exercise static evaluation of constant expressions\n in compiler/optimizing/constant_propagation_test.cc.\n\nChange-Id: I13d0862e5f4eba1275016fb8c3c17e9aff54408b\n" }, { "commit": "33c17021c74b4e1911851ca89d634d15ed811d8d", "tree": "e434700666f2a5c04b063614ebf5d74f3d69ca0f", "parents": [ "41abdb6ec97978df7c6d79abce4efb664c994ce8" ], "author": { "name": "Mathew Zaleski", "email": "mathew.zaleski@intel.com", "time": "Mon Sep 15 09:44:14 2014 -0400" }, "committer": { "name": "Mathew Zaleski", "email": "mathew.zaleski@intel.com", "time": "Wed Oct 08 08:55:47 2014 -0400" }, "message": "ART: Fix issues with SplitBlock\n\nThe SplitBlock is a public interface from MIRGraph to be able to create two\nblocks from one. This interface can be called not just during the control\nflow graph building phase, but later. At that later point, extended instructions\nmay have already been inserted.\n\nFor example, SpecialMethodInliner can insert kMirOpNullCheck and kMirOpNop,\nand then another pass tries to split block that contains this. The DCHECK\nwill fail even though the split is semantically correct.\n\nSigned-off-by: Mathew Zaleski \u003cmathew.zaleski@intel.com\u003e\n\nConflicts:\n\n\tcompiler/dex/mir_graph.cc\n\nChange-Id: I8bb3551407907909cda444a3379da2eb9331b9ff\n" }, { "commit": "50940ea8fe668a80c15920d98cae228851ceb990", "tree": "8aad769b973aba6dfcf97da0b13114340b064ae1", "parents": [ "1000e69b7e11348f2e1d3ba67339616a647f53d7", "7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 08 12:20:28 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Oct 08 12:20:29 2014 +0000" }, "message": "Merge \"Implement method calls using relative BL on ARM64.\"" }, { "commit": "01ef345767ea609417fc511e42007705c9667546", "tree": "8a3cf1b5a576caf212ef31db966b97b6d23aaf98", "parents": [ "a9f2904263581f606a5704f2bb74efcecf7e9f97" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 01 11:32:17 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 21:25:27 2014 +0100" }, "message": "Add trivial register hints to the register allocator.\n\n- Add hints for phis, same as first input, and expected registers.\n- Make the if instruction accept non-condition instructions.\n\nChange-Id: I34fa68393f0d0c19c68128f017b7a05be556fbe5\n" }, { "commit": "7fb49da8ec62e8a10ed9419ade9f32c6b1174687", "tree": "8b1bec67452b84809cecd5645543e1f885ccbd44", "parents": [ "4a1b4679cda2f0d2893b8e3f910c21231849291c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 06 09:12:41 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 20:19:47 2014 +0100" }, "message": "Add support for floats and doubles.\n\n- Follows Quick conventions.\n- Currently only works with baseline register allocator.\n\nChange-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3\n" }, { "commit": "4a1b4679cda2f0d2893b8e3f910c21231849291c", "tree": "be92d292ce3e0a82b2a74d1c9f6a2fa58aec1b84", "parents": [ "0d6102a80ec741d701788decfb701a657d7a98f7", "191c4b1372aef7c0272f8fa3985b55513029e728" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 15:32:24 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 07 15:32:24 2014 +0000" }, "message": "Merge \"Inserting a node must also update its inputs users.\"" }, { "commit": "191c4b1372aef7c0272f8fa3985b55513029e728", "tree": "ea8a2eb84a64b6f808f782ada9ea66ef69e8e764", "parents": [ "41abdb6ec97978df7c6d79abce4efb664c994ce8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 14:14:27 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 16:26:48 2014 +0100" }, "message": "Inserting a node must also update its inputs users.\n\nChange-Id: I55357564b81efcc0cf52fffdf23289696fe27dd1\n" }, { "commit": "0d6102a80ec741d701788decfb701a657d7a98f7", "tree": "541765a4b48b45077e08ca72d2b1c0b65fd562b9", "parents": [ "45eaba56a9d847fed21f215bd9e9cbc2f8a7b14d", "cc8cc7c7e2ba24667c0765b29c4417a5bf1d91c4" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 07 14:26:47 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 07 14:26:48 2014 +0000" }, "message": "Merge \"Propagate optimization flags to kMirOpCheck.\"" }, { "commit": "b6e7206ad7a426adda9cfd649a4ef969607d79d6", "tree": "77d1b0434b64ba5d8569fe70b7c2711ea6ce2f70", "parents": [ "41abdb6ec97978df7c6d79abce4efb664c994ce8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 14:54:48 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 14:54:48 2014 +0100" }, "message": "Fix movw on x86/x86_64 to accept any 16bits immediate.\n\nChange-Id: I282eece0cd497431f207cec61852b4585ed3655c\n" }, { "commit": "41abdb6ec97978df7c6d79abce4efb664c994ce8", "tree": "ec341468d5881c62251a354f31c8081b57e08687", "parents": [ "e9da5d17fb6e8fde383c943c184905d63ed0c644", "7adfcc8cfdf5fe3a8a0aefa08bfc3249fca55c8b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 11:29:10 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 07 11:29:11 2014 +0000" }, "message": "Merge \"Do not use kDiesAtEntry when inputs must be in specific reg.\"" }, { "commit": "7adfcc8cfdf5fe3a8a0aefa08bfc3249fca55c8b", "tree": "51f231854e404edcd2019afa393697a6a08ee9cf", "parents": [ "9800e55b059d4a0fdc0ceebd5652a53f7a8d837a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 12:24:52 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 12:24:52 2014 +0100" }, "message": "Do not use kDiesAtEntry when inputs must be in specific reg.\n\nThe way the register allocator blocks registers currently\ndoes not handle these cases. Since it only applies to x86 for now,\njust ensure such requests cannot happen.\n\nChange-Id: Idfa25532b9b4996a192d05800f56c6e44edd3a8a\n" }, { "commit": "504b7882fbb841787e350f2da54b1fa9171ce82a", "tree": "a65a57afd5b7d850fe8af3c4f693836dcd3b10f2", "parents": [ "92e7b912929528f23abef6b33d9fa6e6bf327ccc" ], "author": { "name": "Yevgeny Rouban", "email": "yevgeny.y.rouban@intel.com", "time": "Wed Oct 01 18:25:28 2014 +0700" }, "committer": { "name": "Yevgeny Rouban", "email": "yevgeny.y.rouban@intel.com", "time": "Tue Oct 07 06:16:52 2014 +0000" }, "message": "ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK\n\nIf the MIRGraph::EliminateNullChecksAndInferTypes() function managed\nto prove that some regs are non-null then it sets the flag\nMIR_IGNORE_NULL_CHECK and resets this flag for all the other regs.\nIf some previous optimizations have already set MIR_IGNORE_NULL_CHECK\nthen it can be reset by EliminateNullChecksAndInferTypes. This way\nNullCheckElimination discards some optimization efforts.\nOptimization passes should not reset MIR_IGNORE_NULL_CHECK unless\nthey 100% sure NullCheck is needed.\n\nThis patch makes the NCE_TypeInference pass be conservative in\nresetting MIR_IGNORE_NULL_CHECK.\n\nChange-Id: I4ea74020968b5c5bd8e3af48211ffd4c6afd7f80\nSigned-off-by: Yevgeny Rouban \u003cyevgeny.y.rouban@intel.com\u003e\n" }, { "commit": "26a25ef62a13f409f941aa39825a51b4d6f0f047", "tree": "aa0ed991cfcea17297e85f74624a44e32e8913cf", "parents": [ "17b1c174dddb1d83018740c2084ab42daa812fff" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 30 13:54:09 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 06 18:52:56 2014 +0100" }, "message": "Add a prepare for register allocation pass.\n\n- Currently the pass just changes the uses of checks to the\n actual values.\n- Also optimize array access, now that inputs can be constants.\n- And fix another bug in the register allocator reveiled by\n this change.\n\nChange-Id: I43be0dbde9330ee5c8f9d678de11361292d8bd98\n" }, { "commit": "9ae0daa60c568f98ef0020e52366856ff314615f", "tree": "e74b9ee49af0b1b202444fdaaca4b39620d962dd", "parents": [ "2d4e89e97812aeca16ff058d7286f29b7549c43a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 30 22:40:23 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 06 16:36:49 2014 +0100" }, "message": "Add support for inputs dying at entry of instructions.\n\n- Start using it in places where it makes sense.\n- Also improve suspend check on arm to use subs directly.\n\nChange-Id: I09ac0589f5ccb9b850ee757c76dcbcf35ee8cd01\n" }, { "commit": "9944b3b792103cb72df1953b5502ced9bf128305", "tree": "e73899948f4df2787d30d0dd5e8366083259388e", "parents": [ "2d4e89e97812aeca16ff058d7286f29b7549c43a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Oct 06 10:58:54 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Oct 06 10:58:54 2014 -0400" }, "message": "Fix to MirGraph::GetSSANameWithConst()\n\nDon\u0027t call ConstantValueWide() for a wide constant if high_word is set,\nas it will DCHECK if you try to get the value for the high word.\n\nChange-Id: I046ee3e6833ceb556a3c2dbc95699882d30d65f9\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "cc8cc7c7e2ba24667c0765b29c4417a5bf1d91c4", "tree": "e73d0dddaaf66edbbcf8dac5a8b3ac85e3ae59b6", "parents": [ "2d4e89e97812aeca16ff058d7286f29b7549c43a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 06 10:52:20 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 06 10:53:33 2014 +0100" }, "message": "Propagate optimization flags to kMirOpCheck.\n\nBug: 17751474\nChange-Id: I9561b641d956e21dac686c7cd414fa0c6a176147\n" }, { "commit": "fc95176845e1db99115202d7f64c03d521ca0aab", "tree": "d63f485c16d1929aa71d302b04a24e1e1985071b", "parents": [ "c226f1417cab34097280e4501ad67b07a23d214a", "62d1ca3182a6cbb921799825f43ad36821233fd7" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Sat Oct 04 00:22:15 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Sat Oct 04 00:22:16 2014 +0000" }, "message": "Merge \"ART: Prepare for ELF64.\"" }, { "commit": "dfaf4c39809035bca7af85d2c51a8bd2f381e58e", "tree": "62d962c53120f0cf6604496c607fa3291b8c2781", "parents": [ "63462448ca4e377074a10a4720aa22f71154dbe9", "7c02e918e752ab36f0b6cab7528f10c0cf55a4ee" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Oct 03 20:51:09 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 03 20:51:09 2014 +0000" }, "message": "Merge \"Quick compiler: Fix ambiguous LoadValue()\"" }, { "commit": "7c02e918e752ab36f0b6cab7528f10c0cf55a4ee", "tree": "704cb9845bbdecc977c8fb31dc0a677450d17303", "parents": [ "b5325e24ca58299b2b011e57e784b2584f99d687" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Oct 03 13:14:17 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Oct 03 13:14:17 2014 -0700" }, "message": "Quick compiler: Fix ambiguous LoadValue()\n\nInternal b/17790197 \u0026 hat tip to Stephen Kyle\n\nThe following custom-edited dex program demonstrated\nincorrect code generation caused by type confusion.\nIn the example, the constant held in v0 is used in both\nfloat and int contexts, and the register class gets\nconfused at the if-eq.\n\n.method private static getInt()I\n .registers 4\n const/16 v0, 100\n const/4 v1, 1\n const/4 v2, 7\n :loop\n if-eq v2, v0, :done\n add-int v2, v2, v1\n goto :loop\n :done\n add-float v3, v0, v1\n return v2\n.end method\n\nThe bug was introduced in c/96499, \"Quick compiler: reference cleanup\"\nThat CL created a convenience variant of LoadValue which selected the\ntarget register type based on the type of the RegLocation. It should\nnot have done so. The type of a RegLocation is the compiler\u0027s best\nguess of the Dalvik type - and Dalvik allows constants to be used\nin multiple type contexts. All code generation utilities must specify\ndesired register class based on the capabilities of the instructions\nto be emitted. In the failing case, OpCmpImmBranch (and\nGenCompareZeroAndBranch) will be using core registers, so the\nLoadValue must specify either kCoreReg or kRefReg.\n\nThe CL deletes the dangerous LoadValue() variant.\n\nChange-Id: Ie4ec6e51b19676dbbb9628c72c8b3473a419e7ec\n" }, { "commit": "62d1ca3182a6cbb921799825f43ad36821233fd7", "tree": "54d9663f5ce10f41e95fe774d4e4841c1a78bbc3", "parents": [ "63462448ca4e377074a10a4720aa22f71154dbe9" ], "author": { "name": "Tong Shen", "email": "endlessroad@google.com", "time": "Wed Sep 03 17:24:56 2014 -0700" }, "committer": { "name": "Tong Shen", "email": "endlessroad@google.com", "time": "Fri Oct 03 11:25:11 2014 -0700" }, "message": "ART: Prepare for ELF64.\n\nOnly expose necessary interface in ElfFile, and move all details into template class ElfFileImpl.\n\nChange-Id: I9df2bbc55f32ba0ba91f4f3d5d0009e84a2ddf74\n" }, { "commit": "7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c", "tree": "17bbfe4d36a5986aa1ca8a7bb2b6945175fd0963", "parents": [ "63462448ca4e377074a10a4720aa22f71154dbe9" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 24 12:42:55 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 03 18:15:33 2014 +0100" }, "message": "Implement method calls using relative BL on ARM64.\n\nChange-Id: I9e5d0b6c100b6cddd6bbb7ab07cff77ab104ea31\n" }, { "commit": "63462448ca4e377074a10a4720aa22f71154dbe9", "tree": "78f40d7490e373649519f14926fbd6b0b6a28088", "parents": [ "b5325e24ca58299b2b011e57e784b2584f99d687", "27cc09337cdff14f592f4e22fd235809ebe0d6a7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 03 17:08:04 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 03 17:08:05 2014 +0000" }, "message": "Merge \"AArch64: oat patches should be 32-bit ints.\"" } ], "next": "27cc09337cdff14f592f4e22fd235809ebe0d6a7" }