)]}' { "log": [ { "commit": "641a473912b3bcaaff2c71070611490b7c547cfc", "tree": "67bf5b2eaaeaf19c6cebac29984b49c19f172f9b", "parents": [ "5555dd1df3c7f3aaea548c3b657b9325538e9780" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Aug 24 13:21:35 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 25 08:59:29 2017 -0700" }, "message": "ART: Fix reference-related warnings\n\nMake some parameters and locals references to avoid unnecessary\ncopies.\n\nBug: 32619234\nTest: m test-art-host\nChange-Id: Idfed600c7c5492a80f72f51424253bcbea824a94\n" }, { "commit": "3ed4a4018ad11ea292cd1e04b0dfe005195d1e3c", "tree": "5b74f3191cf4f4470faf7dab814eb798372f5ad4", "parents": [ "d98350db5c8b1ffc4e63132a40da7943a3dd0ca6", "da483164bac6a630bcdbdd020ca5dec7b131daae" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 24 17:37:04 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 24 17:37:04 2017 +0000" }, "message": "Merge \"Implement OneBit intrinsics for arm64.\"" }, { "commit": "da483164bac6a630bcdbdd020ca5dec7b131daae", "tree": "9490be50c37b617e18c2cce61544ff95f24ee0c2", "parents": [ "86d1db15332571f21bd588efed0de3384269a1c5" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@linaro.org", "time": "Mon Aug 14 13:54:31 2017 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@linaro.org", "time": "Thu Aug 24 13:48:30 2017 +0100" }, "message": "Implement OneBit intrinsics for arm64.\n\nImplemement intrinsics for highestOneBit and lowestOneBit for\njava.lang.Integer and java.lang.Long.\n\nTest: 568-checker-onebit, test_art_target, test_art_host.\nChange-Id: I9d2bd04cb28b739c29811c73939fdbc25007f15a\n" }, { "commit": "23b752b2496536d39b5132ded2c64f48b2891a0d", "tree": "c047c3091af3a36ab18b269f7b1a422c36a8613a", "parents": [ "ae53f10531e559fbbdbe390316b092c6a9c5df39" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Thu Jul 20 14:40:44 2017 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Mon Aug 21 11:50:24 2017 +0100" }, "message": "Remove obsolete code paths from the ARM code generator\n\nAfter the last changes to the ARM code generator, several code paths\nthat handle some HCondition corner cases are rarely executed and are,\nstrictly speaking, unnecessary because the rest of the compiler can do\ntheir job with minimal modifications (and even generate better code),\nbut have been kept in order to minimize the differences with the\nprevious ARM code generator. Now that the latter has been removed, the\nobsolete code paths can be deleted as well (practically without any\nchange in behaviour).\n\nFurthermore, this commit contains a preliminary improved fix for the\nissue checked by the 657-branches test. The proper fix, however, should\nbe in the instruction simplifier or another compiler pass before code\ngeneration.\n\nTest: 657-branches\nTest: test-art-target\nChange-Id: I7d785a1607bc99bff0bfc33050b567a9cf6925c9\n" }, { "commit": "ae53f10531e559fbbdbe390316b092c6a9c5df39", "tree": "14abcc3ef1b8232c662a095736707765b2359ad5", "parents": [ "b28118c74a61b8d1ff9432e753f1f11a72ce049c", "a663d9d5b32a525794a2b98fa43da54dd7c79e3b" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Sat Aug 19 11:52:43 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Sat Aug 19 11:52:43 2017 +0000" }, "message": "Merge \"MIPS32: Allow some patched instructions in delay slots\"" }, { "commit": "a663d9d5b32a525794a2b98fa43da54dd7c79e3b", "tree": "88c643ca5ebfb0dfe11f45a9b232f9a2592fb043", "parents": [ "b9463674919ba91fe131e65785ad67b4202e86b9" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jul 31 18:43:18 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Aug 18 15:29:31 2017 -0700" }, "message": "MIPS32: Allow some patched instructions in delay slots\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest32\nTest: testrunner.py --target --optimizing --32\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0\n" }, { "commit": "5011149cbb1dddf7161ef294b8ed265862ae6d91", "tree": "e420ba6336d69308e73ead7ff7984d4c08e7bcf8", "parents": [ "65ee0f086581a8fbaa18473e8bac7ff9372cff0a", "2dec927e60395210946e5b9dbaa03111dad2466a" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 18 11:59:14 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 18 11:59:14 2017 +0000" }, "message": "Merge \"MIPS64: Implement HSelect\"" }, { "commit": "f708c9a39240716eb3df024ec67bbcb9b3883f61", "tree": "00d78ed6994c79e08c829416fe0ea03dc145b6f0", "parents": [ "2ade881db8642f10007c1c46b5e7f073d463c2d3", "0cab65610a6a984a94ef4c3f232fe0273e78d95b" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 17 14:40:46 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 17 14:40:46 2017 +0000" }, "message": "Merge \"MIPS: Eliminate hard-coded offsets in branches\"" }, { "commit": "5bfead584f56b2a1cfb69f78c385965ec57f7e8b", "tree": "e349bd5c78599475a07f463bd7aca0d68c0a495e", "parents": [ "6b1382dcb24a44e552daaa8dca82eb63d8bf6b11", "bc5460b850a0fa2d8dcf6c8d36b0eb86f8fe46a8" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Aug 14 22:46:20 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 14 22:46:20 2017 +0000" }, "message": "Merge \"MIPS: Support MultiplyAccumulate for SIMD.\"" }, { "commit": "4ec14ff3d6126750de753f7d162df408f278e825", "tree": "9f37b3881e615211a4fd458ee36d67939c6da514", "parents": [ "c1bb1cd339b2ebea9c4770fb4d61bacd7d77746f", "16e528957869c7debb1f6758c9a364819e15ee1a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Aug 14 09:19:03 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 14 09:19:03 2017 +0000" }, "message": "Merge \"RFC: Generate select instruction for conditional returns.\"" }, { "commit": "bc5460b850a0fa2d8dcf6c8d36b0eb86f8fe46a8", "tree": "0db1314987cd0f24c7294c4ad540c7f28e2739d9", "parents": [ "c1bb1cd339b2ebea9c4770fb4d61bacd7d77746f" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 20 16:07:36 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Aug 14 10:16:34 2017 +0200" }, "message": "MIPS: Support MultiplyAccumulate for SIMD.\n\nMoved support for multiply accumulate from arm64-specific to\ngeneral instruction simplification.\nAlso extended 550-checker-multiply-accumulate test.\n\nTest: test-art-host, test-art-target\n\nChange-Id: If113f0f0d5cb48e8a76273c919cfa2f49fce667d\n" }, { "commit": "e9b61bac34bea439d8ce39592973a66a32f43fb7", "tree": "aa0043f331844ba6083b764c7bce8c2a81671058", "parents": [ "675c779cb046bca49229e1e5268d0eb622159214", "6ef45677305048c2bf0600f1c4b98a11b2cfaffb" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 11 19:29:31 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 11 19:29:31 2017 +0000" }, "message": "Merge changes Ic119441c,I83b96b41\n\n* changes:\n optimizing: Add statistics for # of constructor fences added/removed\n optimizing: Refactor statistics to use OptimizingCompilerStats helper\n" }, { "commit": "6ef45677305048c2bf0600f1c4b98a11b2cfaffb", "tree": "9a8df6a3bebe4a6120403562c21817d775a6ef36", "parents": [ "1e065a54845da12541572f4f149e6ab0dcd20180" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue Aug 08 13:59:55 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Fri Aug 11 10:23:30 2017 -0700" }, "message": "optimizing: Add statistics for # of constructor fences added/removed\n\nStatistics are attributed as follows:\n\nAdded because:\n* HNewInstances requires a HConstructorFence following it.\n* HReturn requires a HConstructorFence (for final fields) preceding it.\n\nRemoved because:\n* Optimized in Load-Store-Elimination.\n* Optimized in Prepare-For-Register-Allocation.\n\nTest: art/test.py\nBug: 36656456\nChange-Id: Ic119441c5151a5a840fc6532b411340e2d68e5eb\n" }, { "commit": "1e065a54845da12541572f4f149e6ab0dcd20180", "tree": "061d28c8905c7bc8ac50c8c86f4073034afb5ba2", "parents": [ "f573972a087b798f74bf5404e271355a2805e100" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Wed Aug 09 13:20:34 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Fri Aug 11 10:23:07 2017 -0700" }, "message": "optimizing: Refactor statistics to use OptimizingCompilerStats helper\n\nRemove all copies of \u0027MaybeRecordStat\u0027, replacing them with a single\nOptimizingCompilerStats::MaybeRecordStat helper.\n\nChange-Id: I83b96b41439dccece3eee2e159b18c95336ea933\n" }, { "commit": "52b450bd928a4096e7d9bed768757b41f4ed82e1", "tree": "e198348e61668e7ec54f8e67d9d8aee10cb5c75e", "parents": [ "54636c0e85ad1bcd5798324c0484122364e99298", "5daa4950038a4329ac745059f1ad0927d4a60166" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 11 13:34:55 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 11 13:34:55 2017 +0000" }, "message": "Merge \"Instrument ARM generated code to check the Marking Register.\"" }, { "commit": "5daa4950038a4329ac745059f1ad0927d4a60166", "tree": "48fdf4d85953e931bd455ede290e769979e3906c", "parents": [ "2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 03 17:23:56 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 11 11:44:50 2017 +0100" }, "message": "Instrument ARM generated code to check the Marking Register.\n\nGenerate run-time code in the Optimizing compiler checking that\nthe Marking Register\u0027s value matches `self.tls32_.is.gc_marking`\nin debug mode (on target; and on host with JIT, or with AOT when\ncompiling the core image). If a check fails, abort.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM device/emulator boot test with libartd\nBug: 37707231\nChange-Id: I903f44d385d66ff74d65aa09d7113aa9cb7b9f24\n" }, { "commit": "54636c0e85ad1bcd5798324c0484122364e99298", "tree": "6ec47505bdb6dd232cf43b86eb9d2c438d2f052f", "parents": [ "abafaf83838301b83832c33324d683e7f77aff76", "2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 11 10:26:39 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 11 10:26:39 2017 +0000" }, "message": "Merge \"Instrument ARM64 generated code to check the Marking Register.\"" }, { "commit": "eac21ef2617cc02e6a093d811a926115fb69bd05", "tree": "b9ea86a35a870669029e6375e2a01e5f90297212", "parents": [ "73de4a8f0936bfb8b74db0465f277a2b68d16905", "1545ccc4852255870b5c4676203fc7c2f2fa393f" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Thu Aug 10 22:45:45 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 10 22:45:45 2017 +0000" }, "message": "Merge \"scheduler should not schedule volatile field accesses.\"" }, { "commit": "1545ccc4852255870b5c4676203fc7c2f2fa393f", "tree": "5e983b1ece6e6d7af3cd2d476bdbcac6ebb49631", "parents": [ "3b21019edb5586a73516833482fc203e75309dbe" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Aug 08 15:24:26 2017 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Thu Aug 10 14:10:06 2017 -0700" }, "message": "scheduler should not schedule volatile field accesses.\n\nUnresolved field accesses are not scheduled either since it\u0027s not know\nwhether they are volatile or not, and they are already expensive anyway.\n\nTest: 706-checker-scheduler\nChange-Id: Ie736542590a2459ee9b597e090fbedd4b527782a\n" }, { "commit": "73de4a8f0936bfb8b74db0465f277a2b68d16905", "tree": "76ad27c460c92ea15cc6a55ce1d770d7b58ef3a8", "parents": [ "461ec567f16039374dff35e2f3b808986c100249", "671e48a4895cc1a0b7a1458d608f8c4f9b5cf85c" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 10 19:42:31 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 10 19:42:31 2017 +0000" }, "message": "Merge \"Fix performance regression.\"" }, { "commit": "671e48a4895cc1a0b7a1458d608f8c4f9b5cf85c", "tree": "143dbcf6352af8942ae1c6d253dd6561474b6ecf", "parents": [ "1bd8e5a1b2055e0ff7977ba7e149534d2ee0a696" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Aug 09 13:16:56 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 10 11:00:05 2017 -0700" }, "message": "Fix performance regression.\n\nRationale:\nOne \"improvement\" overlooked in the previous CL hoists\na try-test out of the optimization to make sure we don\u0027t\nchange HIR when not needed. However, the try-test may\naffect the outcome of the test, so that was bad, bad!\n\nBug: 64091002\nTest: test-art-host\nChange-Id: Icf5f73e7cbeb209ee5fa5f6c1bef64fe127bb2fd\n" }, { "commit": "2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40", "tree": "4d5fb728acd7f98f8949c84364375a804ff0ba63", "parents": [ "461ec567f16039374dff35e2f3b808986c100249" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jun 06 16:09:59 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 10 18:17:47 2017 +0100" }, "message": "Instrument ARM64 generated code to check the Marking Register.\n\nGenerate run-time code in the Optimizing compiler checking that\nthe Marking Register\u0027s value matches `self.tls32_.is.gc_marking`\nin debug mode (on target; and on host with JIT, or with AOT when\ncompiling the core image). If a check fails, abort.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test with libartd.\nBug: 37707231\nChange-Id: Ie9b322b22b3d26654a06821e1db71dbda3c43061\n" }, { "commit": "16e528957869c7debb1f6758c9a364819e15ee1a", "tree": "050d42754ce9bca3c3e23652093cd209ae59ea53", "parents": [ "1d2d8b1b6b359f5f476ef78662baa4b8782be530" ], "author": { "name": "Mads Ager", "email": "ager@google.com", "time": "Fri Jul 14 13:11:37 2017 +0200" }, "committer": { "name": "Mads Ager", "email": "ager@google.com", "time": "Thu Aug 10 14:04:04 2017 +0200" }, "message": "RFC: Generate select instruction for conditional returns.\n\nThe select generator currently only inserts select instructions\nif there is a diamond shape with a phi.\n\nThis change extends the select generator to also deal with the\npattern:\n\n if (condition) {\n movable instruction 0\n return value0\n } else {\n movable instruction 1\n return value1\n }\n\nwhich it turns into:\n\n moveable instruction 0\n moveable instruction 1\n return select (value0, value1, condition)\n\nTest: 592-checker-regression-bool-input\nChange-Id: Iac50fb181dc2c9b7619f28977298662bc09fc0e1\n" }, { "commit": "dbd05fe1a6ed2c3e23c9f6b372dd439ad59e777b", "tree": "81968f4f0a16cb37b57933be5cea6542795488a1", "parents": [ "1d2d8b1b6b359f5f476ef78662baa4b8782be530" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu Aug 10 11:41:35 2017 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu Aug 10 11:57:53 2017 +0100" }, "message": "Revert recent JIT code cache changes\n\nFlakiness observed on the bots.\n\nRevert \"Jit Code Cache instruction pipeline flushing\"\nThis reverts commit 56fe32eecd4f25237e66811fd766355a07908d22.\n\nRevert \"ARM64: More JIT Code Cache maintenace\"\nThis reverts commit 17272ab679c9b5f5dac8754ac070b78b15271c27.\n\nRevert \"ARM64: JIT Code Cache maintenance\"\nThis reverts commit 3ecac070ad55d433bbcbe11e21f4b44ab178effe.\n\nRevert \"Change flush order in JIT code cache\"\nThis reverts commit 43ce5f82dae4dc5eebcf40e54b81ccd96eb5fba3.\n\nRevert \"Separate rw from rx views of jit code cache\"\nThis reverts commit d1dbb74e5946fe6c6098a541012932e1e9dd3115.\n\nTest: art/test.py --target --64\nBug: 64527643\nBug: 62356545\nChange-Id: Ifa10ac77a60ee96e8cb68881bade4d6b4f828714\n" }, { "commit": "80dd7567f76aa4cc28a846cb8f0549b57e47fe47", "tree": "b60719920f257f2cf9b4f2a36cdf02a024342c29", "parents": [ "a27a718f3aa89399af353b272f76d3b4fe89ed17", "179861c7e8bb4f5f1b44e7588fc8791446c30ae5" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Thu Aug 10 06:23:55 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 10 06:23:55 2017 +0000" }, "message": "Merge \"Run HeapLocationCollector once in scheduler instead of locally.\"" }, { "commit": "179861c7e8bb4f5f1b44e7588fc8791446c30ae5", "tree": "b4310dc30bfb5f161af6e8bcee8b8a39baa449ad", "parents": [ "3b21019edb5586a73516833482fc203e75309dbe" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Fri Aug 04 13:21:31 2017 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Aug 09 13:30:21 2017 -0700" }, "message": "Run HeapLocationCollector once in scheduler instead of locally.\n\nHeapLocationCollector does alias analysis globally instead of at block\nscale. For example doing it locally breaks the pre-existence based alias\nanalysis. It\u0027s also expensive to do it for each basic block.\n\nTest: run-test/gtest on target/host, 662-regression-alias\nBug: 64018485\nChange-Id: If001e2961b5a52b50b1bcefd5e4a89d9c25f25b8\n" }, { "commit": "785e3555685279767f52f1280ea13ba35b112e86", "tree": "5e67791a67b94324852b35b52efcc6a3d2b94c0c", "parents": [ "a97a14fa206bc8175d785c7fb1ee4e81ec4d100d", "b29f684b74216e8d652c48ab9f86cc7d1b327e54" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Aug 08 19:59:53 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 08 19:59:53 2017 +0000" }, "message": "Merge \"Set basic framework for detecting reductions.\"" }, { "commit": "b29f684b74216e8d652c48ab9f86cc7d1b327e54", "tree": "393839a3b0e3d3aa0fde20beaef846303ce098c7", "parents": [ "bf3710ecec95b2716d1c706b5661192dd9ea6c66" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jul 28 15:58:41 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Aug 08 11:11:00 2017 -0700" }, "message": "Set basic framework for detecting reductions.\n\nRationale:\nRecognize reductions in loops. Note that reductions are *not*\noptimized yet (we would proceed with e.g. unrolling and vectorization).\nThis CL merely sets up the basic detection framework. Also does\na bit of cleanup on loop optimization code.\n\nBug: 64091002\nTest: test-art-host\n\nChange-Id: I0f52bd7ca69936315b03d02e83da743b8ad0ae72\n" }, { "commit": "a22cae7039a3cf23318a9fd79a07bf0ef201d5e9", "tree": "e88f36e78efe2c4349f2a86e4545741c520367e6", "parents": [ "69223111c078f86dab4b2f265c8155b8628bf530" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon Jun 26 17:49:48 2017 +0100" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Tue Aug 08 17:28:58 2017 +0100" }, "message": "HRem support in BCE.\n\nThis CL improves BCE by adding support for handling\n\u0027i % CONST\u0027 format in array index.\n\nDevelopers would write array[i%array.length] or array[i%SIZE] format\narray accesses in code. There are several such cases in Android\nframework and libcore.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: bounds_check_elimination_test\nTest: 449-checker-bce\n\nChange-Id: I9fc3e15dcaaa48c8607a2c486d11c8269932185e\n" }, { "commit": "5aedbcd3d0a1a60643db3e904254e0a3060599bf", "tree": "3d136637c0ef0cb12093d6f412fe1ec7e7a26e7e", "parents": [ "c7c25d5b4cf243cbbf06f2e4302a0faa5eccb42a", "c73ee37b76494253862ee17933acfe2b88de1a01" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Aug 07 17:23:38 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 07 17:23:38 2017 +0000" }, "message": "Merge \"ART: Fix loop header\u0027s predecessors reordering in SimplifyLoops.\"" }, { "commit": "d88a2b5cf4ce61bf86ce5c16d5f4d5687011dc91", "tree": "d21afa1caaff08f18d55af967753cc7a912069e5", "parents": [ "443dbfcf39743f4fd5f1c517a28326ceb97136af", "895f92218f705ff8ad9c47b8be0c093130d9fbbc" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 04 23:21:45 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 04 23:21:45 2017 +0000" }, "message": "Merge \"ART: Fix up small header includes\"" }, { "commit": "2aa1d0b4b3eb4805ddaf6516015b9d2393707000", "tree": "ed1fa3ce80427201efa612247c237ba5e7dc7300", "parents": [ "8f13b262bd71c00ac17fca0aedd05771f46900cd", "1f0eefc59d34fb5b6f088791cdd268a5ee194407" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Fri Aug 04 20:18:10 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 04 20:18:10 2017 +0000" }, "message": "Merge \"Add VisitNewArray() in lsa.\"" }, { "commit": "895f92218f705ff8ad9c47b8be0c093130d9fbbc", "tree": "de590436a5feb2db183e3f3e35e29817c5ea3fb6", "parents": [ "c116154a4aae8ed1608a15ac602f8bd69d8ca0ff" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 05 09:53:32 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 04 07:31:52 2017 -0700" }, "message": "ART: Fix up small header includes\n\nTest: m\nChange-Id: I6978d6eb4b95a6ee810e5a48ca6f5d6c590d4ce1\n" }, { "commit": "1f0eefc59d34fb5b6f088791cdd268a5ee194407", "tree": "d8511d10a121b52830f132824ef5b984223ae82b", "parents": [ "52a3c989f96984f9bc9e02620694fc44708a1df2" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Thu Aug 03 16:43:40 2017 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Thu Aug 03 16:51:50 2017 -0700" }, "message": "Add VisitNewArray() in lsa.\n\nWe missed one VisitNewArray() to create reference info right when a\nNewArray is seen. This may break pre-existence based aliasing analysis\nsince another reference may be wrongly treated as existing before the\nNewArray.\n\nAlso doing the same for a few more nodes that have reference values.\nThis is not correctness issue but can open up more opportunities for\ndetecting false aliases.\n\nTest: run-test on host.\nBug: 64018485\nChange-Id: I11f7857ab6b933448e7ba9ab6451d77dfc5c61a7\n" }, { "commit": "c73ee37b76494253862ee17933acfe2b88de1a01", "tree": "f88685e10a1075748c7634c8ec913544f2b12068", "parents": [ "399492a86198b42fded9ac1f4aa61c82869328eb" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Jul 31 15:08:40 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Aug 03 17:12:31 2017 +0100" }, "message": "ART: Fix loop header\u0027s predecessors reordering in SimplifyLoops.\n\nFix the issue when after loop header\u0027s predecessors reordering in\nSimplifyLoops phi inputs are not reordered correspondingly.\n\nTest: loop_optimization_test.cc, test-art-host, test-art-target.\n\nChange-Id: I8a251a0a953d751f9bb67da58181e47d225d90e6\n" }, { "commit": "e829831cd515d3471d78c159522895137442aacb", "tree": "43de4247c9d8b8d6298e67e983e3da0ff2286d99", "parents": [ "83c0fefa60998a9f344dd21c968234e40c8be965" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 03 09:51:25 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 03 09:35:00 2017 +0000" }, "message": "Fix null dereference in debug check.\n\nSpotted by Ivan Maidanski.\n\nSigned-off-by: Ivan Maidanski \u003ci.maidanski@samsung.com\u003e\n\ntest: test.py\nChange-Id: Icfb1c101ba59aad3a241dbf6474634e6147bb6c4\n" }, { "commit": "2dec927e60395210946e5b9dbaa03111dad2466a", "tree": "2c983497c7dc23c02f08f6c302ee99a2cb992a9b", "parents": [ "4a9ab7d61f3933cbe26f01d7dc5bda1e65dcd567" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Aug 02 11:41:26 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Aug 03 07:34:07 2017 +0200" }, "message": "MIPS64: Implement HSelect\n\nTest: mma test-art-host-gtest\nTest: mma test-art-target-gtest in QEMU (MIPS64R6)\nTest: ./testrunner.py --target --optimizing in QEMU (MIPS64R6)\n\nChange-Id: I633fc479e0ca61b7d49b4c36fbe5db9a94da535d\n" }, { "commit": "21c7e6fbcabef2f22b467e1e89f4abe1aa43e459", "tree": "1a62fe2485d9642ee3d8768c6edd005278b1014f", "parents": [ "2e53f8f69f8c4175085e337445ec42aa045a2f7f" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Jul 27 16:04:42 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Aug 01 11:35:23 2017 +0100" }, "message": "ART: Fix SimplifyInduction for an instruction with HEnvironment.\n\nAfter an instruction is removed during RemoveFromCycle its\nenvironment isn\u0027t properly cleaned: it still has input instructions\npresent and registered (those instructions still hold records for\nthat).\n\nTest: test-art-target, test-art-host.\nChange-Id: Iea315bdf735d75fe477f43671f05b40dfecc63a8\n" }, { "commit": "0cab65610a6a984a94ef4c3f232fe0273e78d95b", "tree": "669fa607f4cd9ad8eef9223bb124fb72265a06b3", "parents": [ "2e53f8f69f8c4175085e337445ec42aa045a2f7f" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jul 25 15:19:36 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Jul 30 20:09:26 2017 -0700" }, "message": "MIPS: Eliminate hard-coded offsets in branches\n\nThe bulk of the change is in the assemblers and their\ntests.\n\nThe main goal is to introduce \"bare\" branches to labels\n(as opposed to the existing bare branches with relative\noffsets, whose direct use we want to eliminate).\nThese branches\u0027 delay/forbidden slots are filled\nmanually and these branches do not promote to long (the\nbranch target must be within reach of the individual\nbranch instruction).\n\nThe secondary goal is to add more branch tests (mainly\nfor bare vs non-bare branches and a few extra) and\nrefactor and reorganize the branch test code a bit.\n\nThe third goal is to improve idiom recognition in the\ndisassembler, including branch idioms and a few others.\n\nFurther details:\n- introduce bare branches (R2 and R6) to labels, making\n R2 branches available for use on R6\n- make use of the above in the code generators\n- align beqz/bnez with their GNU assembler encoding to\n simplify and shorten the test code\n- update the CFI test because of the above\n- add trivial tests for bare and non-bare branches\n (addressing existing debt as well)\n- add MIPS32R6 tests for long beqc/beqzc/bc (debt)\n- add MIPS64R6 long beqzc test (debt)\n- group branch tests together\n- group constant/literal/address-loading tests together\n- make the disassembler recognize:\n - b/beqz/bnez (beq/bne with $zero reg)\n - nal (bltzal with $zero reg)\n - bal/bgezal (bal \u003d bgezal with $zero reg)\n - move (or with $zero reg)\n - li (ori/addiu with $zero reg)\n - dli (daddiu with $zero reg)\n- disassemble 16-bit immediate operands (in andi, ori,\n xori, li, dli) as signed or unsigned as appropriate\n- drop unused instructions (bltzl, bltzall, addi) from\n the disassembler as there are no plans to use them\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I62b74a6c00ce0651528114806ba24a59ba564a73\n" }, { "commit": "67abbca7cf23ef8b5c0aded0cd0a20765ff47cf2", "tree": "14eda472e47c476cc94f04283bc9eb7dba31c1c7", "parents": [ "078a27af849f55fc903da8f291315504618f2207", "b45528c1f1b83ca8c970f439b54fbfcfda6908ea" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 27 17:02:31 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 27 17:02:31 2017 +0000" }, "message": "Merge \"ART: Refactor retrieval of types through ArtMethod.\"" }, { "commit": "b45528c1f1b83ca8c970f439b54fbfcfda6908ea", "tree": "e8f493a7b21064d353d112ea1378d7819db385aa", "parents": [ "2c2e13ec24bff70db6e49270b9d4d787add9925e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 27 14:14:28 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 27 15:30:47 2017 +0100" }, "message": "ART: Refactor retrieval of types through ArtMethod.\n\nSplit Get*() functions that take a \"bool resolve\"\nargument into Lookup*() and Resolve*() functions.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: I0b7eaa1fadc2ffa8c0168203790467f91a126963\n" }, { "commit": "71da4878f2e3f0dc8b7c3a31b4f57172fde5f378", "tree": "ae560b5e56ce09cfaaf1f3c04e96366f193c4180", "parents": [ "b22ae40038aeeebb16936fbf62b48f080d6e7ef4" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 26 10:02:07 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 26 11:23:03 2017 -0700" }, "message": "ART: Move simulator to art/\n\nMove the simulator library out of the runtime directory. Let\u0027s not\npollute the runtime library.\n\nTest: m\nChange-Id: I351a0061ae628c3af0462b72d4de727db296ec23\n" }, { "commit": "03ce1df8f9b1b8d207fc685fd084b96697a50182", "tree": "226b0b4a98af714d848796b8c083f134f6a80fd4", "parents": [ "ff80dfc82a3e5177d45099c090e33f1a060f9152", "786120815be223290f1cb24e88c1be9d044c8dca" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 25 08:31:12 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 25 08:31:12 2017 +0000" }, "message": "Merge \"Fix x86 and x64 codegens for 8/16 stores.\"" }, { "commit": "ff80dfc82a3e5177d45099c090e33f1a060f9152", "tree": "9ee750c2766161d310a625450ada830bc91230b2", "parents": [ "9710fbaea9022149887da4459b47011a803c76fb", "56fe32eecd4f25237e66811fd766355a07908d22" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jul 25 08:23:46 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 25 08:23:46 2017 +0000" }, "message": "Merge \"Jit Code Cache instruction pipeline flushing\"" }, { "commit": "8cf9cb386cd9286d67e879f1ee501ec00d72a4e1", "tree": "88e86e214b425e444760fe4e0ffeee677e1558a2", "parents": [ "914b7b6a6c9f399b26b41e9160e9871ef749e0db" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 19 09:28:38 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jul 24 16:07:10 2017 -0700" }, "message": "ART: Include cleanup\n\nLet clang-format reorder the header includes.\n\nDerived with:\n\n* .clang-format:\n BasedOnStyle: Google\n IncludeIsMainRegex: \u0027(_test|-inl)?$\u0027\n\n* Steps:\n find . -name \u0027*.cc\u0027 -o -name \u0027*.h\u0027 | xargs sed -i.bak -e \u0027s/^#include/ #include/\u0027 ; git commit -a -m \u0027ART: Include cleanup\u0027\n git-clang-format -style\u003dfile HEAD^\n manual inspection\n git commit -a --amend\n\nTest: mmma art\nChange-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02\n" }, { "commit": "56fe32eecd4f25237e66811fd766355a07908d22", "tree": "7c2c75d54edf0865598c106cb013f8c3794bd767", "parents": [ "84b65e977302e1cf16d188636c22c164c7793554" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri Jul 21 11:42:10 2017 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Mon Jul 24 17:29:40 2017 +0100" }, "message": "Jit Code Cache instruction pipeline flushing\n\nRestores instruction pipeline flushing on all cores following crashes\non ARMv7 with dual JIT code page mappings. We were inadvertantly\ntoggling permission on a non-executable page rather than executable.\n\nRemoves the data cache flush for roots data and replaces it with a\nsequentially consistent barrier.\n\nFix MemMap::RemapAtEnd() when all pages are given out. To meet\ninvariants checked in the destructor, the base pointer needs to be\nassigned as nullptr when this happens.\n\nBug: 63833411\nBug: 62332932\nTest: art/test.py --target\nChange-Id: I705cf5a3c80e78c4e912ea3d2c3c4aa89dee26bb\n" }, { "commit": "786120815be223290f1cb24e88c1be9d044c8dca", "tree": "556be2e1337a82ed7c7b4b419520bef6569e2fd7", "parents": [ "ad76ef641d8570affb2e3c728b40876c4ed53fac" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 24 14:18:53 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 24 15:01:56 2017 +0100" }, "message": "Fix x86 and x64 codegens for 8/16 stores.\n\nTest: 660-store-8-16\nChange-Id: I6124818894205ebeed83929f3ff00bf2733292bf\n" }, { "commit": "ad76ef641d8570affb2e3c728b40876c4ed53fac", "tree": "3be2b0da866469391593f6c5142c6e4937d5a2d9", "parents": [ "28e535bd94c84d1019f18c46e189928435e2938d", "bf9e21a33404440e1723e738975e23f7c1334e18" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jul 24 11:33:49 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 24 11:33:49 2017 +0000" }, "message": "Merge \"Improve SchedulingLatencyVisitorARM on HCondition latency settings.\"" }, { "commit": "bf9e21a33404440e1723e738975e23f7c1334e18", "tree": "c25c5a814530c949745aa1f170505319f57a0d0e", "parents": [ "89ae0f42e38a2f985ac404830f2a05fecf9547e2" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Thu Jun 15 11:01:11 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 21 13:50:00 2017 +0000" }, "message": "Improve SchedulingLatencyVisitorARM on HCondition latency settings.\n\nTest: m test-art-host\nTest: m test-art-target\n\nChange-Id: Ieb42a8511036c86a9d99972dfd7d745f64559685\n" }, { "commit": "c73753f70ab4fc9a166637bee514b292f0fa0109", "tree": "a464e300d44b5a3eca10cb00cc42be7c1ab9da96", "parents": [ "530a6b6902b50db43659757a6270b7d111d93a2c", "07bfbace6f835e6c748fd68ec7624992478b16c1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 21 09:41:58 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 21 09:41:58 2017 +0000" }, "message": "Merge \"Hash-based DexCache methods array.\"" }, { "commit": "07bfbace6f835e6c748fd68ec7624992478b16c1", "tree": "5d094a00fbc90455bd9b53e042cf8b4fe8433462", "parents": [ "ba118827465d12177f3996e50133960087b1c916" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 06 14:55:02 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 20 16:33:00 2017 +0100" }, "message": "Hash-based DexCache methods array.\n\nTotal boot*.art size for aosp_angler-userdebug:\n - arm64:\n - before: 11603968\n - after: 10129408 (-1.4MiB, -12.7%)\n - arm:\n - before: 8626176\n - after: 7888896 (-0.7MiB, -8.5%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Nexus 6P boots.\nTest: testrunner.py --target\nTest: Build aosp_mips64-eng\nBug: 30627598\nChange-Id: I7f858605de5f074cbd7f0d9c4c072fbd44aee28f\n" }, { "commit": "331f4c4e287791611733120c1a1c2afd55ecdd65", "tree": "1fcf7810c6c8e2df8b6191bb14a69084f3c7cf11", "parents": [ "13c8343a3394414c90f2fcd1e8efff70e7d2387e", "ba118827465d12177f3996e50133960087b1c916" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 20 14:09:32 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 20 14:09:32 2017 +0000" }, "message": "Merge \"ART: Change method lookup to be more consistent to JLS and the RI.\"" }, { "commit": "ba118827465d12177f3996e50133960087b1c916", "tree": "f39728cdafc7810004d51c0bef2728b98993daa9", "parents": [ "64a102dde8c5daad83b991710decb418ce43aac5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 12 15:41:56 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 20 13:35:06 2017 +0100" }, "message": "ART: Change method lookup to be more consistent to JLS and the RI.\n\nThe method lookup for different invoke types was previously\nwidely different and didn\u0027t work well with the dex cache\nmethod array where we have only a single slot for each\nMethodId. The new behavior is to perform the same lookup for\nall cases, distinguishing only between interface and\nnon-interface referencing class, and to further align the\nbehavior with the JLS and the RI. Where the JLS conflicts\nwith the RI, we follow the JLS semantics.\n\nThe new lookup for class methods first searches the methods\ndeclared in the superclass chain (ignoring \"copied\" methods)\nand only then looks in the \"copied\" methods. If the search\nin the superclass chain finds a method that has not been\ninherited (i.e. either a private method or a package-access\nmethod where one of the classes in the chain does not belong\nto the same package, see JLS 8.4.8), we still search the\n\"copied\" methods as there may actually be a method inherited\nfrom an interface. This follows the JLS semantics where\ninherited methods are included in the search (JLS 15.12.2.1)\nbut conflicts with the RI where the private or\npackage-access method takes precedence over methods\ninherited from interfaces.\n\nNote that this search can find an accessible method that is\nnot inherited by the qualifying type, either for a package\naccess method when the referrer is in the same package but\nthe qualifying type is in another package, or for a private\nmethod where the referrer is in the same class but the\nqualifying type is actually a subclass. For the moment we\nallow such calls and we shall consider whether to throw\nan IncompatibleClassChangeError in this situation in future\nto comply with JLS 15.12.4.3.\n\nThe new lookup for interface methods searches the interface\nclass, then all the superinterfaces and then the\njava.lang.Object class, see implicitly declared methods in\ninterfaces, JLS 9.2. The search for the maximally-specific\nnon-abstract superinterface method is not yet implemented,\nbut the difference should be difficult to observe as the\nusual subsequent call to FindVirtualMethodForInterface()\nshould yield the same result for any matching method.\n\nThe new test 162-method-idx-clash exposes several cases\nwhere we previously completely messed up due to the effects\nof the DexCache, or where we were out of line with the RI.\nIt also tests a case where the JLS and the RI disagree and\nwe follow the JLS.\n\nTest: art/test/run-test --host --jvm 162-method-resolution\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --interp-ac\nTest: Nexus 6P boots.\nTest: testrunner.py --target\nBug: 62855082\nBug: 30627598\nChange-Id: If450c8cff2751369011d649c25d28a482a2c61a3\n" }, { "commit": "13c8343a3394414c90f2fcd1e8efff70e7d2387e", "tree": "c71c2e5775fe82242034c00d0a5c69c4116169bd", "parents": [ "3579eb29f88a9fe4040e4d212e0acaa2e0690946", "4147fcc43c2ee019a06e55384985e3eaf82dcb8c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 20 11:32:20 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 20 11:32:20 2017 +0000" }, "message": "Merge \"MIPS: Reduce Baker read barrier code size overhead\"" }, { "commit": "3579eb29f88a9fe4040e4d212e0acaa2e0690946", "tree": "4b732d4f9aed44e97066b8277a4880d6cbe8e081", "parents": [ "24f4f7956edeffb1ae41809e09f14b6d5e7875c8", "420ee30f4c0f8a5bb6048df4fa27e5432ded893b" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 20 10:32:35 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 20 10:32:35 2017 +0000" }, "message": "Merge \"ARM: VIXL32: Merge (un)signed extensions and integer additions\"" }, { "commit": "4147fcc43c2ee019a06e55384985e3eaf82dcb8c", "tree": "11ec92efbfddf7736bbc74ed35fcfb3756bfcfb0", "parents": [ "e8f48da635c4d07bbe431e5819da8e1fad91a8ef" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Jun 17 19:57:27 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Jul 19 15:03:10 2017 -0700" }, "message": "MIPS: Reduce Baker read barrier code size overhead\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32 and MIPS64 in QEMU with poisoning\n in configurations:\n - with Baker read barrier thunks\n - without Baker read barrier thunks\n - ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2\n" }, { "commit": "01db5f78f627cc64f80b0c0a4eedd0a3dc8b46ca", "tree": "d1ee9267408e2f4d777d28bfc3f65c480f7ecd3f", "parents": [ "c5b1b067fb91c10c75dd0e6dbfd91bebe74347d5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 19 15:05:49 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 19 15:05:49 2017 +0100" }, "message": "Pass the logger to the JIT compiler.\n\nTo avoid effects of concurrent method entrypoints update,\njust pass the logger to the JIT compiler, which will invoke\nit directly with the pointer to the newly allocated code.\n\nTest: test.py --trace\nChange-Id: I5fbcd7cbc948b7d46c98c1545d6e530fb1190602\n" }, { "commit": "420ee30f4c0f8a5bb6048df4fa27e5432ded893b", "tree": "fd72cba9ed09cf78e9377677fd144821fd9f6743", "parents": [ "2f0ac4fb4486e7d9e5c1545d45a2b9b818a80dc3" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Tue Feb 21 18:10:26 2017 +0000" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Tue Jul 18 20:19:58 2017 +0100" }, "message": "ARM: VIXL32: Merge (un)signed extensions and integer additions\n\nTest: m test-art-target-run-test-551-checker-shifter-operand\nChange-Id: I041e80e51bf0954b38ab20dfa9b14aa7f6d6c53b\n" }, { "commit": "9fb4e85d6e42b3f060ddcefcbf39bdfec656fc52", "tree": "80e525f139b88754c23272dd5cf612312b7a61ef", "parents": [ "d44c0d8c7f96644f8176e493de2fbde3eb198bb4", "08490b84048a0267694268185441b70cfa090185" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jul 18 15:15:42 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 18 15:15:42 2017 +0000" }, "message": "Merge \"Only honor $inline$ in AOT.\"" }, { "commit": "08490b84048a0267694268185441b70cfa090185", "tree": "80f96cffd48eb9b43051d4128d4c8654c1a0d8da", "parents": [ "252eda65ae216ff36a4eca2195d1ec3b29612035" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 18 12:58:10 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 18 12:58:59 2017 +0100" }, "message": "Only honor $inline$ in AOT.\n\nThe state of classes is undeterministic when JITting.\n\nTest: test.py\nChange-Id: I05325efe325bb4f7759d7af7cd65d362e6945c57\n" }, { "commit": "24ff0235ab631baccd49fb491197d86d1ef97279", "tree": "d999768a0cf955044a4a771fa802b30034dee234", "parents": [ "252eda65ae216ff36a4eca2195d1ec3b29612035", "c043d006845afef99b17aeab8bb6d6da1a42ad37" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 18 09:54:47 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 18 09:54:47 2017 +0000" }, "message": "Merge \"Remove the old ARM assemblers from ART.\"" }, { "commit": "c043d006845afef99b17aeab8bb6d6da1a42ad37", "tree": "756ce3caca2a7ff62a169c003639657bd7124d2f", "parents": [ "9983e302384c12a975c8d2d5ae239f79fd8e1996" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 16:39:16 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 17 18:00:40 2017 +0100" }, "message": "Remove the old ARM assemblers from ART.\n\nNow that the old ARM code generator for ART\u0027s Optimizing\ncompiler is gone, these assemblers no longer have users;\nretiring them.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iaea42432a9e0d3288b71615f85c58846c0336944\n" }, { "commit": "23cdebe60049850200b30869c6970193f5e7ecea", "tree": "bf6eab054e2595f3dbf269a0cc4f4190799f0528", "parents": [ "d4472455580db696d0f211f8e6f7d99d78b3fa79", "854df416f12c48b52239fe163ab8a7fcac4cddd3" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jul 17 13:13:41 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 17 13:13:41 2017 +0000" }, "message": "Merge \"MIPS: TLAB allocation entrypoints\"" }, { "commit": "65d793bfa91085db5f84b6ee90a3dcdafcafed1b", "tree": "c94b0a8ea3a08a8c29feb4fcccbc0793e85f8ad5", "parents": [ "731af335f4e15e82b8972d63b6424d5228f06eec", "9983e302384c12a975c8d2d5ae239f79fd8e1996" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Sat Jul 15 08:58:21 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Sat Jul 15 08:58:21 2017 +0000" }, "message": "Merge \"Remove the old ARM code generator from ART\u0027s Optimizing compiler.\"" }, { "commit": "9983e302384c12a975c8d2d5ae239f79fd8e1996", "tree": "4e4d269fe1a3d4f0f1b93cd972adab9f17aab8e0", "parents": [ "bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 14:34:22 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 17:25:39 2017 +0100" }, "message": "Remove the old ARM code generator from ART\u0027s Optimizing compiler.\n\nThe AArch32 VIXL-based code generator has been the default\nARM code generator in ART for some time now. The old ARM\ncode generator does not compile anymore; retiring it.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db\n" }, { "commit": "2d0fe4ca6906b4215646f1db99b06f927791f2c6", "tree": "617e2c5fbb508d5500b6a2f06144c0e412386263", "parents": [ "5e7eb2faccf8f4a28e9fcda26053a5b388f2190a", "b79f4ac55c0bb177f541937d0678f2aa777e1c9a" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Jul 14 15:57:26 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 14 15:57:26 2017 +0000" }, "message": "Merge \"Added GVN related attributes to vector nodes.\"" }, { "commit": "bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36", "tree": "58ba3b1d28348da478a44234820ab6c485f5ed37", "parents": [ "06410c093de2b8a21bdbd7dfd9ce324fd4e95c3f", "6d729a789d3d7771e13d9445ee0be1d9d48a81b5" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 10:28:42 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 14 10:28:42 2017 +0000" }, "message": "Merge \"Introduce a Marking Register in ARM code generation.\"" }, { "commit": "b79f4ac55c0bb177f541937d0678f2aa777e1c9a", "tree": "7c331aa30d3c38b4448070527ac02fdbd848f284", "parents": [ "51e74b47f240187d336d9e688f5d7538366f2edf" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Jul 10 10:10:37 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jul 13 16:50:03 2017 -0700" }, "message": "Added GVN related attributes to vector nodes.\n\nRationale: enables better GVNing of vector operations,\nalso pays off some technical debt by adding unit tests\nfor vector nodes.\n\nThis is a revert^2 of a79f0b5deb932aa44e227c94c4ad09082b3ab4c7\n(failed some of the existing checker test due to\nmoving scalar replication; fix was setting can-be-moved\nattribute correctly on that node).\n\nBug: 63538372\n\nTest: test-art-host, test-art-target\n\nChange-Id: I2f29c317354b5e4bf520829232aef17931305ea6\n" }, { "commit": "6d729a789d3d7771e13d9445ee0be1d9d48a81b5", "tree": "360b9af68920f411be5fe6753aaf7ab4976385ea", "parents": [ "8cfbbb826a3ab7bb680cfcd8a8148570b165d620" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 30 18:34:01 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 13 16:41:07 2017 +0100" }, "message": "Introduce a Marking Register in ARM code generation.\n\nWhen generating code for ARM, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register R8,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: m test-art-host-gtest\nTest: ARM device boot test\nBug: 37707231\nChange-Id: I30b44254460d0bbb9f1b2adc65eca52ca3de3f53\n" }, { "commit": "51765b098301fff1897361b2d1a21af356d9d6d8", "tree": "5d35468c9ecd428803fe7e4339fb8e251b6ed926", "parents": [ "e63a91111d13f33028c2988ded53a4659140ca2e" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jun 22 13:49:59 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 13 10:34:27 2017 +0200" }, "message": "MIPS32: ART Vectorizer\n\nMIPS32 implementation which uses MSA extension.\n\nNote: Testing is done with checker parts of tests 640, 645, 646 and\n 651, locally changed to cover MIPS32 cases. These changes can\u0027t\n be included in this patch since MSA is not a default option.\n\nTest: ./testrunner.py --target --optimizing -j1 in QEMU (mips32r6)\nChange-Id: Ieba28f94c48c943d5444017bede9a5d409149762\n" }, { "commit": "854df416f12c48b52239fe163ab8a7fcac4cddd3", "tree": "f5cf247f1e71a5242c797b8fab99ded21839267d", "parents": [ "e63a91111d13f33028c2988ded53a4659140ca2e" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Jun 27 14:41:39 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Jul 13 10:17:07 2017 +0200" }, "message": "MIPS: TLAB allocation entrypoints\n\nAdd fast paths for TLAB allocation entrypoints for MIPS32 and MIPS64.\nAlso improve rosalloc entrypoints.\n\nNote: All tests are executed on CI20 (MIPS32R2) and in QEMU (MIPS32R6\n and MIPS64R6), with and without ART_TEST_DEBUG_GC\u003dtrue.\n\nTest: ./testrunner.py --optimizing --target\nTest: mma test-art-target-gtest\nTest: mma test-art-host-gtest\n\nChange-Id: I92195d2d318b26a19afc5ac46a1844b13b2d5191\n" }, { "commit": "de4b08ff24c330d5b36b5c4dc8664ed4848eeca6", "tree": "79835478b8b631bbf006b5e023704f3cf53bda7c", "parents": [ "c9267c48979698a9217760c914aba13ea20b5990" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Jul 10 14:13:41 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Jul 12 17:54:49 2017 -0700" }, "message": "Reduce quicken info size\n\nMove the quicken info from using a map of \u003cdex pc, index\u003e to an array\nof indices. Removed leb encoding since it is harmful for 16 bit\nindices. The map is indexed by the dequickenable instruction index\nfrom the start of the code item.\n\nNumbers for a certain large app compiled with quicken filter:\ndex2oat native alloc: 85345936B -\u003e 81527072B\noat file size: 9068968B -\u003e 8659368B\nvdex file size: 90479120B -\u003e 86321184B\n\nBug: 63467744\nBug: 36457259\nTest: test-art-host\n\n(cherry picked from commit 959f348acabc48efbb18c547dad6300c0f610c1c)\n\nChange-Id: I85546d8cd409cbf96140cbdddabd7e228797b9e3\n" }, { "commit": "af24def8967027f10ce8d44cb209c23032a2a1b4", "tree": "503bc7430d73944dc1faf51082fc36be1735d4c4", "parents": [ "08dd84adab79f98b2f2e7dfbccf8ef6b07cd3f2e" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 12 13:18:01 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 12 13:20:53 2017 +0100" }, "message": "Fix ART ARM64 CFI gtests with GCs other than CC with Baker read barriers.\n\nSince the introduction of a Marking Register in the ARM64 back\nend, gtests jni_cfi_test and optimizing_cfi_test produce\ndifferent outputs for the Concurrent Copying (CC) collector\nwith Baker read barriers on the one hand, and for other GCs on\nthe other hand.\n\nTest: m test-art-host-gtest with tree built with ART_USE_READ_BARRIER\u003dfalse\nBug: 37707231\nChange-Id: I63de8873f52df593eb664970f2be20f1089804a9\n" }, { "commit": "97c46466aea25ab63a99b3d1afc558f0d9f55abb", "tree": "afd225f51d28a77329bc2590a025400e088f260c", "parents": [ "00cca3a275562d110a8b35094b9b12fac37f67ab" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu May 11 14:04:03 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 11 17:43:27 2017 +0100" }, "message": "Introduce a Marking Register in ARM64 code generation.\n\nWhen generating code for ARM64, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register X20,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test\nBug: 37707231\nChange-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b\n" }, { "commit": "ca8c2951ea25e8f93eea9decc70d81937b4361dd", "tree": "72c811abe58895b4972cd88ee267c8ca66155fd1", "parents": [ "2e0a7e5047fde08ddd220aaa1a0e64d44ecbb420" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Mon May 29 11:31:46 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 06 14:06:33 2017 +0200" }, "message": "MIPS32: Saves 128-bit vector registers along SuspendCheckSlowPath\n\nWe need to save 128 bits of data. This is only done for vector\nregisters that are live, so overhead is not too big.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS)\nChange-Id: I0f792e9c98011be3e24d5fad35a8244faafcb9a0\n" }, { "commit": "640fbdc7516a40883f219bd3c9f0e7b8a49842b4", "tree": "09b4ed23b6904c78ce6b1229b0b70f9a8830717f", "parents": [ "4a77b1e96733be419c0cb571448e8590c803bd91", "2a3471fc83383bfe3e060799482e372420ba6150" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 05 10:28:20 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jul 05 10:28:20 2017 +0000" }, "message": "Merge \"Disambiguate memory accesses in instruction scheduling\"" }, { "commit": "8091ed8a26db4609c719ea8d905145ddfed7f498", "tree": "342d4459e8e9c61af7b69fc2ac2e0512592cf9f4", "parents": [ "61cfb15e2588ff1fe3c80efbfcf55973122b28cb", "5fa5c04ca39fb9c46bfef0e0807a18d0cd9a4ba7" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jul 03 11:48:56 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 03 11:48:56 2017 +0000" }, "message": "Merge \"MIPS: Shorten .bss string/class loads\"" }, { "commit": "e128af51eb0d1a882b9bc37cd213639d0c3a63e7", "tree": "cce9394c1892680e9d731df24475fca35decaf59", "parents": [ "dfcf10b92330164f8af6c82c8232e85cfff1ae3c", "8f7c41044bdb7a36913444a3437bf2b946f7efe9" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Jun 30 18:18:06 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 30 18:18:06 2017 +0000" }, "message": "Merge \"ARM: ART Vectorizer (64-bit vectors).\"" }, { "commit": "dd3240ce699129007935ba0bae4872e28652b90c", "tree": "305d061a33740ce48c7f027b474641017e1bab86", "parents": [ "89ae0f42e38a2f985ac404830f2a05fecf9547e2", "8098da9cf3e3f7875546c2cd953f2337587b39db" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jun 30 15:50:59 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 30 15:50:59 2017 +0000" }, "message": "Merge \"MIPS32: MoveLocation refactoring\"" }, { "commit": "2a3471fc83383bfe3e060799482e372420ba6150", "tree": "7b7764521a0b67392e023f1efacc0dbae64fe675", "parents": [ "89ae0f42e38a2f985ac404830f2a05fecf9547e2" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon May 08 18:36:40 2017 +0100" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Fri Jun 30 16:32:54 2017 +0100" }, "message": "Disambiguate memory accesses in instruction scheduling\n\nBased on aliasing information from heap location collector,\ninstruction scheduling can further eliminate side-effect\ndependencies between memory accesses to different locations,\nand perform better scheduling on memory loads and stores.\n\nPerformance improvements of this CL, measured on Cortex-A53:\n| benchmarks | ARM64 backend | ARM backend |\n|----------------+---------------|-------------|\n| algorithm | 0.1 % | 0.1 % |\n| benchmarksgame | 0.5 % | 1.3 % |\n| caffeinemark | 0.0 % | 0.0 % |\n| math | 5.1 % | 5.0 % |\n| stanford | 1.1 % | 0.6 % |\n| testsimd | 0.4 % | 0.1 % |\n\nCompilation time impact is negligible, because this\nheap location load store analysis is only performed\non loop basic blocks that get instruction scheduled.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: 706-checker-scheduler\n\nChange-Id: I43d7003c09bfab9d3a1814715df666aea9a7360b\n" }, { "commit": "aed3dbf9601bc1bb91142dce10a89cf5ea6a93d3", "tree": "03742367b4f8f6a1b6eb44effae478c6d16a6e50", "parents": [ "6cb5ae065a54f08f0c8d09b41c2697b097094ce9", "016c0f165dc6872d22c12c239d19b094983519f1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jun 30 11:44:18 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 30 11:44:18 2017 +0000" }, "message": "Merge \"Improve array index analysis in LSA.\"" }, { "commit": "8f7c41044bdb7a36913444a3437bf2b946f7efe9", "tree": "cdfcc8dae149617f6270198e15101b329f821ebd", "parents": [ "a4811cd3496eb28295fe61057844c53793f3023e" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jun 21 11:21:37 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Jun 30 11:52:24 2017 +0100" }, "message": "ARM: ART Vectorizer (64-bit vectors).\n\nBasic vectorization support with 64-bit vector length on ARM 32-bit\nplatforms (128-bit vectors require massive changes in register\nallocator).\n\nTest: test-art-target, test-art-host\n\nChange-Id: I1d740146c3f00170fc033ae5fd69d59321ddcbf4\n" }, { "commit": "740c3008171fe69432db8bfe4b9c837ac24b85c0", "tree": "ead2d10a4c0478e2e08d30a9e7de7f8f5fbb4a27", "parents": [ "4aa0cf8d72386bc2bc42f437919a66ec392eca21", "757b26c2442ae792039bc50153bef91145f3c7b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jun 30 09:12:51 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 30 09:12:51 2017 +0000" }, "message": "Merge \"Add CHECKs to help diagnose a crash seen internally.\"" }, { "commit": "4aa0cf8d72386bc2bc42f437919a66ec392eca21", "tree": "8032373cf5073225b8d6082d98760a3a4c3f4e09", "parents": [ "5f17267621174ac22ab53f02b3a5e1ee54308775", "c9c310487b8730fce5edfa72e79c4188629898a3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jun 30 09:11:55 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 30 09:11:55 2017 +0000" }, "message": "Merge \"Turn a few DCHECK into CHECKs.\"" }, { "commit": "37dc4df47fec811ea52f7180880961565f013434", "tree": "eac308a6c7ef8b7d53f64889ff0a93740a2dc62a", "parents": [ "76754cc816af46b41a8d1f419a38334b5db59b6e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jun 28 14:08:00 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jun 29 11:20:56 2017 -0700" }, "message": "Improved subscript and data dependence analysis.\n\nRationale:\nWe missed vectorizing a simple stencil operation\ndue to inaccurate unit stride analysis and failure\nto detect single runtime data dependence test.\n\nTest: test-art-host, test-art-target\nChange-Id: I07ba03455bfb1c0aff371c1244a1328f885d0916\n" }, { "commit": "757b26c2442ae792039bc50153bef91145f3c7b4", "tree": "4d8798405364a51bb7dd6f2c365bfdffca26f791", "parents": [ "fe9a4f061841a3c597aac6817a47c799c54fcad7" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 29 16:11:41 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 29 16:13:06 2017 +0100" }, "message": "Add CHECKs to help diagnose a crash seen internally.\n\nbug: 62855731\nTest: test.py\nChange-Id: I7904257174ce11a138ca769172dbc2e33e10ef76\n" }, { "commit": "c9c310487b8730fce5edfa72e79c4188629898a3", "tree": "e9e72b0296b557722979b51bf9d98054c4fb1971", "parents": [ "853cc56ae6a79fa9540bb49c5c95d1568d47656d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 29 14:04:16 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 29 15:04:21 2017 +0100" }, "message": "Turn a few DCHECK into CHECKs.\n\nTo help diagnose b/63070152.\n\nbug: 63070152\nTest: test.py\nChange-Id: I1ac1cf9bfe1bc15ecfa94b5b8537cd3afda6fd14\n" }, { "commit": "76754cc816af46b41a8d1f419a38334b5db59b6e", "tree": "9a04d4a9811c5f196b29c144875a57818e8815d9", "parents": [ "3dc94c4763ecab28c0053d5d07e332c61a3f781b", "f57c1ae3682f95e6d7ce08ae4c241d04b09de658" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jun 28 22:33:32 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 28 22:33:32 2017 +0000" }, "message": "Merge \"Prevent loop optimization in debuggable mode.\"" }, { "commit": "f57c1ae3682f95e6d7ce08ae4c241d04b09de658", "tree": "bf12e0e19626c28edd933fb31c5652e7f974bf1d", "parents": [ "0ca1ae25d33dc8b92d9eecd585657f74cbb313e9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 28 17:40:18 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 28 21:10:13 2017 +0100" }, "message": "Prevent loop optimization in debuggable mode.\n\nbug: 33775412\nTest: no scanner crash (torn on whether I should spend some time working on a smali test)\n\nChange-Id: I8b94725ce57171b592bede4bf55cd0a9626a8a10\n" }, { "commit": "a6d098c3f4da902d6607972fcadaf57760d76d63", "tree": "3d0a0590183765deacb3ed812b4f4fe5b3e78cf1", "parents": [ "0ca1ae25d33dc8b92d9eecd585657f74cbb313e9", "14a68b4aa9620e4fd58907255b049fb5c18bd1ec" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jun 28 16:02:59 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 28 16:02:59 2017 +0000" }, "message": "Merge \"Unrolling and dynamic loop peeling framework in vectorizer.\"" }, { "commit": "8098da9cf3e3f7875546c2cd953f2337587b39db", "tree": "8f0b2d69f83a1de7a0bb80ce1c3f1412c429615d", "parents": [ "ebd4def76f4e60e442edb8d48f43a931bc3c773e" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Wed Jun 28 12:07:50 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Wed Jun 28 17:42:17 2017 +0200" }, "message": "MIPS32: MoveLocation refactoring\n\nMove32 and Move64 are removed so MoveLocation now handles all cases.\nReason for this are 128-bit (SIMDStackSlot, VectorRegister) moves\nwhich will be added in follow-up patch.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU\n\nChange-Id: I93496e74874f77337b11b2265aa4b470bc7c6ce2\n" }, { "commit": "14a68b4aa9620e4fd58907255b049fb5c18bd1ec", "tree": "692319b6a9344d84a2e8916c388be954d8878c41", "parents": [ "afdcd847498abc0f4e295bece443afabf8aaf868" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jun 08 14:06:58 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jun 27 11:29:07 2017 -0700" }, "message": "Unrolling and dynamic loop peeling framework in vectorizer.\n\nRationale:\nThis CL introduces the basic framework for dynamically peeling\n(to obtain aligned access) and unrolling the vector loop (to reduce\nlooping overhead and allow more target specific optimizations\non e.g. SIMD loads and stores).\n\nNOTE:\nThe current heuristics are \"bogus\" and merely meant to exercise\nthe new framework. This CL focuses on introducing correct code for\nthe vectorizer. Heuristics and the memory computations for alignment\nare to be implemented later.\n\nTest: test-art-target, test-art-host\n\nChange-Id: I010af1475f42f92fd1daa6a967d7a85922beace8\n" }, { "commit": "db87b28cd68d5b1705da2e4fdbe04f9182e5452a", "tree": "a213ee07206ff08f1ebe633f6ffc346437e41522", "parents": [ "90d71886bf3c134e1fc9255a312f41b56700854a", "5ceac0e41bdf8d486f978c43800f493bce83f5d4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 27 11:07:23 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 27 11:07:23 2017 +0000" }, "message": "Merge \"Don\u0027t use the graph\u0027s dex file when printing HInvoke.\"" }, { "commit": "80b99c23b09bf1c4ca49385cff15879d821aecb9", "tree": "ac62622ac8948fedd1572087f4c63b992154e639", "parents": [ "afdcd847498abc0f4e295bece443afabf8aaf868", "a4b58ed1ef8dceafbffcfa88bf2c11144e302d18" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jun 26 18:41:42 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jun 26 18:41:44 2017 +0000" }, "message": "Merge \"Fix static analyzer warning\"" }, { "commit": "5ceac0e41bdf8d486f978c43800f493bce83f5d4", "tree": "6d0f266e85405afc88ebc28b70dd09a91bb85ddb", "parents": [ "d1c983a5bc3ae50eab3af405ae8a415e1f36f532" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 26 13:19:09 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 26 16:17:43 2017 +0100" }, "message": "Don\u0027t use the graph\u0027s dex file when printing HInvoke.\n\nIt\u0027s not the right dex file if the invokes come from inlined\nmethods.\n\nTest: manual\nChange-Id: I4e3fb35e2bddc67510c39e12075c9a5ca0498a3a\n" }, { "commit": "016c0f165dc6872d22c12c239d19b094983519f1", "tree": "bef8e9912412d02b7aa3913f2750147835454b2e", "parents": [ "d1c983a5bc3ae50eab3af405ae8a415e1f36f532" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Fri May 12 18:16:31 2017 +0100" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon Jun 26 11:30:39 2017 +0100" }, "message": "Improve array index analysis in LSA.\n\nThis CL improves analysis on array index in load store analysis.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: m test-art-host-gtest-load_store_analysis_test\n\nChange-Id: Id5e5aa8b396c68e082db95809659494107985fa2\n" }, { "commit": "6fda42718a348cfb758d8714e223cab7e855765b", "tree": "d6f0f4d0c1ca2eec26a56e2aadaf00d3205b70a0", "parents": [ "a0e63dfbfe2f2513a709e94b8a1ac17418396fdf" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 26 09:12:45 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 26 10:59:17 2017 +0100" }, "message": "Fix braino when handling branches fallthrough in arm backend.\n\nbug: 62210114\nTest: 657-branches\nChange-Id: I753a9a57e404c792cd4375ea66c91839684bdee2\n" }, { "commit": "a4b58ed1ef8dceafbffcfa88bf2c11144e302d18", "tree": "c1a931ba1bc1c710d1cdad9291c57aaa6b373597", "parents": [ "b96ed2c271a56fb8be0c8f30231710095e66a201" ], "author": { "name": "George Burgess IV", "email": "gbiv@google.com", "time": "Thu Jun 22 15:47:25 2017 -0700" }, "committer": { "name": "George Burgess IV", "email": "gbiv@google.com", "time": "Thu Jun 22 15:47:25 2017 -0700" }, "message": "Fix static analyzer warning\n\nnodes.cc: warning: Access to field \u0027next_\u0027 results in a dereference of a\nnull pointer (loaded from field \u0027last_instruction_\u0027)\n\nThis was split from\nhttps://android-review.googlesource.com/#/c/416101/. Please see the\ndiscussion nodes.cc (patch set 1) for why this warning is triggered.\n\nBug: 32619234\nTest: test-art-host. Rebuilt ART with the analyzer to verify that these\nissues are gone.\n\nChange-Id: Id5da00ceee0667441233153a7971d238ea8c8650\n" }, { "commit": "1a0a519c82044ec3e6d3910ff0602b11292de47a", "tree": "342691a82a58ddb0660b9111622b2ff67d92f898", "parents": [ "8979f71079ec18fa8d3c0915549ec03ee1fbadf5" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 22 11:56:01 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 22 12:09:16 2017 +0100" }, "message": "Fix loop optimization in the presence of environment uses.\n\nWe should not remove instructions that have deoptimize as\nusers, or that have environment uses in a debuggable setup.\n\nbug: 62536525\nbug: 33775412\nTest: 656-loop-deopt\nChange-Id: Iaec1a0b6e90c6a0169f18c6985f00fd8baf2dece\n" }, { "commit": "f789353025401c1907d2264952a88f253a9af8e7", "tree": "9ad4c6a4eed419eb8664fd8aa6b4811d5f259f71", "parents": [ "1368312bb4772a1c505452f766fdaceef4c48f6e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 15 12:34:36 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 15 14:05:08 2017 +0100" }, "message": "Set the deopt flag after adjusting the stack pointer.\n\nOne should not write to something below the stack pointer, or\nit could be overwritten during an interrupt.\n\nTest: test.py\nChange-Id: Ie6c997b9f7548ca5844303d6a3fc0c531f469c6e\n" } ], "next": "c0fe9db1af30a162448ca5ccd386e970a8d31f83" }