)]}' { "log": [ { "commit": "55ab7e84c4682c492b6fa18375b87ffc5d0b23bb", "tree": "5fcc2567a1a4e6ae73dead2f70c69bc03b0a64bb", "parents": [ "ac27ac01490f53f9e2413dc9b66fbb2880904c96" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 27 21:02:28 2020 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Fri Feb 05 11:34:38 2021 +0000" }, "message": "ARM64: Support SVE VL other than 128-bit.\n\nArm SVE register size is not fixed and can be a\nmultiple of 128 bits. To support that the patch\nremoves explicit assumptions on the SIMD register\nsize to be 128 bit from the vectorizer and code\ngenerators and enables configurable SVE vector\nlength autovectorization, e.g. extends SIMD register\nsave/restore routines.\n\nTest: art SIMD tests on VIXL simulator.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n with FVP arg:\n -C SVE.ScalableVectorExtension.veclen\u003d[2,4]\n (SVE vector [128,256] bits wide)\n\nChange-Id: Icb46e7eb17f21d3bd38b16dd50f735c29b316427\n" }, { "commit": "8ba4de1a5684686447a578bdc425321fd3bccca6", "tree": "20c24450b24950266ccc235306e3ad2109c57497", "parents": [ "32bf6d39bc020cacfc655ce60630f4a0da3b45cf" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Dec 04 21:10:23 2019 +0000" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Thu Feb 04 06:16:33 2021 +0000" }, "message": "ART: Implement predicated SIMD vectorization.\n\nThis CL brings support for predicated execution for\nauto-vectorizer and implements arm64 SVE vector backend.\n\nThis version passes all the VIXL simulator-runnable tests in\nSVE mode with checker off (as all VecOp CHECKs need to be\nadjusted for an extra input) and all tests in NEON mode.\n\nTest: art SIMD tests on VIXL simulator.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n\nChange-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f\n" }, { "commit": "98873affc25ef6bc96f8c65f828f28530b8f3fcd", "tree": "be471ad310edb1aa3a7b3df44528905ec7ce9a6c", "parents": [ "771708f3f0a15c1ae50617b4141c5f5dd47bf94f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 16 12:10:03 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 08 13:44:10 2021 +0000" }, "message": "arm64: Implement VarHandle intrinsics for byte array views.\n\nUsing benchmarks provided by\n https://android-review.googlesource.com/1420959\non blueline little cores with fixed frequency 1420800:\n before after\nGetByteArrayViewInt 27.093 0.024\nSetByteArrayViewInt 28.067 0.024\nGetByteArrayViewBigEndianInt 27.142 0.026\nSetByteArrayViewBigEndianInt 28.040 0.025\n\nTest: testrunner.py --target --64 --optimizing\nBug: 71781600\nChange-Id: I604326675042bd63dce8ec15075714003ca9915d\n" }, { "commit": "c8178f5eb06aa54f78237145d7fdc05609c02962", "tree": "e69d3979efb81ca752f5f2d469279e26f22329aa", "parents": [ "e8cdb0bb53e42316e8c7379d41a647ca672c4bee" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 24 10:38:16 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 02 20:20:49 2020 +0000" }, "message": "arm64: Clean up VarHandle intrinsics implementation.\n\nFix some typos and update some table lookup code that\u0027s\ncurrently unused. Bring in a few things from arm (naming,\nstatic assertion, pull an expression to a named variable).\n\nTest: testrunner.py --target --64 --optimizing\nBug: 71781600\nChange-Id: If2f2c4417942a272a8ad672c6b876e0569f8827c\n" }, { "commit": "1bff99f706a1b1a4c1799e0f037d9f59f303587a", "tree": "06cabecf52fbd336a2e65dbde991c45ce10bc64a", "parents": [ "b15e8797d2ca6fb480a940887c66dd2aae7c9065" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 02 15:07:33 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 10 10:36:19 2020 +0000" }, "message": "arm64: Implement VarHandle CAS intrinsics.\n\nAnd refactor Unsafe CAS intrinsics for code reuse.\n\nAdd extra tests to the 160-read-barrier-stress to test the\nslow paths. The main path is sufficiently exercised by the\n712-varhandle-invocations test. The refactored Unsafe CAS is\nalready covered by 004-Unsafe and 160-read-barrier-stress.\n\nUsing benchmarks provided by\n https://android-review.googlesource.com/1420959\non blueline little cores with fixed frequency 1420800:\n before after\nCompareAndSetStaticFieldInt 24.721 0.026\nCompareAndSetStaticFieldString 29.015 0.032\nCompareAndSetFieldInt 27.237 0.028\nCompareAndSetFieldString 31.326 0.033\nWeakCompareAndSetStaticFieldInt 24.735 0.027\nWeakCompareAndSetStaticFieldString 28.970 0.031\nWeakCompareAndSetFieldInt 27.252 0.028\nWeakCompareAndSetFieldString 31.309 0.036\nWeakCompareAndSetPlainStaticFieldInt 24.738 0.026\nWeakCompareAndSetPlainStaticFieldString 29.004 0.030\nWeakCompareAndSetPlainFieldInt 27.252 0.027\nWeakCompareAndSetPlainFieldString 31.326 0.035\nWeakCompareAndSetAcquireStaticFieldInt 24.728 0.026\nWeakCompareAndSetAcquireStaticFieldString 28.977 0.030\nWeakCompareAndSetAcquireFieldInt 27.250 0.027\nWeakCompareAndSetAcquireFieldString 31.306 0.034\nWeakCompareAndSetReleaseStaticFieldInt 24.738 0.026\nWeakCompareAndSetReleaseStaticFieldString 28.994 0.032\nWeakCompareAndSetReleaseFieldInt 27.250 0.028\nWeakCompareAndSetReleaseFieldString 31.312 0.035\nCompareAndExchangeStaticFieldInt 23.898 0.026\nCompareAndExchangeStaticFieldString 28.544 0.032\nCompareAndExchangeFieldInt 26.787 0.027\nCompareAndExchangeFieldString 31.022 0.034\nCompareAndExchangeAcquireStaticFieldInt 23.957 0.026\nCompareAndExchangeAcquireStaticFieldString 28.586 0.031\nCompareAndExchangeAcquireFieldInt 26.785 0.026\nCompareAndExchangeAcquireFieldString 31.011 0.033\nCompareAndExchangeReleaseStaticFieldInt 23.963 0.026\nCompareAndExchangeReleaseStaticFieldString 28.511 0.032\nCompareAndExchangeReleaseFieldInt 26.729 0.027\nCompareAndExchangeReleaseFieldString 30.938 0.034\n\nTest: testrunner.py --target --64 --optimizing\nTest: Repeat with ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue.\nTest: Repeat with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP.\n (Ignore two pre-existing checker test failures.)\nBug: 71781600\nChange-Id: I01b2218bb812bc636a941f9bd67c844aee5f8b41\n" }, { "commit": "de91ca90389e4b41ed27b320a6c43ff56a6d75ff", "tree": "2e18ff33d30fce88d578ea68b8b1037755aececc", "parents": [ "9ca92fb4646eccff9f972f6a2a21709676b65460" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 27 13:41:40 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 29 15:42:52 2020 +0000" }, "message": "Refactor Integer.valueOf() intrinsic implementation.\n\nPrepare for Reference.getReferent() intrinsic implementation\nby a refactoring to separate the retrieval of an intrinsic\nmethod\u0027s declaring class to its own helper function, rather\nthan being a part of a larger one.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: aosp_blueline-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing --jit\nBug: 170286013\nChange-Id: Ib6c0e55d0c6fcc932999428f21c51afe32ab7ef2\n" }, { "commit": "eb9eb00868106af52386d7113a8aafaa6d44e8b6", "tree": "05b1243b30b31d6e2d3215ebdaa329c90d9875f8", "parents": [ "5fa36f99fdb5617d1ced977c637dcaa2762704fc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 02 13:54:19 2020 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Oct 19 17:01:09 2020 +0000" }, "message": "Faster @CriticalNative for boot image.\n\nThe @CriticalNative call does not need the target method, so\nwe can avoid one instruction on x86, x86-64 and arm64. The\ncurrent approach for arm does not allow such optimization.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_blueline-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --64 --optimizing\nBug: 112189621\nChange-Id: I11b7e415be2697757cbb11c9cccf4058d1d72d7d\n" }, { "commit": "8d34a182fea1b24f7b8361b55e930cb953cf3fb2", "tree": "4f5ed9d9ac417dfd69fd18f64412b2272c448e05", "parents": [ "8ecbc4e844fc3b73e6a5c5151eda914d53297180" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 16 09:46:58 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 07 08:32:52 2020 +0000" }, "message": "Change interface conflict stub to take the interface method.\n\nTo avoid doing dex cache lookup, pass the interface method instead. This\ncosts a few hundred KBs on speed compiled APKs (\u003c 0.5% code size), but\nimproves performance when hitting a conflict (as seen on dogfood data).\n\nFor nterp, we currently pass the conflict method instead of the\ninterface method. We need to handle default methods before optimizing\nit.\n\nThis removes our last use of dex cache in compiled code. A follow-up CL\nwill remove the NeedsDexCacheOfDeclaringClass from HInvokeInterface.\n\nTest: test.py\n\nChange-Id: I3cdd4543ad7d904b3e81950af46a48a48af6991a\n" }, { "commit": "8f63f1084b013a129f66cf8a7ed8ab1cae9f02aa", "tree": "6e9bbf5ad71a55f701f740e2995e0b84e9b87307", "parents": [ "7aa2bfc09541ea5d2516738de84c24cd0269fed0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 28 12:10:28 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 30 13:58:32 2020 +0000" }, "message": "Faster access to unresolved classes from compiled code.\n\nAdd two new load kinds to LoadClass, similar to kBssEntry\nbut using the access-checking entrypoint on the slow-path.\nOne is used for classes that are in the literal package and\nthe other for classes outside the literal package of the\ncompiling class. Associate new .bss entries with these load\nkinds and update them from entrypoints based on the resolved\nclass properties. If the resolved class is public, both\ntypes of entries can be updated, otherwise only the package\nlocal entry can be updated and only if the defining class\nloader of the class is the same as the caller\u0027s defining\nclass loader (which is identical for all code in an oat\nfile) because the run time access check for same package\nrequires both class loader and literal package name match.\n\nTest: Additional tests in 727-checker-unresolved-class.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_blueline-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nBug: 161898207\nChange-Id: I281e06ac2825caf81c6d7ee3128af833abd39992\n" }, { "commit": "c679fe3915fee6c490c1e8478a6c455f62c10a3f", "tree": "f0f676afba57ee13a3e040bce1a5636d5e6b838a", "parents": [ "952c0904d46f4170c6a2578c19a702a0499e57f4" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Sep 14 14:02:40 2020 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Sep 18 12:23:51 2020 +0000" }, "message": "ARM: Optimize div/rem when dividend is compared with a non-negative\n\nWhen a divisor is a positive constant and a dividend is compared with a\nnon-negative value, the result of the comparison can guarantee that the\ndividend is non-negative. In such a case there is no need to generate\ninstructions correcting the result of div/rem.\n\nThe CL implements this optimization for ARM32/ARM64.\n\nTest: 411-checker-hdiv-hrem-pow2\nTest: 411-checker-hdiv-hrem-const\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\nChange-Id: If1dc1389f6e34d2be3480ef620a626f389ca53a5\n" }, { "commit": "dec7817522eeaf8f88dcae9ce065969aeebda3b3", "tree": "a15fd16ccb4a1929ec60584ead8f095b565c9e3e", "parents": [ "ea4d7d2d52dd9795cf39eccd46cb07551c62392f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 19 15:31:23 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 22 08:05:28 2020 +0000" }, "message": "Optimizing: Introduce {Increase,Decrease}Frame().\n\nAnd use it to clean up code generators.\n\nAlso fix CFI in MaybeIncrementHotness() for arm/arm64/x86.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --host --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nTest: aosp_cf_x86_phone-userdebug boots.\nTest: aosp_cf_x86_phone-userdebug/jitzygote boots.\nTest: # On blueline:\n testrunner.py --target --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nBug: 112189621\nChange-Id: I524e6c3054ffe1b05e2860fd7988cd9995df2963\n" }, { "commit": "86c8752f64629325026945cd4eabd1dcea224acb", "tree": "9dc2be978f9e784a3ce16fa29d46941a94ac1c94", "parents": [ "f97a859e85f703644d897f0e3e1bc54315557aaa" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 11 16:55:55 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 19 08:26:46 2020 +0000" }, "message": "Direct calls to @CriticalNative methods.\n\nEmit direct calls from compiled managed code to the native\ncode registered with the method, avoiding the JNI stub.\n\nGolem results:\nart-opt-cc x86 x86-64 arm arm64\nNativeDowncallStaticCritical +12.5% +62.5% +75.9% +41.7%\nNativeDowncallStaticCritical6 +55.6% +87.5% +72.1% +35.3%\nart-opt x86 x86-64 arm arm64\nNativeDowncallStaticCritical +28.6% +85.6% +76.4% +38.4%\nNativeDowncallStaticCritical6 +44.6% +44.6% +74.6% +32.2%\n\nTest: Covered by 178-app-image-native-method.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nTest: testrunner.py --target --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nTest: aosp_cf_x86_phone-userdebug boots.\nTest: aosp_cf_x86_phone-userdebug/jitzygote boots.\nBug: 112189621\nChange-Id: I8b37da51e8fe0b7bc513bb81b127fe0416068866\n" }, { "commit": "9922f00cf68aac69209216a0726a45eb6338763c", "tree": "7e43b55e85ed17443af1c6be6532dafbb8550495", "parents": [ "16527e892b13c9e1fb34f8d2e9993e58a72ac662" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 15:05:15 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 09 10:03:58 2020 +0000" }, "message": "arm/arm64: Clean up intrinsic slow paths.\n\nGeneralize and use the slow path template IntrinsicSlowPath\nfrom intrinsics_utils.h.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boot image is unchanged.\nChange-Id: Ia8fa4e1b31c1f190fc5f02671336caec15e4cf4d\n" }, { "commit": "0ddb338f084b1c46efbfa7a79ad6aa1b63a24ded", "tree": "e36eaa49dd79914622fff402f6ca2e829646c3fb", "parents": [ "8bcba2264f5ba66ef8820e3963e838a67bd6215f" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon May 18 11:15:46 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 15:10:40 2020 +0000" }, "message": "ARM64: Combine LSR+ADD into ADD_shift for Int32 HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nIn case of Int32 the multiplication is done into a 64-bit register\nhigh 32 bits of which are only used.\nThe multiplication result might need some ADD/SUB corrections.\nCurrently it is done by extracting high 32 bits with LSR and applying\nADD/SUB. However we can do correcting ADD/SUB on high 32 bits and extracting\nthose bits with the final right shift. This will eliminate the\nextracting LSR instruction.\n\nThis CL implements this optimization.\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I5ba557aa283291fd76d61ac0eb733cf6ea975116\n" }, { "commit": "a6653d304faa3bbd981507570a4ac1107760c6a7", "tree": "6dc333f6f19b932c0fd739b4862c3800b3a51b45", "parents": [ "4d0f795aaa9abd1b36e2704b3851b2cc39c70cdd" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 05 16:30:24 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 07 09:04:21 2020 +0000" }, "message": "ART: Refactor InstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant\n\nInstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant handles\nboth Int32 and Int64 cases. However Int32 cases can have additional\noptimizations. Having them in GenerateDivRemWithAnyConstant makes code\ndifficult to read.\n\nThis CL splits the code of GenerateDivRemWithAnyConstant to:\n* GenerateInt32DivRemWithAnyConstant\n* GenerateInt64DivRemWithAnyConstant\n* GenerateResultDivRemWithAnyConstant\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I267331c026e87d6a233b593586f1b74759382896\n" }, { "commit": "1a719e4de83532a1dcd9ddfad2c92d4130f28ea9", "tree": "445026effb3298ca8e962701ee01f65785be6fe6", "parents": [ "e33dca6d44463606168330d2f84bc616e8c147f6" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Jul 18 14:24:55 2019 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Mon May 04 08:19:17 2020 +0000" }, "message": "RFC: ARM64: Split arm64 codegen into scalar and vector (SVE and NEON).\n\nThis is a first CL in the series of introducing arm64 SVE support\nin ART. The patch splits the codegen functionality into scalar and\nvector ones and for the latter introduces NEON and SVE\nimplementations. SVE one currently is an exact copy of NEON one -\nfor the sake of testing and an easy diff when the next CL comes\nwith an actual SVE instructions support.\n\nThe patch effectively doesn\u0027t change any behavior; NEON mode is\nused for vector instructions, tests pass.\n\nTest: test-art-target.\nChange-Id: I5f7f2c8218330998e5a733a56f42473526cd58e6\n" }, { "commit": "c8150b5def82058c23df377a5006a78e7668afeb", "tree": "8f0e15b91cd55b978ca7f152206f0a550353810a", "parents": [ "b2028739a2db03623ed76f5028ede1333c48f4c9" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 31 18:28:00 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Apr 17 10:35:45 2020 +0000" }, "message": "ART: Refactor SIMD slots and regs size processing.\n\nART vectorizer assumes that there is single size of SIMD\nregister used for the whole program. Make this assumption explicit\nand refactor the code.\n\nNote: This is a base for the future introduction of SIMD slots of\nsize other than 8 or 16 bytes.\n\nTest: test-art-target, test-art-host.\nChange-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c\n" }, { "commit": "a59af8aeaad8fe7d68d8f8de63eab9cf85b6ab31", "tree": "83195c74b135731cc4555254763a8f449691c1b0", "parents": [ "5c8cc64b5f1580faf510f27527e7e22987174963" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 17:42:32 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 03 14:32:09 2019 +0000" }, "message": "JIT baseline: trigger optimized compilation on hotness threshold.\n\n- Add a new hotness count in the ProfilingInfo to not conflict with\ninterpreter hotness which may use it for OSR.\n- Add a baseline flag in the OatQuickMethodHeader to identify baseline\ncompiled methods.\n- Add a -Xusetieredjit flag to experiment and test.\n\nBug: 119800099\nTest: test.py with Xusetieredjit to true\n\nChange-Id: I8512853f869f1312e3edc60bf64413dee9143c52\n" }, { "commit": "e2a3aa988630b3c2952ac44943f03dde60454195", "tree": "acee7012af6e2b161c91e6cd8b7b4d12eb5aa927", "parents": [ "a2c4d61e482a15974e3e220bcd62a64043ee536f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 25 17:52:58 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 14:04:43 2019 +0000" }, "message": "Baseline JIT: update inline caches in compiled code.\n\nIn trying to remove profiling from interpreter, to speed up\ninterpreter performance.\n\nBug: 119800099\nTest: test.py --baseline\nChange-Id: Ica1fa41a889b31262d9f5691b30a31fbcec01b34\n" }, { "commit": "7d48dcd51db4b950c22ec78ef3caa53fdf4214d3", "tree": "72600968b1daf5682018880f20ca07610e62b8e7", "parents": [ "f05f04b429a63eb036f501866a863109f05b95b2" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Oct 16 12:46:28 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 31 14:56:52 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API\n\nVIXL has had FPRegister as an alias for VRegister for backward\ncompatibility. In the latest upstream VIXL the alias has been removed and all\nFPRegister based API has became VRegister based. As AOSP VIXL is being\nupdated to the latest upstream VIXL all uses of FPRegister based API\nmust be replaced with VRegister based API.\nThis CL moves ART from FPRegister based API to VRegister based API.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I12541c16d0557835ea19c8667ae18c6601359b05\n" }, { "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0", "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f", "parents": [ "e2727154f25e0db9a5bb92af494d8e47b181dfcf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n" }, { "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf", "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8", "parents": [ "c78860b91ae07eed92f86876e7a03132adea6fcd" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 10 10:46:42 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 08:22:00 2019 +0000" }, "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n - before:\n arm: 2396152\n arm64: 3345280\n - after:\n arm: 2016176 (-371KiB, -15.9%)\n arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n" }, { "commit": "98416bf06592493ee6fde039af5eaa5efab73acc", "tree": "a0052ec5364ce1068639a9b7d7355683eb691371", "parents": [ "63b0c26aae3e7237166dd781eb7a15fbc7c091c2" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Sep 09 14:52:12 2019 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu Oct 10 13:06:08 2019 +0100" }, "message": "Fix uses of MaybeRecordImplicitNullCheck without special scopes\n\nMaybeRecordImplicitNullCheck is a function which uses\nCodeGenerator::RecordPcInfo() and requires an exact PC. However for ARM32/ARM64,\nwhen CodeGenerator::RecordPcInfo() is used without VIXL special scopes (EmissionCheckScope,\nExactAssemblyScope) there is no guarantee of an exact PC. Without the special scopes VIXL might\nemit veneer/literal pools affecting a PC.\nThe ARM32 code generator has uses of MaybeRecordImplicitNullCheck without the\nspecial scopes.\n\nThis CL fixes missing special scopes in the ARM32/ARM64 code generators.\nIt also changes API to prevent such cases:\n1. A variant of CodeGenerator::RecordPcInfo with native_pc as a\nparameter is added. The old variant (where Assembler::CodePosition is used) is\nkept and documented that Assembler::CodePosition is target-dependent and\nmight be imprecise.\n2. CodeGenerator::MaybeRecordImplicitNullCheck is made virtual. Checks\nare added to ARM32/ARM64 code generators that\nMaybeRecordImplicitNullCheck is invoked within VIXL special scopes.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\n\nChange-Id: Ic66c16e7bdf4751cbc19a9de05846fba005b7f55\n" }, { "commit": "6a0b657a1875b4fbb020b806169e2f73fcb2578b", "tree": "955bb0e3413e18f2b13b7fee7fa3e6e48a214597", "parents": [ "61f071630083775fe64d177455a056daa7071eca" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Jul 26 20:38:37 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 02 13:31:43 2019 +0000" }, "message": "ART: ARM64: Optimize frame size for SIMD graphs.\n\nFor SIMD graphs allocate 64 bit instead of 128 bit on stack for\neach FP register to be preserved by the callee in the frame entry\nas ABI suggests (currently 64-bit registers are preserved but\nmore space on stack is allocated).\n\nNote: slow paths still require spilling full 128-bit Q-Registers\nfor SIMD graphs due to register allocator restrictions.\n\nTest: test-art-target.\nChange-Id: Ie0b12e4b769158445f3d0f4562c70d4fb0ea7744\n" }, { "commit": "2d06e029b1c84916154b5960d2acd1c84706dc04", "tree": "31dca979adebd2ed3a058b23a12a3c91ce2874d1", "parents": [ "7cde45800e21c270945b43a8989334ffc7422c32" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 08 15:45:19 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 16 08:22:46 2019 +0000" }, "message": "Clean up linker patches in codegens.\n\nIn preparation for introducing boot image extension, make\nsure that we can use both kBootImageLinkTimePcRelative and\nkBootImageRelRo load kinds at the same time.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nChange-Id: I340f2d7d19e1c20699b37b0304d2e487d497da98\n" }, { "commit": "f667508a2103cfafd1582df6aeea144490f1d11d", "tree": "7394cec1f1463a86deb75dcecca9f3eacd8ecb03", "parents": [ "8fa839cfe6f72adabdf79f938c57300e589e0803" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 17 12:05:28 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 23 11:47:28 2019 +0000" }, "message": "ARM/ARM64: Use trampolines for slow-path entrypoint calls.\n\nThis reduces the size of the generated code. We do this only\nfor AOT compilation where we get the most benefit.\n\nSizes of aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 19624804\n arm64/boot*.oat: 23265752\n oat/arm64/services.odex: 22417968\n - after:\n arm/boot*.oat: 19460500 (-160KiB)\n arm64/boot*.oat: 22957928 (-301KiB)\n oat/arm64/services.odex: 21957864 (-449KiB)\n\nTest: m test-art-host-gtest\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nBug: 12607709\nChange-Id: Ie9dbd1ba256173e4e439e8bbb8832a791965cbe6\n" }, { "commit": "0806f589a8a8e1fca573069b37761c320660aa63", "tree": "51a26fc5e59cca70a3f6875ece57aee39962221f", "parents": [ "02338775e33b553be51d44ff60bb1ef8e527bd94" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 11 20:14:20 2018 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 25 18:33:55 2018 +0100" }, "message": "ARM64: Support interm. address for object arrays.\n\nSupport IntermediateAddress on arm64 for object\narray reads in Baker read barrier configuration.\n\nThe patch brings minor boot.oat size reduction and\nperformance improvement on Puzzle benchmark.\n\nTest: test-art-target, test-art-host, gc_stress.\nTest: 527-checker-array-access-split.\n\nBug: 26601270\nBug: 32578862\n\nChange-Id: I781a911905038b36428964a990771fdf74e99bbd\n" }, { "commit": "bdb2ecc8cfd0d6fc2f3f4fa4c65cca84b358cd61", "tree": "a7660c98c22d28bf508fe208845957418e0dee40", "parents": [ "4bd4d2c199c9e0e522526c40303652e29bc7c631" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 18 14:33:55 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 19 14:46:04 2018 +0100" }, "message": "Remove sharpening as an optimization pass.\n\nMake the last sharpening helper (methods) like the other\nhelpers: being invoked by the instruction builder.\n\nTest: test.py\nChange-Id: Ic80a454f9b59b0b4ef7825590b24402500ba851c\n" }, { "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403", "tree": "0fbce767bc383358cf4cd65aafc74140e1850982", "parents": [ "19379b58bd433da91230e4fe6cd96e7416d16adc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 24 16:58:47 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 28 11:06:07 2018 +0100" }, "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n" }, { "commit": "94796f8e1b1d920c6107ffddf4efdabcf85e1da4", "tree": "e6c068b622bc60b1570eb1c54d3ddeea4972b1a2", "parents": [ "248141f724cbb9d436f13181b5301172c4385cc2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 08 15:15:33 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 14 16:36:39 2018 +0100" }, "message": "ARM64: Reimplement the UnsafeCASObject intrinsic.\n\nFor the UnsafeCASObject with Baker read barriers, drop the\nold code updating the field. Perform the main path CAS loop\nand redirect the flow for failure to a slow path that marks\nthe old value and compares it with the expected value (if\nnot marking, this is just a few instructions to determine\nthat they differ). If it\u0027s the same, the old value is known\nto be the from-space reference to the expected object and\nthe slow path performs a modified CAS loop checking for both\nexpected object references (from-space and to-space).\n\nTest: Already covered by the 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --64\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing --64\nBug: 36141117\nChange-Id: I175806dbc003640c9bb6759be6788311bcc9310c\n" }, { "commit": "248141f724cbb9d436f13181b5301172c4385cc2", "tree": "8828a0e319fa692c4a80e8cecadff7b68a845faa", "parents": [ "6e99db490fabbc38d96cc618a7aa82a99b3d07cf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 10 10:40:07 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 10 13:05:12 2018 +0100" }, "message": "ARM/ARM64: Introspection Baker RB for intrinsics.\n\nNamely Unsafe.getObject/-Volatile().\n\nTest: Additional tests in 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing\nBug: 36141117\nChange-Id: I7305d75ab0ae8c9621843f9a382ad3a5e0aefa0b\n" }, { "commit": "0ecac681bd0f55fad16027fe341f55edd632e3db", "tree": "016727b357ef37b9be41451359f5ca1c1edea8dd", "parents": [ "008e09f35541bcce782cd172d0745b802a720033" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 07 10:40:38 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 07 16:27:17 2018 +0100" }, "message": "ARM64: Introspection Baker RB for volatile fields.\n\nTest: Already covered by 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit --64\nBug: 36141117\nChange-Id: I2f9a707587d1ee27c0efb19d77becba7ec7ffec4\n" }, { "commit": "008e09f35541bcce782cd172d0745b802a720033", "tree": "8a75f77ac9f24196763038a53208266d70e3b584", "parents": [ "f5705e3502183e6dfd03facada5f5cbfab116ec7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 06 15:42:43 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 06 18:05:05 2018 +0100" }, "message": "ARM/ARM64: Clean up Baker RB introspection codegen.\n\nRemove the guard flags and remove unused code.\n\nAvoid unnecessary temporaries for JIT. This was missed in\n https://android-review.googlesource.com/725705\n\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit\nBug: 36141117\nChange-Id: Ic1bdc640db3f18d7169b0e62644f190e65a98d38\n" }, { "commit": "966b46fcba43764267069b6e19bcb2a092260418", "tree": "fe89667cbb09a981e67ebd1196d324038a6413ff", "parents": [ "98afa11c3cd8517bd28d1cad7aacaf0179c905f0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 10:20:19 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 12:35:34 2018 +0100" }, "message": "Revert^2 \"ARM/ARM64: Use introspection marking for JITted code.\"\n\nThis reverts commit 756e722c323c69a7c9891892602730e9c94b78f9.\n\nFix the introspection code to avoid avoid macro instructions\nfor unpoisoning references inside ExactAssemblyScope.\n\nChange-Id: I6effadb84de74aba0236ab84b52ca85770daf5be\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit\nTest: ART_HEAP_POISONING\u003dtrue m test-art-target-gtest\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing --jit\nBug: 36141117\n" }, { "commit": "756e722c323c69a7c9891892602730e9c94b78f9", "tree": "a2bf360d95f0aef84f3bce43f43871910a0b7ed9", "parents": [ "450f1d0fa0c40198e63c3e016f02e40ac854b0cb" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 02 17:53:46 2018 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 02 17:53:46 2018 +0000" }, "message": "Revert \"ARM/ARM64: Use introspection marking for JITted code.\"\n\nThis reverts commit 450f1d0fa0c40198e63c3e016f02e40ac854b0cb.\n\nReason for revert: breaks poisoning configuration\n\nBug: 36141117\nChange-Id: I198c20ca1db6d7d7602aa5318616e2b149de8772\n" }, { "commit": "450f1d0fa0c40198e63c3e016f02e40ac854b0cb", "tree": "0606a5c722be0d706242c015cb1218021c5c1309", "parents": [ "da6220a29fae95f17edd5374dc6bc2d4870a84da" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 25 17:27:45 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 25 18:34:19 2018 +0100" }, "message": "ARM/ARM64: Use introspection marking for JITted code.\n\nImpact on Golem benchmarks is within noise.\n\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nBug: 36141117\nChange-Id: Idf5177ee5cd34e2034d298a7907240b3e3e12d82\n" }, { "commit": "f58dc65c52f5e3f15eaaa1e25d7259e64649ade3", "tree": "4485299d9959a658909879b5a234fd807d7627ff", "parents": [ "0b4a439f808f4602c7b97364e49c5546f5100d51" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Jun 25 17:54:07 2018 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jul 13 16:30:32 2018 +0100" }, "message": "ART: Delete code optimizing a%1 and a%-1 from InstructionCodeGeneratorARM64\n\nIn InstructionWithAbsorbingInputSimplifier there is code optimizing a%1\nand a%-1. So the code in InstructionCodeGeneratorARM64 optimizing such\ncases can be deleted.\n\nThis patch deletes the code from InstructionCodeGeneratorARM64 and adds\nadditional tests.\n\nTest: 012-math, 014-math3, 411-optimizing-arith, 411-checker-hdiv-hrem-pow2\nTest: 701-easy-div-rem, 442-checker-constant-folding\nTest: test-art-host, test-art-target\nChange-Id: Ib80c0aa4c3e28b07fa79bb43783274c9d7fc456a\n" }, { "commit": "6fd1606a3f3fc2dd53ab4f8b371e420b3e33c74f", "tree": "9f944d267ce3616eb969c027665e4a451c2b3879", "parents": [ "bb089b6bf850c87e0e42917a383cc7298dcb09c5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 26 11:02:04 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 29 14:39:00 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for boot image.\n\nAnd generate only one \"boot image live objects\" array rather\nthan one per boot*.art file.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 71526895\nChange-Id: I23af7f47fea5150805f801cd2512f2d152ee5b73\n" }, { "commit": "f07d5617770c37d87447c8bddf105eb0469ab093", "tree": "e6b15b904e591a3b805b292ce9afd9b0cecbf40d", "parents": [ "2dc252e37d4df0c4160cd20b6fc852f5f28b7b87", "a043111e3a2c09b549708a6227a1f54d91da76aa" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 27 12:23:54 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 27 12:23:54 2018 +0000" }, "message": "Merge \"Move instruction_set_ to CompilerOptions.\"" }, { "commit": "a043111e3a2c09b549708a6227a1f54d91da76aa", "tree": "393fe11cfceccebf474e4bdf36ff79b70b97f589", "parents": [ "213ee2da6a1c58d0fc12c937bbd9c9974ca00aca" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 09:32:54 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 18:43:19 2018 +0100" }, "message": "Move instruction_set_ to CompilerOptions.\n\nRemoves CompilerDriver dependency from ImageWriter and\nseveral other classes.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing\nChange-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465\n" }, { "commit": "ccfc88af4ab94ff91f9b241d5113dfe7cb1f2b34", "tree": "68198426ee1a8ff1f4ee06f131be1e75fd961968", "parents": [ "ef3f32487a8a9a8b4272ea5ae372642c721ee41a", "eebb821b1adaf2db7662fc1c3ff4e9fcfe59a694" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 22 09:03:30 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 22 09:03:30 2018 +0000" }, "message": "Merge \"Implement Integer.valueOf() intrinsic for PIC.\"" }, { "commit": "bf711e388998c9233b9fc930bcf02511b6943706", "tree": "eeb66747dff7329516d85e29da22795ae51947b7", "parents": [ "5774f57afc997ffe765c32199bd0d5e55d23005a", "878f17d7737a91235013ed16ebe057a12367941b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 21 16:28:30 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jun 21 16:28:30 2018 +0000" }, "message": "Merge \"ARM64: Splitting GenerateDivRem* functions into GenerateIntDiv and GenerateIntRem functions\"" }, { "commit": "eebb821b1adaf2db7662fc1c3ff4e9fcfe59a694", "tree": "a3d3cf5f8c20d03fccdc0808537904da63e74938", "parents": [ "7e56bd41cde4e489a11050d9e340bf8b5692d9e8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 05 14:57:24 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 21 16:12:28 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for PIC.\n\nAnd fix the intrinsic for JIT even in case when someone\nmesses up the IntegerCache using reflection. Two cases are\nexposed with a regression test (one that previously failed\nrandomly and one that failed 100%) but other crashes were\npossible; for example, we would need a read barrier for\narray reads when elements are not guaranteed to be in the\nboot image.\n\nThe new approach loads references only from the boot image\nlive objects array which cannot be touched by reflection.\nThe referenced objects and IntegerCache.cache are exposed\nand can lead to weird behavior but not crashes.\n\nOn x86, the pc_relative_fixups_86 actually checks the cache\nan additional time but discrepancies between this check and\nthe location building at the beginning of codegen should be\nOK as the HIsX86ComputeBaseMethodAddress should be added\nfor PIC regardless of whether pc_relative_fixups_86 thinks\nthe method is intrinsified or not.\n\nTest: 717-integer-value-of\nTest: Pixel 2 XL boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: testrunner.py --host --jit\nTest: testrunner.py --target --optimizing --pictest --npictest\nTest: testrunner.py --target --jit\nBug: 71526895\nChange-Id: I89b3245a62aba22980c86a99e2af480bfa250af1\n" }, { "commit": "2227fe49558c5c5fc4820acb2cf357479e74b518", "tree": "bbfb6546c5da802132405569d2f06b459f12a0c3", "parents": [ "111b895dfaa271d8e9c32d1186615a0b73c106b5" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@linaro.org", "time": "Fri Apr 20 17:12:05 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 14 07:42:40 2018 +0000" }, "message": "Small refactor of MIN/MAX compiler code.\n\nIntegrate instruction code generation and location creation with\nHandleBinaryOp. Code generation has been improved for constant\ninputs 0, 1 and -1.\n\nTest: 679-checker-minmax\nTest: test-art-host, test-art-target.\n\nChange-Id: Ib34eb8a4b29d22a2491d21656e1f64011ef9f986\n" }, { "commit": "878f17d7737a91235013ed16ebe057a12367941b", "tree": "f18731e59850baf5d0535a1253643884237e889b", "parents": [ "32e83b36601e080b01712aeb6e9ebaa512eb0f33" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jun 01 16:53:58 2018 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Jun 13 21:47:36 2018 +0100" }, "message": "ARM64: Splitting GenerateDivRem* functions into GenerateIntDiv and GenerateIntRem functions\n\nVisitDiv and VisitRem call GenerateDivRemIntegral.\nGenerateDivRemIntegral does not know whether it is invoked for HDiv or\nHRem and has to check this. As a result all GenerateDivRem* functions\nhave such checks. Code for optimizing HRem and HDiv, e.g. a denominator is\npower of 2, can be specific for HRem or HDiv. So having it in\nGenerateDivRem would create issues with code maintenance.\n\nThis patch split GenerateDivRem* functions into GenerateIntDiv* and\nGenerateIntRem. BTW \u0027Integral\u0027 meaning is not \u0027Integer\u0027. So changed it\nas well. It also removes the case \u0027division by 1 or -1\u0027 because the case\nis handled in InstructionSimplifierVisitor. As there is a commonly used\nfunction Int64ConstantFrom(Location) it is used instead of\nInt64FromConstant(HConstant). This removes some code as well.\n\nTest: 012-math, 014-math3, 411-optimizing-arith\nTest: test-art-host, test-art-target\nChange-Id: I972129b24a206c8230d304be551cd2c18dbc7c9c\n" }, { "commit": "d3083dd15af1cb4ffc13d87a7d2c3be2edb9199d", "tree": "88dd2599ad89da5a4f2668a2c9debd0335669cd0", "parents": [ "6623bc389c43efc87668ce7465e19b195e765e22" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 17 08:43:47 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 22 14:38:14 2018 +0100" }, "message": "Refactor runtime callee save frame info.\n\nAnd avoid storing the info in Runtime.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nChange-Id: Ib14853fc06c420753993e1f9e82a1b01f5e35e8c\n" }, { "commit": "ca1e038eb94694f0f1f94ed3781572411c85d365", "tree": "90ad2c2494821c2f3d904eb42e61fbecd7acaf9d", "parents": [ "3f967b25650e44cd61f5a1112727a8218f2b0804" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 11 09:58:41 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 11 11:10:10 2018 +0100" }, "message": "Revert^2 \"Compile link-time thunks in codegen.\"\n\nThe linker crash (the reason for revert) is flaky and maybe\nwe shall not see it with this CL now that unrelated source\ncode has changed.\n\nTest: Rely on TreeHugger\nBug: 36141117\nBug: 77581732\n\nThis reverts commit 5806a9ec99b5494b511e84c74f494f0b3a8ebec5.\n\nChange-Id: I3a4a058847dff601681ba391abf45833424fa06d\n" }, { "commit": "5806a9ec99b5494b511e84c74f494f0b3a8ebec5", "tree": "bb50d00ff0890c2e10f351f462b47b56b01e78ea", "parents": [ "c9dd2207dfdab42586b1d6a5e7f11cf2fcea3a7a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 04 17:23:28 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 04 17:23:28 2018 +0000" }, "message": "Revert \"Compile link-time thunks in codegen.\"\n\nReason for revert: This caused clang linker crash\nin several branches.\n\nBug: 77581732\n\nThis reverts commit c9dd2207dfdab42586b1d6a5e7f11cf2fcea3a7a.\n\nChange-Id: I1923809083cf41c4f19e3e60df03ae80517aaedb\n" }, { "commit": "c9dd2207dfdab42586b1d6a5e7f11cf2fcea3a7a", "tree": "879df31fd10658093b8931117ee617064ce82519", "parents": [ "30a2d9c61da75359dee4ce90236d19fc6341b07a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 23 16:05:19 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 04 10:34:36 2018 +0100" }, "message": "Compile link-time thunks in codegen.\n\nPrepare for experimenting with Baker read barrier marking\nintrospection entrypoints for JIT.\n\nTest: m test-art-host-gtest\nTest: Compare compiled boot*.oat before and after (no diff).\nTest: Pixel 2 XL boots.\nBug: 36141117\nChange-Id: Idb413a31b158db4bf89a8707ea46dd167a06f110\n" }, { "commit": "175e7862dbdb44089ef327fc43ba00c791fd3838", "tree": "7b7ff4327b51b57e47e4b22af8d771edb9d462c1", "parents": [ "77c6fc7341143dd27c74cddd786398688d7b4c91" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 09:03:13 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 10:04:25 2018 +0100" }, "message": "Revert^4 \"Compiler changes for bitstring based type checks.\"\n\nDisabled the build time flag. (No image version bump needed.)\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\n\nThis reverts commit 3fbd3ad99fad077e5c760e7238bcd55b07d4c06e.\n\nChange-Id: I5d83c4ce8a7331c435d5155ac6e0ce1c77d60004\n" }, { "commit": "3fbd3ad99fad077e5c760e7238bcd55b07d4c06e", "tree": "e8bc33fa60c38f7e1c85f8d4acf6a738df9b426a", "parents": [ "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "message": "Revert^3 \"Compiler changes for bitstring based type checks.\"\n\nThis reverts commit 3f41323cc9da335e9aa4f3fbad90a86caa82ee4d.\n\nReason for revert: Fails sporadically.\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\nChange-Id: I84d1e9e46c58aeecf17591ff71fbac6a1e583909\n" }, { "commit": "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d", "tree": "ce41c620d2cd411da3c20aa95fb9a69328e77c42", "parents": [ "9ec1e24ebc683b15bb9c6db5554ac2ff9458adae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 12 18:39:15 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 22 12:12:39 2018 +0000" }, "message": "Revert^2 \"Compiler changes for bitstring based type checks.\"\n\nAdd extra output for debugging failures and re-enable\nthe bitstring type checks.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --host -t 670-bitstring-type-check\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --target -t 670-bitstring-type-check\nBug: 64692057\nBug: 26687569\n\nThis reverts commit bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb.\n\nChange-Id: I090e241983f3ac6ed8394d842e17716087d169ac\n" }, { "commit": "312f3b2fd0094c028a7d243b116947a35a745806", "tree": "3d7ec049ded98c489098c87250c75e3f711f8290", "parents": [ "0a3d5eb2ff9e70fa5785638da938439835d0337e" ], "author": { "name": "David Sehr", "email": "sehr@google.com", "time": "Mon Mar 19 08:39:26 2018 -0700" }, "committer": { "name": "David Sehr", "email": "sehr@google.com", "time": "Mon Mar 19 11:02:48 2018 -0700" }, "message": "Move some remaining dex utilities\n\nThere were several utilities related to building/walking/testing dex\nfiles that were not in libdexfile. This change consolidates these.\n\nBug: 22322814\nTest: make -j 50 test-art-host\nChange-Id: Id76e9179d03b8ec7d67f7e0f267121f54f0ec2e0\n" }, { "commit": "9992e095643f6746361df03c4c98e742d9ad5899", "tree": "8abf49af54ee57fc0acebf2a3d9cafd87d6ec48e", "parents": [ "a5867bfeb34529dad71220046e7327cef23af207", "e47f60c482648172334aaca59e6c1ab7a3d42610" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "message": "Merge \"Retrieve String/Class references from .data.bimg.rel.ro.\"" }, { "commit": "8ba5641ddc43fc13cdb0158bd9f3237c4a90a356", "tree": "4dad508f24b675e87dd31ff26e597289a329c5cc", "parents": [ "66f40dbc3e56c7102820842ec49a55b70cf0e151", "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "message": "Merge \"Load ArtMethod* from .data.bimg.rel.ro entries.\"" }, { "commit": "e47f60c482648172334aaca59e6c1ab7a3d42610", "tree": "ae0672b12a6ad200e1c38962c77bccfc3e5cb531", "parents": [ "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 21 13:43:28 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 10:40:12 2018 +0000" }, "message": "Retrieve String/Class references from .data.bimg.rel.ro.\n\nFor PIC AOT-compiled app, use the .data.bimg.rel.ro to load\nthe boot image String/Class references instead of using the\nmmapped boot image ClassTable and InternTable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --pictest --npictest\nBug: 71526895\nChange-Id: Id5703229777aecb589a933a41f92e44d3ec02a3d\n" }, { "commit": "b066d43b1d9184899aff32b1f243d092611ad9c6", "tree": "5409177f52b1f1c648297913cb0e0b2808b9048d", "parents": [ "fe491c7b9cdd64ff4ccc10f6b212cb92a59fc765" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 03 13:14:37 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 10:40:10 2018 +0000" }, "message": "Load ArtMethod* from .data.bimg.rel.ro entries.\n\nIntroduce a new .data.bimg.rel.ro section in oat files where\nwe store offsets of boot image objects from the beginning of\nthe boot image. At runtime we relocate these entries using\nthe actual boot image address to turn offsets to pointers.\n\nUse the .data.bimg.rel.ro to prepare the boot image methods\nused by HInvokeStaticOrDirect for PIC AOT app compilation.\nLoading the ArtMethod* from .data.bimg.rel.ro instead of the\n.bss avoids the initial call to the resolution trampoline.\n\nTest: Additional test in 522-checker-sharpening\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --pictest --npictest\nBug: 71526895\nChange-Id: Ie5f5b1f622704877b36730377146e59092e46c0c\n" }, { "commit": "351df3e70521ebbe00ed6c7ac4ea25a0c26f4034", "tree": "8a22bf2eb06d2a5e57c6d6272ac070d368467118", "parents": [ "72efc159bf4e5cde85cd28e78316681effdceb5b" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 11:54:57 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 12:00:42 2018 -0800" }, "message": "Minor cleanup of MIN/MAX code.\n\nRationale:\nShare the type dispatching code better.\n\nBug: b/65164101\n\nTest: test-art-host,target\nChange-Id: Ib06c915d570fd0a53f7734cdb316d2d16310db74\n" }, { "commit": "1f8d51bc03cbc607ae32fadf3a90f385adeffb95", "tree": "70e18902051ce47e0d524525b83709efbe6f250f", "parents": [ "7a02c66fd9ed174fc2e49ccc9f582dd661b7de9e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Feb 15 10:42:37 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 09:22:09 2018 -0800" }, "message": "Introduce MIN/MAX/ABS as HIR nodes.\n\nRationale:\nHaving explicit MIN/MAX/ABS operations (in contrast\nwith intrinsics) simplifies recognition and optimization\nof these common operations (e.g. constant folding, hoisting,\ndetection of saturation arithmetic). Furthermore, mapping\nconditionals, selectors, intrinsics, etc. (some still TBD)\nonto these operations generalizes the way they are optimized\ndownstream substantially.\n\nBug: b/65164101\n\nTest: test-art-host,target\n\nChange-Id: I69240683339356e5a012802f179298f0b04c6726\n" }, { "commit": "59eb30f96d87e3e72a060099a292ae14dd5fe1c8", "tree": "49f9334a44a28eef8d0c35c6061c61743d4db4a8", "parents": [ "5919f737facdebbe8b738272e681ae33e085de98" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 20 11:52:34 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 20 14:27:43 2018 +0000" }, "message": "ART: Clean up patching data in codegens.\n\nReuse PatchInfo\u003c\u003e for additional architectures and make the\nnaming more consistent across architectures. Change the\nDexFile reference to pointer in preparation for patching\nreferences to the upcoming .data.bimg.rel.ro section.\n\nUpdate obsolete comments; instead of referencing dex cache\narrays which were used in the past, reference the .bss and\nthe .data.bimg.rel.ro which shall be used in upcoming CLs.\n\nTest: Rely on TreeHugger.\nChange-Id: I03be4c4118918189e55c62105bb594500c6a42c1\n" }, { "commit": "bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb", "tree": "e281a8dde61e396ed5f20c31d41086b1b1b18389", "parents": [ "83af48e9f4cdfcf3f0069c63561bab4c176bd2f1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 25 13:33:07 2018 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 25 15:05:16 2018 +0000" }, "message": "Revert \"Compiler changes for bitstring based type checks.\"\n\nBug: 64692057\nBug: 71853552\nBug: 26687569\n\nThis reverts commit eb0ebed72432b3c6b8c7b38f8937d7ba736f4567.\n\nChange-Id: I7daeaa077960ba41b2ed42bc47f17501621be4be\n" }, { "commit": "eb0ebed72432b3c6b8c7b38f8937d7ba736f4567", "tree": "74d95eb4bfbf01ef6fd3a68695f5d7cec69338d7", "parents": [ "e57043081e6b091a9fd23a84043373148ae72f1f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 10 18:26:38 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 23 13:02:59 2018 +0000" }, "message": "Compiler changes for bitstring based type checks.\n\nWe guard the use of this feature with a compile-time flag,\nset to true in this CL.\n\nBoot image size for aosp_taimen-userdebug in AOSP master:\n - before:\n arm boot*.oat: 63604740\n arm64 boot*.oat: 74237864\n - after:\n arm boot*.oat: 63531172 (-72KiB, -0.1%)\n arm64 boot*.oat: 74135008 (-100KiB, -0.1%)\n\nThe new TypeCheckBenchmark yields the following changes\nusing the little cores of taimen fixed at 1.4016GHz:\n 32-bit 64-bit\n timeCheckCastLevel1ToLevel1 11.48-\u003e15.80 11.47-\u003e15.78\n timeCheckCastLevel2ToLevel1 15.08-\u003e15.79 15.08-\u003e15.79\n timeCheckCastLevel3ToLevel1 19.01-\u003e15.82 17.94-\u003e15.81\n timeCheckCastLevel9ToLevel1 42.55-\u003e15.79 42.63-\u003e15.81\n timeCheckCastLevel9ToLevel2 39.70-\u003e14.36 39.70-\u003e14.35\n timeInstanceOfLevel1ToLevel1 13.74-\u003e17.93 13.76-\u003e17.95\n timeInstanceOfLevel2ToLevel1 17.02-\u003e17.95 16.99-\u003e17.93\n timeInstanceOfLevel3ToLevel1 24.03-\u003e17.95 24.45-\u003e17.95\n timeInstanceOfLevel9ToLevel1 47.13-\u003e17.95 47.14-\u003e18.00\n timeInstanceOfLevel9ToLevel2 44.19-\u003e16.52 44.27-\u003e16.51\nThis suggests that the bitstring typecheck should not be\nused for exact type checks which would be equivalent to the\n\"Level1ToLevel1\" benchmark. Whether the implementation is\na beneficial replacement for the kClassHierarchyCheck and\nkAbstractClassCheck on average depends on how many levels\nfrom the target class (or Object for a negative result) is\na typical object\u0027s class.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --host -t 670-bitstring-type-check\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --target -t 670-bitstring-type-check\nBug: 64692057\nBug: 71853552\nBug: 26687569\nChange-Id: I538d7e036b5a8ae2cc3fe77662a5903d74854562\n" }, { "commit": "9e734c7ab4599d7747a05db0dc73c7b668cb6683", "tree": "dce1d1993734a947fb2e6f626eb1b425cb72143b", "parents": [ "b496af808eaf3af5ebac50aef4fbec33323b5016" ], "author": { "name": "David Sehr", "email": "sehr@google.com", "time": "Thu Jan 04 17:56:19 2018 -0800" }, "committer": { "name": "David Sehr", "email": "sehr@google.com", "time": "Fri Jan 05 11:07:19 2018 -0800" }, "message": "Create dex subdirectory\n\nMove all the DexFile related source to a common subdirectory dex/ of\nruntime.\n\nBug: 71361973\nTest: make -j 50 test-art-host\nChange-Id: I59e984ed660b93e0776556308be3d653722f5223\n" }, { "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1", "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07", "parents": [ "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 14:49:14 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 06 17:53:50 2017 +0100" }, "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n" }, { "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32", "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af", "parents": [ "e1e347dace0ded83774999bb26c37527dcdb1d5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 22:50:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 25 15:45:01 2017 +0100" }, "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n" }, { "commit": "d8dbc8da0e5cc6b5c2176ce2d3877e6194d72c0c", "tree": "af6e9fb02471d75ebdea46190a0aa3e9dbdb892d", "parents": [ "93780a60090356921b844dbefdc13442c9f18b52" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 13:37:47 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 15:55:10 2017 +0100" }, "message": "Refactor compiled_method.h .\n\nMove LinkerPatch to compiler/linker/linker_patch.h .\nMove SrcMapElem to compiler/debug/src_map_elem.h .\nIntroduce compiled_method-inl.h to reduce the number\nof `#include`s in compiled_method.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: Id211cdf94a63ad265bf4709f1a5e06dffbe30f64\n" }, { "commit": "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63", "tree": "f92b309ddc43c2254b6067346a653170fbbf7316", "parents": [ "0f3c7003e08a42a4ed8c9f8dfffb1bee1118de59" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 25 13:26:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 07 17:52:35 2017 +0100" }, "message": "Use mmapped boot image intern table for PIC app HLoadString.\n\nImplement new HLoadString load kind for boot image strings\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image InternTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image strings compared to the kBssEntry\nas we can completely avoid the slow path and stack map.\n\nWe separate the InternedStrings and ClassTable sections of\nthe boot image (.art) file from the rest, aligning the\nstart of the InternedStrings section to a page boundary.\nThis may actually increase the size of the boot image file\nby a page but it also allows mprotecting() these tables as\nread-only. The ClassTable section is included in\nanticipation of a similar load kind for HLoadClass.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20862776\n - after: 20308512 (-541KiB)\nNote that 92KiB savings could have been achieved by simply\navoiding the read barrier, similar to the HLoadClass flag\nIsInBootImage(). Such flag is now unnecessary.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I5f2bf1fc0bb36a8483244317cfdfa69e192ef6c5\n" }, { "commit": "2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40", "tree": "4d5fb728acd7f98f8949c84364375a804ff0ba63", "parents": [ "461ec567f16039374dff35e2f3b808986c100249" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jun 06 16:09:59 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 10 18:17:47 2017 +0100" }, "message": "Instrument ARM64 generated code to check the Marking Register.\n\nGenerate run-time code in the Optimizing compiler checking that\nthe Marking Register\u0027s value matches `self.tls32_.is.gc_marking`\nin debug mode (on target; and on host with JIT, or with AOT when\ncompiling the core image). If a check fails, abort.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test with libartd.\nBug: 37707231\nChange-Id: Ie9b322b22b3d26654a06821e1db71dbda3c43061\n" }, { "commit": "97c46466aea25ab63a99b3d1afc558f0d9f55abb", "tree": "afd225f51d28a77329bc2590a025400e088f260c", "parents": [ "00cca3a275562d110a8b35094b9b12fac37f67ab" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu May 11 14:04:03 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 11 17:43:27 2017 +0100" }, "message": "Introduce a Marking Register in ARM64 code generation.\n\nWhen generating code for ARM64, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register X20,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test\nBug: 37707231\nChange-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b\n" }, { "commit": "0eb882bfc5d260e8014c26adfda11602065aa5d8", "tree": "e66dbebfb1e9a254c20954a2f2f98541aebfd5af", "parents": [ "b5f5d746ac3f2c3088292395603cb1470e7749d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 15 13:39:18 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 15:39:24 2017 +0100" }, "message": "Use ArtMethod* .bss entries for HInvokeStaticOrDirect.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug.\nBug: 30627598\nChange-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f\n" }, { "commit": "e7197bf7d58c705a048e13e241d7ca320502cd40", "tree": "496032b40145660b40002b9d5b7a78f1c2eeb44f", "parents": [ "4ee8e291a7d5b7b98f35f495eb97705836910871" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 17:00:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 06 15:26:42 2017 +0100" }, "message": "Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\n\nIn preparation for replacing the dex cache method array\nwith a hash-based array, get rid of one unnecessary use.\nThis method load kind is currently used only on mips for\nirreducible loops and OSR, so this should have no impact\non x86/x86-64/arm/arm64.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Repeat the above tests with manually changing\n kDexCachePcRelative to kRuntimeCall in sharpening.cc.\n (Ignore failures in 552-checker-sharpening.)\nBug: 30627598\nChange-Id: Ifce42645f2dcc350bbb88c2f4642e88fc5f98152\n" }, { "commit": "d254f5c0d7b43397e8b8885a56ec4d36e9b61602", "tree": "ef645025a42f88a2c9eb0ab9483ff519886f0a4c", "parents": [ "cff1b21b3e19c5d3a2d726fdb60dacd7de2a6f0d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 15:18:36 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 16:24:33 2017 +0100" }, "message": "Revert \"ART: Reference.getReferent intrinsic for arm and arm64\"\n\nReverting because GenerateCalleeMethodStaticOrDirectCall()\nprevents replacing kDexCacheViaMethod with kRuntimeCall\nwhere we would not retrieve the target method at all and\nleave the runtime to retrieve and call it just like for\nunresolved methods.\n\nThe intrinsic should be re-implemented by loading the\nflags through HLoadClass.\n\nNote that the intrinsic was unimplemented for CC and a bit\nbroken for non-CC, using LDR instead of LDRB for loading\nthe flags.\n\nTest: Rely on TreeHugger.\nBug: 32535355\nBug: 30627598\n\nThis reverts commit d8c052ac0aa3382c4807add33afa32580ffeecbb.\n\nChange-Id: I81fd14dac60c94ac543e336f4f3c888259fc8bd7\n" }, { "commit": "dbddc22f5dc2d1ff4d4783fbd66c27812f4980d1", "tree": "2a0a8efa1c2630e57ab48ab2de171f2847ff282f", "parents": [ "a559fa1b0d6c276dde2cdc707de1acd4950f7190" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed May 24 12:04:13 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu May 25 16:59:44 2017 -0700" }, "message": "Refactor profiles to use TypeReference instead of ClassReference\n\nRefactor type reference into runtime and use it for profiles.\nClassReference was just duplicated code since it wasn\u0027t even using\nthe class def indexes.\n\nTest: test-art-host\n\nBug: 62040831\nChange-Id: Ia92f21c0e85c00321f52c97bb7a90158d882849b\n" }, { "commit": "6597946d29be9108e2cc51223553d3db9290a3d9", "tree": "cea6647a45cc59fa1423751179e647124f269990", "parents": [ "a654e0378a8d0bb149362399917e4da2959e6991" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 19 17:25:12 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 22 18:35:05 2017 +0100" }, "message": "Use PC-relative pointer to boot image methods.\n\nIn preparation for adding ArtMethod entries to the .bss\nsection, add direct PC-relative pointers to methods so that\nthe number of needed .bss entries for boot image is small.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target on Nexus 6P\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug\nBug: 30627598\nChange-Id: Ia89f5f9975b741ddac2816e1570077ba4b4c020f\n" }, { "commit": "764d454d1d51448deb81f6e8d2d7d317c7f4d1b4", "tree": "029f9e65cfe7e953df55b7af45e099924ffdbbac", "parents": [ "7974468d32b817be1d49dfcf513605f646c481bc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 10:31:41 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 15:08:55 2017 +0100" }, "message": "Remove LoadString/Class kind kBootImageLinkTimeAddress.\n\nWe no longer support non-PIC boot image compilation.\n\nAlso clean up some obsolete code for method patches\nand make JIT correctly report itself as non-PIC.\n\nTest: testrunner.py --host\nTest: testrunner.py --target\nBug: 33192586\nChange-Id: I593289c5c1b0e88b82b86a933038be97bbb15ad2\n" }, { "commit": "ff48700df9da9aa0c6a8c1f65c9d862f936e1a89", "tree": "932dd5749a82d9477d24200db6d747d6008a0a5d", "parents": [ "15cb9753075bcaa5b91a6497a2d35e8bd98af1f0" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 07 16:50:01 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri May 05 16:08:50 2017 +0100" }, "message": "Improve the implementation of UnsafeCASObject with Baker read barriers.\n\nOn ARM and ARM64, avoid loading the reference altogether when the\nGC is not marking.\n\nAlso, extract the code logic for updating a reference field from\nGenerateReferenceLoadWithBakerReadBarrier routines and move it to\nnew routines (UpdateReferenceFieldWithBakerReadBarrier), to make\nthe implementation more legible.\n\nTest: Run ART target tests in Baker read barrier configuration.\nBug: 29516974\nChange-Id: I11c53f0607e997cd02ec7911725e98ef3dc97d90\n" }, { "commit": "472821b210a7fc7a4d2e3d45762c7b5b9628a35b", "tree": "d3dad427cdfcf4ebe8d324bcd3b7618ed42d14dd", "parents": [ "70940dfe99df0084a3f3fed1a88255ec976a60e3" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Apr 27 17:23:51 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Apr 28 09:49:26 2017 -0700" }, "message": "Enable string \"array get\" vectorization.\n\nRationale:\nLike its scalar counterpart, the SIMD implementation of array get from\na string needs to deal with compressed and uncompressed cases.\nMicro benchmarks shows 2x to 3x speedup for just copying data!\n\nTest: test-art-target, test-art-host\nChange-Id: I2fd714e50715b263123c215cd181f19194456d2b\n" }, { "commit": "0225b7712202d95ac7ba40ec96e95e14c4ce0895", "tree": "cb5fdd6a7b95322ce7fa95b77aba8021e287c7fb", "parents": [ "6d3c61d8c6d2f96dec8345263c948fae3caa4e1a" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Apr 19 15:43:53 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Apr 21 17:41:42 2017 +0100" }, "message": "ARM64: Improve SIMD LDR/STR.\n\nTest: 640-checker-*-simd\nTest: test-art-target, test-art-host\n\nChange-Id: I2bcdef3f5cb7c0e7d1b3d02910fbf89ac694d89a\n" }, { "commit": "7b331261c6bdb6316a649ab591813f4dd1a5892f", "tree": "22b60227265c73903428ea55cde3123ea992ac4e", "parents": [ "b1a52116a1ca418dcccad2ca2acd6cb36f8ca0e7", "f4f2daafb38c9c07ea74044a0fb89a2a19288b7a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 13 12:54:22 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 13 12:54:23 2017 +0000" }, "message": "Merge \"ARM64: Use link-time generated thunks for Baker CC read barrier.\"" }, { "commit": "f4f2daafb38c9c07ea74044a0fb89a2a19288b7a", "tree": "13fd63a65c12e60074bc2bc1e693fbb3b788ed8e", "parents": [ "26c25d5da32fe1bdd94dd1404197c14994ecab60" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Mar 20 18:26:59 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 12 17:02:06 2017 +0100" }, "message": "ARM64: Use link-time generated thunks for Baker CC read barrier.\n\nRemaining work for follow-up CLs:\n - array loads,\n - volatile field loads,\n - use implicit null check in field thunk.\n\nTest: Added tests to relative_patcher_arm64\nTest: New run-test 160-read-barrier-stress\nTest: m test-art-target-gtest on Nexus 6P.\nTest: testrunner.py --target on Nexus 6P.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: Id68ff171c55a3f1bf1ac1b657f480531aa7b3710\n" }, { "commit": "d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331", "tree": "2890740d9cab3eee2be223666f528c6707b89f90", "parents": [ "903b8169074c01590ab3f5ad9190d9c7e3fe795b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 03 18:47:32 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 10 11:43:33 2017 +0100" }, "message": "ARM64: Support 128-bit registers for SIMD.\n\nTest: test-art-host, test-art-target\n\nChange-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa\n" }, { "commit": "f8f5a16ed7bad1e18179e38453e59c96a944de10", "tree": "53369083a97103563467cc5910a439a1864dd0b1", "parents": [ "7298b1ae3e9af5fdb46d168302a26cfbf5d475f5" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 06 15:35:29 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Mar 31 10:58:11 2017 -0700" }, "message": "ART vectorizer.\n\nRationale:\nMake SIMD great again with a retargetable and easily extendable vectorizer.\n\nProvides a full x86/x86_64 and a proof-of-concept ARM implementation. Sample\nimprovement (without any perf tuning yet) for Linpack on x86 is about 20% to 50%.\n\nTest: test-art-host, test-art-target (angler)\nBug: 34083438, 30933338\n\nChange-Id: Ifb77a0f25f690a87cd65bf3d5e9f6be7ea71d6c1\n" }, { "commit": "5ed51e3176f3dc4ff2e50ba4bf52743d404b5b4f", "tree": "1638115757601e4d41d1dc3f3cb9045f5d3d6dd9", "parents": [ "079f5fd58799a23aa5d60a5f85008a4663a33f2a", "54f869ed3c7910e6eb7bade924d41570e9a4cb14" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Mar 09 13:02:12 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 09 13:02:12 2017 +0000" }, "message": "Merge changes Ia26b07f0,Id3d2758c\n\n* changes:\n Revert \"Revert \"Use the holder\u0027s gray bit in Baker read barrier slow paths (ARM, ARM64).\"\"\n Revert \"Revert \"Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\"\"\n" }, { "commit": "c52f3034b06c03632e937aff07d46c2bdcadfef5", "tree": "031e4d1b2ca0961014e57e4987d80d7aa2c435b0", "parents": [ "ef81e988d0eb4db390e576aac346701b2d820916" ], "author": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Thu Mar 02 13:45:45 2017 +0000" }, "committer": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Wed Mar 08 10:55:17 2017 +0000" }, "message": "Remove --include-patch-information option from dex2oat.\n\nBecause we no longer support running patchoat on npic oat files, which\nmeans the included patch information is unused .\n\nBug: 33192586\nTest: m test-art-host\n\nChange-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67\n" }, { "commit": "ba650a4d5a0a82c6c88d6546b6111013c2ee8072", "tree": "cc3046a30aab382cc9c346391ca7cc22f3bf11ad", "parents": [ "ef81e988d0eb4db390e576aac346701b2d820916" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Mar 06 13:52:32 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Mar 06 13:57:15 2017 +0000" }, "message": "Revert \"Revert \"Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\"\"\n\nThis reverts commit 35345a555bd7928582a7ffa6369b374b3ddc379d.\n\nIn compiler-generated code, when deciding whether to mark\na heap reference or not in a read barrier, check whether\nthe GC is currently marking, instead of checking the gray\nbit in the reference\u0027s holder\u0027s lock word.\n\nThis change is only for ARM and ARM64, as it does not\nbenefit x86 nor x86-64.\n\nChange-Id: Id3d2758c600115b2f07d345442cfa87edfc2792c\nTest: Run ART tests in Baker read barrier configuration.\nTest: Boot a device in Baker read barrier configuration.\nBug: 35780827\nBug: 29516974\n" }, { "commit": "35345a555bd7928582a7ffa6369b374b3ddc379d", "tree": "ef5e6236203e04b59151b2e1b1529f9b389957b4", "parents": [ "e25fc07d3d3b31fe46cb02a3ed0933c7af3999fd" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Feb 27 14:32:08 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Feb 27 14:33:37 2017 +0000" }, "message": "Revert \"Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\"\n\nThis reverts commit 1372c9f40df1e47bf775f1466bbb96f472b6b9ed.\n\nThis change (along with https://android-review.googlesource.com/#/c/342429/)\ncreates null pointer dereferences.\n\nBug: 35780827\nBug: 29516974\nChange-Id: I2a9c4d0ad8d2ab870c2e0ddbff32152933c77abe\n" }, { "commit": "1372c9f40df1e47bf775f1466bbb96f472b6b9ed", "tree": "d00923d1045ab66c6aa07ed5a42a69899580d210", "parents": [ "6cc0250f1d1507957fc2fe1543179eab5a8b53f9" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 13 11:47:39 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 23 13:50:11 2017 +0000" }, "message": "Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\n\nIn compiler-generated code, when deciding whether to mark\na heap reference or not in a read barrier, check whether\nthe GC is currently marking, instead of checking the gray\nbit in the reference\u0027s holder\u0027s lock word.\n\nThis change is only for ARM and ARM64, as it does not\nbenefit x86 nor x86-64.\n\nTest: Run ART tests in Baker read barrier configuration.\nTest: Boot a device in Baker read barrier configuration.\nBug: 29516974\nChange-Id: Ia5d90286bb9f753f3bbcb3a6254eb166523a2ff5\n" }, { "commit": "914d7a8fca1184837475016d186585d863e81830", "tree": "e0b2ea229d4071d3d1149aa3c60307b75e350d6c", "parents": [ "4e4b62e21672dbacf5d5abb688a126aabad29269" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Feb 07 14:33:49 2017 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Feb 10 15:12:36 2017 +0000" }, "message": "ARM64: Remove all uses of BlockPoolsScope.\n\nBlockPoolsScope should not be used because it is a VIXL scope\nfor VIXL internal usage only. In arm64 backend the intent was to\nblock pools between a particular instruction (Ldr, Str, Blr, etc)\nand a subsequent MaybeRecordImplicitNullCheck or RecordPcInfo call.\nHowever pools should be emitted at the opening of a scope if this\nis required to satisfy branch/ldr ranges. This is not done by the\nBlockPoolsScope, so proper scopes are now used now:\nExactAssemblyScope and EmissionCheckScope.\n\nTest: test-art-host\nTest: test-art-target\n\nBug: 34850123\n\nChange-Id: I30365ad63c644cf9dd85d5a3c2118f9c57be9d20\n" }, { "commit": "8e0e7f78431d7c6fcdaa8e0f8de9ea130a265d53", "tree": "c156e098fd7a92e2c81d487b6e31a7b24e69eecd", "parents": [ "334b51132a2fd1a396822a3aa80129224c94e721", "5b3c6c0fcca76d82a4c9acb03f7714457ae53dd9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 26 12:35:06 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 26 12:35:07 2017 +0000" }, "message": "Merge \"Refactor code for unresolved field entrypoint.\"" }, { "commit": "5b3c6c0fcca76d82a4c9acb03f7714457ae53dd9", "tree": "e1678dcd577abb63391a0cfcbb27a69a0ac4e769", "parents": [ "c9569731061e560cb56116255b00a49d6a5daeb8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 19 14:22:26 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 26 10:37:58 2017 +0000" }, "message": "Refactor code for unresolved field entrypoint.\n\n- Do macro magic to avoid source code duplication.\n- Do not fetch the referrer from the assembly, but\n from the C entrypoint instead.\n\nTest: test-art-host test-art-target\n\nChange-Id: Ib139c94bc8f74686640cad538ba75dc56fa00e1d\n" }, { "commit": "c51842b8dd2ad57a1b05f31ab20ad01123443c50", "tree": "1f252e84d65dda9e301e2db3760adcbddb55bed6", "parents": [ "b0dde4397fa5b0756312b46bd18477a2c1f6a7da", "d8c052ac0aa3382c4807add33afa32580ffeecbb" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jan 23 16:48:50 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 23 16:48:51 2017 +0000" }, "message": "Merge \"ART: Reference.getReferent intrinsic for arm and arm64\"" }, { "commit": "d8c052ac0aa3382c4807add33afa32580ffeecbb", "tree": "97679692824fee4b12b03b4d71cb0763a8233e70", "parents": [ "4cd515521828b1f9ce0d5e2f545cb3376a94e9f3" ], "author": { "name": "TatWai Chong", "email": "tatwai.chong@linaro.org", "time": "Wed Nov 02 16:12:48 2016 +0800" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jan 23 14:20:35 2017 +0000" }, "message": "ART: Reference.getReferent intrinsic for arm and arm64\n\nTest: m test-art-host\nTest: m test-art-target\nTest: export ART_HEAP_POISONING\u003dtrue; m test-art-host\nTest: export ART_HEAP_POISONING\u003dtrue; m test-art-target\nBug: 32535355\nChange-Id: Ie63317689dd9e03a24e701c30411f8014970173a\n" }, { "commit": "5247c08fb186a5a2ac02226827cf6b994f41a681", "tree": "8b1305f9fb918024302382b8e8aa43962098e9fa", "parents": [ "0d478f289f0e33f19693d135f1d562b57427ed32" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 13 14:17:29 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 16 23:42:09 2017 +0000" }, "message": "Put the resolved class in HLoadClass.\n\nTo avoid repeated lookups in sharpening/rtp/inlining.\n\nTest: test-art-host test-art-target\nChange-Id: I08d0da36a4bb061cdaa490ea2af3a3217a875bbe\n" }, { "commit": "1998cd02603197f2acdc0734397a6d48b2f59b80", "tree": "aa639c7ec96f71d7aaf5d0c865a8a133dbc457c3", "parents": [ "6bec91c7d4670905cd67440991ec76fd54d0f000" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 13 13:02:58 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 13:39:24 2017 +0000" }, "message": "Implement HLoadClass/kBssEntry for boot image.\n\nTest: m test-art-host\nTest: m test-art-host with CC\nTest: m test-art-target on Nexus 9\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng\nBug: 30627598\nChange-Id: I168f24dedd5fb54a1e4215ecafb947ffb0dc3280\n" }, { "commit": "6bec91c7d4670905cd67440991ec76fd54d0f000", "tree": "05f4ba288e629270773c65b34b71be7bae5e92ff", "parents": [ "4155998a2f5c7a252a6611e3926943e931ea280a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 09 15:03:12 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Store resolved types for AOT code in .bss.\n\nTest: m test-art-host\nTest: m test-art-target on Nexus 9.\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng.\nBug: 30627598\nBug: 34193123\nChange-Id: I8ec60a98eb488cb46ae3ea56341f5709dad4f623\n" }, { "commit": "f0acfe7a812a332122011832074142718c278dae", "tree": "49c4fc481cebd03323aaf0109066859165508303", "parents": [ "91db41f315f6c2366b7098c531224bee01170364" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 09 20:54:52 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 10 21:26:23 2017 +0000" }, "message": "Keep resolved String in HLoadString.\n\nFor the following reasons:\n- Avoids needing to do a lookup again in CodeGenerator::EmitJitRoots.\n- Fixes races where we the string was GC\u0027ed before CodeGenerator::EmitJitRoots.\n- Makes it possible to do GVN on the same string but defined in different\n dex files.\n\nTest: test-art-host, test-art-target\nChange-Id: If2b5d3079f7555427b1b96ab04546b3373fcf921\n" }, { "commit": "c1a42cf3873be202c8c0ca3c4e67500b470ab075", "tree": "f2bffbd14e1f9d5429dd8514d19be4fa6dfa392f", "parents": [ "06ce6d4359ed897f1d1b39be4e748f0c4f3ca2ff" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Dec 18 15:52:36 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 20 13:29:45 2016 +0000" }, "message": "Remove soon to be obsolete call kinds for direct calls.\n\nAnd remove CompilerDriver::GetCodeAndMethodForDirectCall in\npreparation of removing non-PIC prebuild and non-PIC on-device\nboot image compilation.\n\nTest: test-art-host test-art-target\nbug:33192586\nChange-Id: Ic48e3e8b9d7605dd0e66f31d458a182198ba9578\n" }, { "commit": "0f0829ba15e4ed54472fb6ebac3a19b101d03db3", "tree": "d968014b299db7fd4eaf23dde82cad3572d8147a", "parents": [ "1e35a69a44bbf3999ec1829e501d7305bd9fc9d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 13 13:50:14 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 13 13:50:14 2016 +0000" }, "message": "Remove obsolete DeduplicateDexCacheAddressLiteral().\n\nTest: Rely on TreeHugger\nBug: 30627598\nChange-Id: Ia3c7a1d528f62b730d7ac1cc7b67f21d9ff06c9e\n" }, { "commit": "22384aeab988df7fa5ccdc48a668589c5f602c39", "tree": "daca06adfc92c93017618c3729af54ed40214ba4", "parents": [ "0ee6447c63e354131dec78743ccabcbc964129e3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 22:33:36 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 23:06:38 2016 +0000" }, "message": "Revert \"Revert \"Add kJitTableAddress for HLoadClass.\"\"\n\nThis reverts commit d2d5262c8370309e1f2a009f00aafc24f1cf00a0.\n\nChange-Id: I6149d5c7d5df0b0fc5cb646a802a2eea8d01ac08\n" }, { "commit": "d2d5262c8370309e1f2a009f00aafc24f1cf00a0", "tree": "15b542ac079f30043cd3654cf5d3c40ae3ea34d0", "parents": [ "5b12f7973636bfea29da3956a9baa7a6bbe2b666" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 16:28:54 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 16:28:54 2016 +0000" }, "message": "Revert \"Add kJitTableAddress for HLoadClass.\"\n\nOne test failure after merge.\n\nThis reverts commit 5b12f7973636bfea29da3956a9baa7a6bbe2b666.\n\nChange-Id: I120c49e53274471fc1c82a10d52e99c83f5f85cc\n" } ], "next": "5b12f7973636bfea29da3956a9baa7a6bbe2b666" }