)]}' { "log": [ { "commit": "6a0b657a1875b4fbb020b806169e2f73fcb2578b", "tree": "955bb0e3413e18f2b13b7fee7fa3e6e48a214597", "parents": [ "61f071630083775fe64d177455a056daa7071eca" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Jul 26 20:38:37 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 02 13:31:43 2019 +0000" }, "message": "ART: ARM64: Optimize frame size for SIMD graphs.\n\nFor SIMD graphs allocate 64 bit instead of 128 bit on stack for\neach FP register to be preserved by the callee in the frame entry\nas ABI suggests (currently 64-bit registers are preserved but\nmore space on stack is allocated).\n\nNote: slow paths still require spilling full 128-bit Q-Registers\nfor SIMD graphs due to register allocator restrictions.\n\nTest: test-art-target.\nChange-Id: Ie0b12e4b769158445f3d0f4562c70d4fb0ea7744\n" }, { "commit": "2d06e029b1c84916154b5960d2acd1c84706dc04", "tree": "31dca979adebd2ed3a058b23a12a3c91ce2874d1", "parents": [ "7cde45800e21c270945b43a8989334ffc7422c32" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 08 15:45:19 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 16 08:22:46 2019 +0000" }, "message": "Clean up linker patches in codegens.\n\nIn preparation for introducing boot image extension, make\nsure that we can use both kBootImageLinkTimePcRelative and\nkBootImageRelRo load kinds at the same time.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nChange-Id: I340f2d7d19e1c20699b37b0304d2e487d497da98\n" }, { "commit": "bdb2ecc8cfd0d6fc2f3f4fa4c65cca84b358cd61", "tree": "a7660c98c22d28bf508fe208845957418e0dee40", "parents": [ "4bd4d2c199c9e0e522526c40303652e29bc7c631" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 18 14:33:55 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 19 14:46:04 2018 +0100" }, "message": "Remove sharpening as an optimization pass.\n\nMake the last sharpening helper (methods) like the other\nhelpers: being invoked by the instruction builder.\n\nTest: test.py\nChange-Id: Ic80a454f9b59b0b4ef7825590b24402500ba851c\n" }, { "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403", "tree": "0fbce767bc383358cf4cd65aafc74140e1850982", "parents": [ "19379b58bd433da91230e4fe6cd96e7416d16adc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 24 16:58:47 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 28 11:06:07 2018 +0100" }, "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n" }, { "commit": "6fd1606a3f3fc2dd53ab4f8b371e420b3e33c74f", "tree": "9f944d267ce3616eb969c027665e4a451c2b3879", "parents": [ "bb089b6bf850c87e0e42917a383cc7298dcb09c5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 26 11:02:04 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 29 14:39:00 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for boot image.\n\nAnd generate only one \"boot image live objects\" array rather\nthan one per boot*.art file.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 71526895\nChange-Id: I23af7f47fea5150805f801cd2512f2d152ee5b73\n" }, { "commit": "a043111e3a2c09b549708a6227a1f54d91da76aa", "tree": "393fe11cfceccebf474e4bdf36ff79b70b97f589", "parents": [ "213ee2da6a1c58d0fc12c937bbd9c9974ca00aca" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 09:32:54 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 18:43:19 2018 +0100" }, "message": "Move instruction_set_ to CompilerOptions.\n\nRemoves CompilerDriver dependency from ImageWriter and\nseveral other classes.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing\nChange-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465\n" }, { "commit": "eebb821b1adaf2db7662fc1c3ff4e9fcfe59a694", "tree": "a3d3cf5f8c20d03fccdc0808537904da63e74938", "parents": [ "7e56bd41cde4e489a11050d9e340bf8b5692d9e8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 05 14:57:24 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 21 16:12:28 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for PIC.\n\nAnd fix the intrinsic for JIT even in case when someone\nmesses up the IntegerCache using reflection. Two cases are\nexposed with a regression test (one that previously failed\nrandomly and one that failed 100%) but other crashes were\npossible; for example, we would need a read barrier for\narray reads when elements are not guaranteed to be in the\nboot image.\n\nThe new approach loads references only from the boot image\nlive objects array which cannot be touched by reflection.\nThe referenced objects and IntegerCache.cache are exposed\nand can lead to weird behavior but not crashes.\n\nOn x86, the pc_relative_fixups_86 actually checks the cache\nan additional time but discrepancies between this check and\nthe location building at the beginning of codegen should be\nOK as the HIsX86ComputeBaseMethodAddress should be added\nfor PIC regardless of whether pc_relative_fixups_86 thinks\nthe method is intrinsified or not.\n\nTest: 717-integer-value-of\nTest: Pixel 2 XL boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: testrunner.py --host --jit\nTest: testrunner.py --target --optimizing --pictest --npictest\nTest: testrunner.py --target --jit\nBug: 71526895\nChange-Id: I89b3245a62aba22980c86a99e2af480bfa250af1\n" }, { "commit": "175e7862dbdb44089ef327fc43ba00c791fd3838", "tree": "7b7ff4327b51b57e47e4b22af8d771edb9d462c1", "parents": [ "77c6fc7341143dd27c74cddd786398688d7b4c91" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 09:03:13 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 10:04:25 2018 +0100" }, "message": "Revert^4 \"Compiler changes for bitstring based type checks.\"\n\nDisabled the build time flag. (No image version bump needed.)\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\n\nThis reverts commit 3fbd3ad99fad077e5c760e7238bcd55b07d4c06e.\n\nChange-Id: I5d83c4ce8a7331c435d5155ac6e0ce1c77d60004\n" }, { "commit": "3fbd3ad99fad077e5c760e7238bcd55b07d4c06e", "tree": "e8bc33fa60c38f7e1c85f8d4acf6a738df9b426a", "parents": [ "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "message": "Revert^3 \"Compiler changes for bitstring based type checks.\"\n\nThis reverts commit 3f41323cc9da335e9aa4f3fbad90a86caa82ee4d.\n\nReason for revert: Fails sporadically.\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\nChange-Id: I84d1e9e46c58aeecf17591ff71fbac6a1e583909\n" }, { "commit": "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d", "tree": "ce41c620d2cd411da3c20aa95fb9a69328e77c42", "parents": [ "9ec1e24ebc683b15bb9c6db5554ac2ff9458adae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 12 18:39:15 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 22 12:12:39 2018 +0000" }, "message": "Revert^2 \"Compiler changes for bitstring based type checks.\"\n\nAdd extra output for debugging failures and re-enable\nthe bitstring type checks.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --host -t 670-bitstring-type-check\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --target -t 670-bitstring-type-check\nBug: 64692057\nBug: 26687569\n\nThis reverts commit bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb.\n\nChange-Id: I090e241983f3ac6ed8394d842e17716087d169ac\n" }, { "commit": "312f3b2fd0094c028a7d243b116947a35a745806", "tree": "3d7ec049ded98c489098c87250c75e3f711f8290", "parents": [ "0a3d5eb2ff9e70fa5785638da938439835d0337e" ], "author": { "name": "David Sehr", "email": "sehr@google.com", "time": "Mon Mar 19 08:39:26 2018 -0700" }, "committer": { "name": "David Sehr", "email": "sehr@google.com", "time": "Mon Mar 19 11:02:48 2018 -0700" }, "message": "Move some remaining dex utilities\n\nThere were several utilities related to building/walking/testing dex\nfiles that were not in libdexfile. This change consolidates these.\n\nBug: 22322814\nTest: make -j 50 test-art-host\nChange-Id: Id76e9179d03b8ec7d67f7e0f267121f54f0ec2e0\n" }, { "commit": "9992e095643f6746361df03c4c98e742d9ad5899", "tree": "8abf49af54ee57fc0acebf2a3d9cafd87d6ec48e", "parents": [ "a5867bfeb34529dad71220046e7327cef23af207", "e47f60c482648172334aaca59e6c1ab7a3d42610" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "message": "Merge \"Retrieve String/Class references from .data.bimg.rel.ro.\"" }, { "commit": "8ba5641ddc43fc13cdb0158bd9f3237c4a90a356", "tree": "4dad508f24b675e87dd31ff26e597289a329c5cc", "parents": [ "66f40dbc3e56c7102820842ec49a55b70cf0e151", "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "message": "Merge \"Load ArtMethod* from .data.bimg.rel.ro entries.\"" }, { "commit": "e47f60c482648172334aaca59e6c1ab7a3d42610", "tree": "ae0672b12a6ad200e1c38962c77bccfc3e5cb531", "parents": [ "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 21 13:43:28 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 10:40:12 2018 +0000" }, "message": "Retrieve String/Class references from .data.bimg.rel.ro.\n\nFor PIC AOT-compiled app, use the .data.bimg.rel.ro to load\nthe boot image String/Class references instead of using the\nmmapped boot image ClassTable and InternTable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --pictest --npictest\nBug: 71526895\nChange-Id: Id5703229777aecb589a933a41f92e44d3ec02a3d\n" }, { "commit": "b066d43b1d9184899aff32b1f243d092611ad9c6", "tree": "5409177f52b1f1c648297913cb0e0b2808b9048d", "parents": [ "fe491c7b9cdd64ff4ccc10f6b212cb92a59fc765" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 03 13:14:37 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 10:40:10 2018 +0000" }, "message": "Load ArtMethod* from .data.bimg.rel.ro entries.\n\nIntroduce a new .data.bimg.rel.ro section in oat files where\nwe store offsets of boot image objects from the beginning of\nthe boot image. At runtime we relocate these entries using\nthe actual boot image address to turn offsets to pointers.\n\nUse the .data.bimg.rel.ro to prepare the boot image methods\nused by HInvokeStaticOrDirect for PIC AOT app compilation.\nLoading the ArtMethod* from .data.bimg.rel.ro instead of the\n.bss avoids the initial call to the resolution trampoline.\n\nTest: Additional test in 522-checker-sharpening\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --pictest --npictest\nBug: 71526895\nChange-Id: Ie5f5b1f622704877b36730377146e59092e46c0c\n" }, { "commit": "351df3e70521ebbe00ed6c7ac4ea25a0c26f4034", "tree": "8a22bf2eb06d2a5e57c6d6272ac070d368467118", "parents": [ "72efc159bf4e5cde85cd28e78316681effdceb5b" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 11:54:57 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 12:00:42 2018 -0800" }, "message": "Minor cleanup of MIN/MAX code.\n\nRationale:\nShare the type dispatching code better.\n\nBug: b/65164101\n\nTest: test-art-host,target\nChange-Id: Ib06c915d570fd0a53f7734cdb316d2d16310db74\n" }, { "commit": "1f8d51bc03cbc607ae32fadf3a90f385adeffb95", "tree": "70e18902051ce47e0d524525b83709efbe6f250f", "parents": [ "7a02c66fd9ed174fc2e49ccc9f582dd661b7de9e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Feb 15 10:42:37 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 09:22:09 2018 -0800" }, "message": "Introduce MIN/MAX/ABS as HIR nodes.\n\nRationale:\nHaving explicit MIN/MAX/ABS operations (in contrast\nwith intrinsics) simplifies recognition and optimization\nof these common operations (e.g. constant folding, hoisting,\ndetection of saturation arithmetic). Furthermore, mapping\nconditionals, selectors, intrinsics, etc. (some still TBD)\nonto these operations generalizes the way they are optimized\ndownstream substantially.\n\nBug: b/65164101\n\nTest: test-art-host,target\n\nChange-Id: I69240683339356e5a012802f179298f0b04c6726\n" }, { "commit": "59eb30f96d87e3e72a060099a292ae14dd5fe1c8", "tree": "49f9334a44a28eef8d0c35c6061c61743d4db4a8", "parents": [ "5919f737facdebbe8b738272e681ae33e085de98" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 20 11:52:34 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 20 14:27:43 2018 +0000" }, "message": "ART: Clean up patching data in codegens.\n\nReuse PatchInfo\u003c\u003e for additional architectures and make the\nnaming more consistent across architectures. Change the\nDexFile reference to pointer in preparation for patching\nreferences to the upcoming .data.bimg.rel.ro section.\n\nUpdate obsolete comments; instead of referencing dex cache\narrays which were used in the past, reference the .bss and\nthe .data.bimg.rel.ro which shall be used in upcoming CLs.\n\nTest: Rely on TreeHugger.\nChange-Id: I03be4c4118918189e55c62105bb594500c6a42c1\n" }, { "commit": "bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb", "tree": "e281a8dde61e396ed5f20c31d41086b1b1b18389", "parents": [ "83af48e9f4cdfcf3f0069c63561bab4c176bd2f1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 25 13:33:07 2018 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 25 15:05:16 2018 +0000" }, "message": "Revert \"Compiler changes for bitstring based type checks.\"\n\nBug: 64692057\nBug: 71853552\nBug: 26687569\n\nThis reverts commit eb0ebed72432b3c6b8c7b38f8937d7ba736f4567.\n\nChange-Id: I7daeaa077960ba41b2ed42bc47f17501621be4be\n" }, { "commit": "eb0ebed72432b3c6b8c7b38f8937d7ba736f4567", "tree": "74d95eb4bfbf01ef6fd3a68695f5d7cec69338d7", "parents": [ "e57043081e6b091a9fd23a84043373148ae72f1f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 10 18:26:38 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 23 13:02:59 2018 +0000" }, "message": "Compiler changes for bitstring based type checks.\n\nWe guard the use of this feature with a compile-time flag,\nset to true in this CL.\n\nBoot image size for aosp_taimen-userdebug in AOSP master:\n - before:\n arm boot*.oat: 63604740\n arm64 boot*.oat: 74237864\n - after:\n arm boot*.oat: 63531172 (-72KiB, -0.1%)\n arm64 boot*.oat: 74135008 (-100KiB, -0.1%)\n\nThe new TypeCheckBenchmark yields the following changes\nusing the little cores of taimen fixed at 1.4016GHz:\n 32-bit 64-bit\n timeCheckCastLevel1ToLevel1 11.48-\u003e15.80 11.47-\u003e15.78\n timeCheckCastLevel2ToLevel1 15.08-\u003e15.79 15.08-\u003e15.79\n timeCheckCastLevel3ToLevel1 19.01-\u003e15.82 17.94-\u003e15.81\n timeCheckCastLevel9ToLevel1 42.55-\u003e15.79 42.63-\u003e15.81\n timeCheckCastLevel9ToLevel2 39.70-\u003e14.36 39.70-\u003e14.35\n timeInstanceOfLevel1ToLevel1 13.74-\u003e17.93 13.76-\u003e17.95\n timeInstanceOfLevel2ToLevel1 17.02-\u003e17.95 16.99-\u003e17.93\n timeInstanceOfLevel3ToLevel1 24.03-\u003e17.95 24.45-\u003e17.95\n timeInstanceOfLevel9ToLevel1 47.13-\u003e17.95 47.14-\u003e18.00\n timeInstanceOfLevel9ToLevel2 44.19-\u003e16.52 44.27-\u003e16.51\nThis suggests that the bitstring typecheck should not be\nused for exact type checks which would be equivalent to the\n\"Level1ToLevel1\" benchmark. Whether the implementation is\na beneficial replacement for the kClassHierarchyCheck and\nkAbstractClassCheck on average depends on how many levels\nfrom the target class (or Object for a negative result) is\na typical object\u0027s class.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --host -t 670-bitstring-type-check\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --target -t 670-bitstring-type-check\nBug: 64692057\nBug: 71853552\nBug: 26687569\nChange-Id: I538d7e036b5a8ae2cc3fe77662a5903d74854562\n" }, { "commit": "e7de5ec3e4cd1d607b647d98ea64df105479b867", "tree": "d692c4d1dee08eea4beffd71bd8cdf1d106c059e", "parents": [ "bee510c94560703102ca553a08ec47119959c204" ], "author": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Thu Dec 14 10:25:20 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Fri Dec 15 17:33:12 2017 +0100" }, "message": "MIPS: Support swaps between 128-bit locations\n\nAdd support for swaps between two SIMDStackSlots, two\nVectorRegisters (extended FpuRegister) and between a\nSIMDStackSlot and a VectorRegister.\n\nThis fixes test 623-checker-loop-regressions for\nMIPS64R6 and MIPS32R6.\n\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS64R6)\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS32R6)\n\nChange-Id: I36aa209f79790fb6c08b9a171f810769a6b40afc\n" }, { "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32", "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af", "parents": [ "e1e347dace0ded83774999bb26c37527dcdb1d5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 22:50:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 25 15:45:01 2017 +0100" }, "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n" }, { "commit": "d8dbc8da0e5cc6b5c2176ce2d3877e6194d72c0c", "tree": "af6e9fb02471d75ebdea46190a0aa3e9dbdb892d", "parents": [ "93780a60090356921b844dbefdc13442c9f18b52" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 13:37:47 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 15:55:10 2017 +0100" }, "message": "Refactor compiled_method.h .\n\nMove LinkerPatch to compiler/linker/linker_patch.h .\nMove SrcMapElem to compiler/debug/src_map_elem.h .\nIntroduce compiled_method-inl.h to reduce the number\nof `#include`s in compiled_method.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: Id211cdf94a63ad265bf4709f1a5e06dffbe30f64\n" }, { "commit": "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63", "tree": "f92b309ddc43c2254b6067346a653170fbbf7316", "parents": [ "0f3c7003e08a42a4ed8c9f8dfffb1bee1118de59" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 25 13:26:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 07 17:52:35 2017 +0100" }, "message": "Use mmapped boot image intern table for PIC app HLoadString.\n\nImplement new HLoadString load kind for boot image strings\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image InternTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image strings compared to the kBssEntry\nas we can completely avoid the slow path and stack map.\n\nWe separate the InternedStrings and ClassTable sections of\nthe boot image (.art) file from the rest, aligning the\nstart of the InternedStrings section to a page boundary.\nThis may actually increase the size of the boot image file\nby a page but it also allows mprotecting() these tables as\nread-only. The ClassTable section is included in\nanticipation of a similar load kind for HLoadClass.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20862776\n - after: 20308512 (-541KiB)\nNote that 92KiB savings could have been achieved by simply\navoiding the read barrier, similar to the HLoadClass flag\nIsInBootImage(). Such flag is now unnecessary.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I5f2bf1fc0bb36a8483244317cfdfa69e192ef6c5\n" }, { "commit": "2dec927e60395210946e5b9dbaa03111dad2466a", "tree": "2c983497c7dc23c02f08f6c302ee99a2cb992a9b", "parents": [ "4a9ab7d61f3933cbe26f01d7dc5bda1e65dcd567" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Aug 02 11:41:26 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Aug 03 07:34:07 2017 +0200" }, "message": "MIPS64: Implement HSelect\n\nTest: mma test-art-host-gtest\nTest: mma test-art-target-gtest in QEMU (MIPS64R6)\nTest: ./testrunner.py --target --optimizing in QEMU (MIPS64R6)\n\nChange-Id: I633fc479e0ca61b7d49b4c36fbe5db9a94da535d\n" }, { "commit": "4147fcc43c2ee019a06e55384985e3eaf82dcb8c", "tree": "11ec92efbfddf7736bbc74ed35fcfb3756bfcfb0", "parents": [ "e8f48da635c4d07bbe431e5819da8e1fad91a8ef" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Jun 17 19:57:27 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Jul 19 15:03:10 2017 -0700" }, "message": "MIPS: Reduce Baker read barrier code size overhead\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32 and MIPS64 in QEMU with poisoning\n in configurations:\n - with Baker read barrier thunks\n - without Baker read barrier thunks\n - ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2\n" }, { "commit": "ca8c2951ea25e8f93eea9decc70d81937b4361dd", "tree": "72c811abe58895b4972cd88ee267c8ca66155fd1", "parents": [ "2e0a7e5047fde08ddd220aaa1a0e64d44ecbb420" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Mon May 29 11:31:46 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 06 14:06:33 2017 +0200" }, "message": "MIPS32: Saves 128-bit vector registers along SuspendCheckSlowPath\n\nWe need to save 128 bits of data. This is only done for vector\nregisters that are live, so overhead is not too big.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS)\nChange-Id: I0f792e9c98011be3e24d5fad35a8244faafcb9a0\n" }, { "commit": "5fa5c04ca39fb9c46bfef0e0807a18d0cd9a4ba7", "tree": "f902c5dad2486b8372c31989ac9b917715231fa8", "parents": [ "83b140474aa1759739c8ee4464bf226c4fa0f6d7" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Jun 01 21:07:52 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Jun 08 14:39:57 2017 -0700" }, "message": "MIPS: Shorten .bss string/class loads\n\nThis is a follow-up to\nhttps://android-review.googlesource.com/#/c/384033/.\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 and MIPS64 in QEMU in configurations:\n ART_USE_READ_BARRIER\u003dfalse,\n ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I4cb2f4ded13c0d9fc960c7eac55396f7931c1e38\n" }, { "commit": "0eb882bfc5d260e8014c26adfda11602065aa5d8", "tree": "e66dbebfb1e9a254c20954a2f2f98541aebfd5af", "parents": [ "b5f5d746ac3f2c3088292395603cb1470e7749d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 15 13:39:18 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 15:39:24 2017 +0100" }, "message": "Use ArtMethod* .bss entries for HInvokeStaticOrDirect.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug.\nBug: 30627598\nChange-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f\n" }, { "commit": "3c8a91250b3e4e87548ec16bf1ab1ea46dbb84a4", "tree": "b5da100b358d1335eab403372e4f616c5c2d607c", "parents": [ "0a87f31513e5f9da27856af054d2241452898b22", "e7197bf7d58c705a048e13e241d7ca320502cd40" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 10:38:10 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 07 10:38:11 2017 +0000" }, "message": "Merge \"Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\"" }, { "commit": "e7197bf7d58c705a048e13e241d7ca320502cd40", "tree": "496032b40145660b40002b9d5b7a78f1c2eeb44f", "parents": [ "4ee8e291a7d5b7b98f35f495eb97705836910871" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 17:00:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 06 15:26:42 2017 +0100" }, "message": "Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\n\nIn preparation for replacing the dex cache method array\nwith a hash-based array, get rid of one unnecessary use.\nThis method load kind is currently used only on mips for\nirreducible loops and OSR, so this should have no impact\non x86/x86-64/arm/arm64.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Repeat the above tests with manually changing\n kDexCachePcRelative to kRuntimeCall in sharpening.cc.\n (Ignore failures in 552-checker-sharpening.)\nBug: 30627598\nChange-Id: Ifce42645f2dcc350bbb88c2f4642e88fc5f98152\n" }, { "commit": "19680d3655433e98582983ed0a6d44d6b4822951", "tree": "15113506e75b1480c5c1d3cfdf9df4480f30eae8", "parents": [ "0a5ace58e973da278049f837bf2cdbaf7b44849c" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu May 11 10:38:36 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon May 29 17:57:39 2017 +0200" }, "message": "MIPS64: ART Vectorizer\n\nMIPS64 implementation which uses MSA extension. Also extended all\nrelevant checker tests to test MIPS64 implementation.\n\nTest: booted MIPS64R6 in QEMU\nTest: ./testrunner.py --target --optimizing -j1 in QEMU\n\nChange-Id: I8b8a2f601076bca1925e21213db8ed1d41d79b52\n" }, { "commit": "dbddc22f5dc2d1ff4d4783fbd66c27812f4980d1", "tree": "2a0a8efa1c2630e57ab48ab2de171f2847ff282f", "parents": [ "a559fa1b0d6c276dde2cdc707de1acd4950f7190" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed May 24 12:04:13 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu May 25 16:59:44 2017 -0700" }, "message": "Refactor profiles to use TypeReference instead of ClassReference\n\nRefactor type reference into runtime and use it for profiles.\nClassReference was just duplicated code since it wasn\u0027t even using\nthe class def indexes.\n\nTest: test-art-host\n\nBug: 62040831\nChange-Id: Ia92f21c0e85c00321f52c97bb7a90158d882849b\n" }, { "commit": "6597946d29be9108e2cc51223553d3db9290a3d9", "tree": "cea6647a45cc59fa1423751179e647124f269990", "parents": [ "a654e0378a8d0bb149362399917e4da2959e6991" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 19 17:25:12 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 22 18:35:05 2017 +0100" }, "message": "Use PC-relative pointer to boot image methods.\n\nIn preparation for adding ArtMethod entries to the .bss\nsection, add direct PC-relative pointers to methods so that\nthe number of needed .bss entries for boot image is small.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target on Nexus 6P\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug\nBug: 30627598\nChange-Id: Ia89f5f9975b741ddac2816e1570077ba4b4c020f\n" }, { "commit": "764d454d1d51448deb81f6e8d2d7d317c7f4d1b4", "tree": "029f9e65cfe7e953df55b7af45e099924ffdbbac", "parents": [ "7974468d32b817be1d49dfcf513605f646c481bc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 10:31:41 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 15:08:55 2017 +0100" }, "message": "Remove LoadString/Class kind kBootImageLinkTimeAddress.\n\nWe no longer support non-PIC boot image compilation.\n\nAlso clean up some obsolete code for method patches\nand make JIT correctly report itself as non-PIC.\n\nTest: testrunner.py --host\nTest: testrunner.py --target\nBug: 33192586\nChange-Id: I593289c5c1b0e88b82b86a933038be97bbb15ad2\n" }, { "commit": "d8b6a53074be7d6b98c651ed8d2127f089da39a6", "tree": "f0780307647818a97f041e62d31cc27fa4cc971a", "parents": [ "81c50bf31d9f9e35890404a2baf93f2c1e061ad9" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 20 11:42:30 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon May 08 13:05:20 2017 +0200" }, "message": "MIPS64: Saves 128-bit vector registers along SuspendCheckSlowPath\n\nWe need to save 128 bits of data. This is only done for vector\nregisters that are live, so overhead is not too big.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS64)\n\nChange-Id: I2cdfeb8056dc5ef35c92f589d8c0399c41d913b2\n" }, { "commit": "5633ce718b9544af1c7b1a811ed2872889019c84", "tree": "2ffc0f10ba7f2b9f19403187f3eaee37f17b811c", "parents": [ "a57c334075b193de9690fff97acf6c1b1d1283fc" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Apr 10 15:47:40 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Sun Apr 30 08:29:49 2017 -0700" }, "message": "MIPS: java.lang.Integer.valueOf intrinsic.\n\nTest: run-test --64 --optimizing 640-checker-integer-valueof\nTest: run-test --64 640-checker-integer-valueof\nTest: run-test --64 --no-prebuild --optimizing 640-checker-integer-valueof\nTest: run-test --64 --no-prebuild 640-checker-integer-valueof\nTest: run-test --optimizing 640-checker-integer-valueof\nTest: run-test 640-checker-integer-valueof\nTest: run-test --no-prebuild --optimizing 640-checker-integer-valueof\nTest: run-test --no-prebuild 640-checker-integer-valueof\nTest: mma test-art-host\nTest: mma test-art-target\n\nBooted on both MIPS32 and MIPS64 emulators.\n\nChange-Id: I5b2f21cf2334c392080cff9654150504207f4c01\n" }, { "commit": "1595815c2a914a78df7dfb6f0082f47d4e82bb36", "tree": "8fd53c3c91158b33e744e43cc655b2e2a180a3fc", "parents": [ "4ba18fdfc2581a2328ab745c2707e3ed375d9e64" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Feb 09 19:08:30 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Mar 28 23:35:34 2017 -0700" }, "message": "MIPS: Implement read barriers.\n\nThis is the core functionality. Further improvements\nwill be done separately.\n\nThis also adds/moves memory barriers where they belong and\nremoves the UnsafeGetLongVolatile and UnsafePutLongVolatile\nMIPS32 intrinsics as they need to load/store a pair of\nregisters atomically, which is not supported directly by\nthe CPU.\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"testrunner.py --target --optimizing -j1\"\nTest: same MIPS64 boot/test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\nTest: \"testrunner.py --target --optimizing --32 -j2\" on CI20\nTest: same CI20 test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I0ff91525fefba3ec1cc019f50316478a888acced\n" }, { "commit": "ba89c34e94a82f0a6904dcc62caa6aa7bb14c12c", "tree": "a10992eabb2aade0c97e283038873a6c36d05132", "parents": [ "224f6ab7620ddbc20a338e56ccf9952d86b08b51" ], "author": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Fri Mar 10 13:36:08 2017 +0100" }, "committer": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Tue Mar 14 07:40:59 2017 +0100" }, "message": "MIPS64: Improve storing of constants in fields and array elements\n\nTest: booted MIPS64 in QEMU\nTest: mma test-art-target-run-test\nTest: mma test-art-host-gtest-assembler_mips64_test\n\nChange-Id: I8e0002166174eebea1309358eb9d96f34eee3225\n" }, { "commit": "c52f3034b06c03632e937aff07d46c2bdcadfef5", "tree": "031e4d1b2ca0961014e57e4987d80d7aa2c435b0", "parents": [ "ef81e988d0eb4db390e576aac346701b2d820916" ], "author": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Thu Mar 02 13:45:45 2017 +0000" }, "committer": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Wed Mar 08 10:55:17 2017 +0000" }, "message": "Remove --include-patch-information option from dex2oat.\n\nBecause we no longer support running patchoat on npic oat files, which\nmeans the included patch information is unused .\n\nBug: 33192586\nTest: m test-art-host\n\nChange-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67\n" }, { "commit": "627c1a0e573b4512e68f097771d7fdd4d8c7f7de", "tree": "5e9590d470e32e205f862d694cebd95da5cf0a97", "parents": [ "318797a758f81e7f8a0b440129238b9b5eb1b74e" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jan 30 19:28:14 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Feb 01 15:29:43 2017 -0800" }, "message": "MIPS: Support kJitTableAddress kinds of string/class loads.\n\nAlso remove a few stale comments.\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dfalse\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dtrue\n test-art-target-run-test\"\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I8914b8e6594e030f8137e7fface1ae20b6d6b971\n" }, { "commit": "0cb124219e986a27c40001a1b22ea7ebd833a2d8", "tree": "87c335705a0386710553ce5bc6cca4119c017ebd", "parents": [ "e38436063fb4baf88152344b465eeeb1b7f6dce5" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Jan 25 19:30:18 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Jan 27 13:37:56 2017 -0800" }, "message": "MIPS: Refactor code for unresolved field entrypoint.\n\nThis is a follow-up to\nhttps://android-review.googlesource.com/#/c/325423/.\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test-optimizing in QEMU\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing\n (MIPS64R6 and MIPS32R6) in QEMU\n\nChange-Id: Ie663ecf0489e7b182434708bef71686df5f37273\n" }, { "commit": "1998cd02603197f2acdc0734397a6d48b2f59b80", "tree": "aa639c7ec96f71d7aaf5d0c865a8a133dbc457c3", "parents": [ "6bec91c7d4670905cd67440991ec76fd54d0f000" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 13 13:02:58 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 13:39:24 2017 +0000" }, "message": "Implement HLoadClass/kBssEntry for boot image.\n\nTest: m test-art-host\nTest: m test-art-host with CC\nTest: m test-art-target on Nexus 9\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng\nBug: 30627598\nChange-Id: I168f24dedd5fb54a1e4215ecafb947ffb0dc3280\n" }, { "commit": "6bec91c7d4670905cd67440991ec76fd54d0f000", "tree": "05f4ba288e629270773c65b34b71be7bae5e92ff", "parents": [ "4155998a2f5c7a252a6611e3926943e931ea280a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 09 15:03:12 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Store resolved types for AOT code in .bss.\n\nTest: m test-art-host\nTest: m test-art-target on Nexus 9.\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng.\nBug: 30627598\nBug: 34193123\nChange-Id: I8ec60a98eb488cb46ae3ea56341f5709dad4f623\n" }, { "commit": "f67dadb5550ee2bd9db0b7b0b75d8c44ddf170d2", "tree": "44f61f9bd0a674cae29c42e6dff72d4ff14189d0", "parents": [ "cda4b75615f5f11c101ff846a05affda405b101b", "0960ac5a5a255bb3e8418e185914243aeef54a7c" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jan 05 17:37:56 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 05 17:37:57 2017 +0000" }, "message": "Merge \"MIPS64: Implement table-based packed switch\"" }, { "commit": "e2157fb29e02561bc3197ab49e6c1d9dfe801b81", "tree": "13c473634beee0557095486a7079e5e86488af9d", "parents": [ "0ec9ac0a5f70cbbd8964d817d7d6234a91b6990c", "4375819125bce2132cde663ba5024e33d7bd2681" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 04 10:04:08 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 04 10:04:09 2017 +0000" }, "message": "Merge \"MIPS64: Implement branchless HCondition for floats\"" }, { "commit": "595375fc44770bf3837e79cc49a0336bfd346377", "tree": "1866e6a18f71917b243610d1e662b050ff893fbf", "parents": [ "00797355fa88299db5b4ac941bbda17cd97ab39e", "c378980e32f0ec9ab7f1d0b87e1d5b97c1f3972c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 03 20:43:00 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 03 20:43:01 2017 +0000" }, "message": "Merge \"MIPS64: Align register spills on 8-byte boundaries in slow paths\"" }, { "commit": "4375819125bce2132cde663ba5024e33d7bd2681", "tree": "3457bce20da8c048d988c16e92ad54d4d09c50d1", "parents": [ "6a14c622700e088173ba909799c1e1785aeb4b34" ], "author": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Fri Dec 30 09:23:01 2016 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Dec 30 09:53:12 2016 +0100" }, "message": "MIPS64: Implement branchless HCondition for floats\n\nTest: mma test-art-target-run-test64 in QEMU\n\nChange-Id: I595b5b7ddf9ebb19e872ed85f2e4098a835d9214\n" }, { "commit": "c378980e32f0ec9ab7f1d0b87e1d5b97c1f3972c", "tree": "11023f47469b9042091197ea3d2b5fb6e32cfb9e", "parents": [ "07001c8540718117b91e8137804fa94d35cbb37a" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Dec 22 13:54:23 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Dec 22 16:42:01 2016 -0800" }, "message": "MIPS64: Align register spills on 8-byte boundaries in slow paths\n\n64-bit loads/stores would otherwise be split into pairs of\n32-bit ones.\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS64R6) in QEMU\n\nChange-Id: I4846d11b52b71507dfd5ca2e27b3f2a5befcc58e\n" }, { "commit": "0960ac5a5a255bb3e8418e185914243aeef54a7c", "tree": "7163af0759328285dce0e3a5af13bd5b0cc042c0", "parents": [ "07001c8540718117b91e8137804fa94d35cbb37a" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 20 17:24:59 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Dec 21 16:01:49 2016 -0800" }, "message": "MIPS64: Implement table-based packed switch\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS64R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: I333dca43fca57ae7e6021bb84585487c889417c3\n" }, { "commit": "c1a42cf3873be202c8c0ca3c4e67500b470ab075", "tree": "f2bffbd14e1f9d5429dd8514d19be4fa6dfa392f", "parents": [ "06ce6d4359ed897f1d1b39be4e748f0c4f3ca2ff" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Dec 18 15:52:36 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 20 13:29:45 2016 +0000" }, "message": "Remove soon to be obsolete call kinds for direct calls.\n\nAnd remove CompilerDriver::GetCodeAndMethodForDirectCall in\npreparation of removing non-PIC prebuild and non-PIC on-device\nboot image compilation.\n\nTest: test-art-host test-art-target\nbug:33192586\nChange-Id: Ic48e3e8b9d7605dd0e66f31d458a182198ba9578\n" }, { "commit": "f63f569eeefe3907c48a175494a2a0ba351b641a", "tree": "c2ba1621cbcd77571378b8261ec6d47c754953aa", "parents": [ "2c43590dc2bb7fb4a3a015b1b65543bb8705ffe8" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 13 17:43:11 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Dec 19 14:47:16 2016 -0800" }, "message": "MIPS64: Improve string and class loads.\n\nThis adds most kinds of string/class loads.\nJIT string/class loads are TBD separately.\n\nThis also fixes Mips64Assembler::LoadLabelAddress()\n(adding a constant to a 64-bit address must be done\nusing daddiu, not addiu).\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test64\"\n\nChange-Id: I1f94ece4cd202382c11167e1ed958e9d08d92822\n" }, { "commit": "19f6c696bbb7a17d8ac521b316c40f9cbef32151", "tree": "6ce87f3ba9f224efc0036d3ab99e4272c48eeddb", "parents": [ "aea9ffece7eb32f3884a4ad0553e1df4d90fd9e4" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 30 19:19:55 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 13 14:07:16 2016 -0800" }, "message": "MIPS64: Improve method invocation.\n\nImprovements include:\n- support for all kinds of method loads and static/direct calls\n- 32-bit and 64-bit literals for the above and future work\n- shorter instruction sequences for recursive static/direct calls\nAlso:\n- include the MIPS64 dinsu instruction (missed earlier) and minor\n clean-up in the disassembler\n- properly prefix constant names with \u0027k\u0027 in relative patcher tests\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test64\"\n\nChange-Id: I19876fa5316b68531af7dfddfce90d2068433116\n" }, { "commit": "5e4e11e171f90d9a3ea178fc8e72aac909de55d5", "tree": "53314d1139ac797d55258f39097ecfb5cef45920", "parents": [ "ca8bad9136d1389deeebc8652fb17063388de6b2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 22 13:17:41 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Sep 23 09:08:00 2016 +0100" }, "message": "Clean-up sharpening and compiler driver.\n\nRemove dependency on compiler driver for sharpening\nand dex2dex (the methods called on the compiler driver were\ndoing unnecessary work), and remove the now unused methods\nin compiler driver.\n\nAlso remove test that is now invalid, as sharpening always\nsucceeds.\n\ntest: m test-art-host m test-art-target\nChange-Id: I54e91c6839bd5b0b86182f2f43ba5d2c112ef908\n" }, { "commit": "f41f956558ceb5402d3b4499a44a15c42f1c0064", "tree": "50afd6f7509adca0c8ed8cbdc04398058b687b81", "parents": [ "8850c73572215669efc893763791f7ec7f0b0667" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Sep 14 19:26:48 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Sep 14 19:26:48 2016 +0100" }, "message": "Add missing OVERRIDE qualifiers in code generators.\n\nTest: mmma art\nChange-Id: I91d0a2dc23dc8d63a9bb3607eb1c1517eabaeb1f\n" }, { "commit": "fc734088e6656a918b6c75094eb942a22bd799e8", "tree": "c31e8677df68e72fdc40aef798d09bd485f736b5", "parents": [ "fca16663334e5838790631d8eac95f4ffdb0cc2e" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Tue Jul 19 17:18:07 2016 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Aug 31 17:22:59 2016 +0100" }, "message": "Extend the InvokeRuntime() changes to mips64.\n\nChange-Id: I3f825746053b9288ca31ab5e823d6a1648dfd894\n" }, { "commit": "26de38bb7f2122417388809f4ff88a7cb5c4af5e", "tree": "878f432e2476f90201dd4695cfc8c3498c2c207f", "parents": [ "9755c262df1be7f5d5b98d038c8fd3734e974f9d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 17:53:11 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 17:56:08 2016 -0700" }, "message": "ART: Delete old compiler_enums.h\n\nHoldover from the Quick days. Move the two enums that are still\nused closer to the actual users (and prune no longer used cases).\n\nTest: m test-art-host\nChange-Id: I88aa49961a54635788cafac570ddc3125aa38262\n" }, { "commit": "dbb7f5bef10138ade0fb202da1d61f562b2df649", "tree": "f0aa4b390c534b215a6e000c865783cdd9852353", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 30 13:23:58 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 15:11:57 2016 +0100" }, "message": "Improve HLoadClass code generation.\n\nFor classes in the boot image, use either direct pointers\nor PC-relative addresses. For other classes, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe type\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -252KiB (-0.3%)\n - 64-bit boot.oat: -412KiB (-0.4%)\n - 32-bit dalvik cache total: -392KiB (-0.4%)\n - 64-bit dalvik-cache total: -2312KiB (-1.0%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -124KiB (-0.2%)\n - 64-bit boot.oat: -420KiB (-0.5%)\n - 32-bit dalvik cache total: -136KiB (-0.1%)\n - 64-bit dalvik-cache total: -1136KiB (-0.5%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 27950288\nChange-Id: I4da991a4b7e53c63c92558b97923d18092acf139\n" }, { "commit": "c01a66465a398ad15da90ab2bdc35b7f4a609b17", "tree": "e85cb2aa05be5c1491814fa83b94748439b8394b", "parents": [ "dad35b0762f97ce79ce3b9a35c9df5021b7dbd17" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "message": "Fix: correctly destruct VIXL labels.\n\nBug: 27505766\nChange-Id: I077465e3d308f4331e7a861902e05865f9d99835" }, { "commit": "dee58d6bb6d567fcd0c4f39d8d690c3acaf0e432", "tree": "5a2f20546ca3c1544c44bee560062580e22dc79c", "parents": [ "391e155a6936a05bd39b171031ec21d2dee62133" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 09:54:26 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 16:03:16 2016 +0000" }, "message": "Revert \"Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\"\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nThis CL fixed an issue with parsing quickened instructions.\n\nBug: 27894376\nBug: 27998571\nBug: 27995065\n\nChange-Id: I20dbe1bf2d0fe296377478db98cb86cba695e694\n" }, { "commit": "60328910cad396589474f8513391ba733d19390b", "tree": "01702f6df5c39925b354a3152dd04289e7d97062", "parents": [ "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "message": "Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\n\nBug: 27995065\nThis reverts commit e3ff7b293be2a6791fe9d135d660c0cffe4bd73f.\n\nChange-Id: I5363c7ce18f47fd422c15eed5423a345a57249d8\n" }, { "commit": "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f", "tree": "d578d27cb78e6d2caef683cd8ac94c9a9752b192", "parents": [ "86ea7eeabe30c98bbe1651a51d03cb89776724e7" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 02 16:48:20 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 11:21:30 2016 +0100" }, "message": "Refactor HGraphBuilder and SsaBuilder to remove HLocals\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nBug: 27894376\nChange-Id: Iefe28d40600c169c5d306fd2c77034ae19476d90\n" }, { "commit": "cac5a7e871f1f346b317894359ad06fa7bd67fba", "tree": "2df7d4892216a7c976dfe848c9893cb5eb8fa6a5", "parents": [ "6f51d7756a9c66007fe7666b19399e1f60ff6092" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 22 10:39:50 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 29 19:27:40 2016 +0100" }, "message": "Optimizing: Improve const-string code generation.\n\nFor strings in the boot image, use either direct pointers\nor pc-relative addresses. For other strings, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe string\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -692KiB (-0.9%)\n - 64-bit boot.oat: -948KiB (-1.1%)\n - 32-bit dalvik cache total: -900KiB (-0.9%)\n - 64-bit dalvik cache total: -3672KiB (-1.5%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -380KiB (-0.5%)\n - 64-bit boot.oat: -928KiB (-1.0%)\n - 32-bit dalvik cache total: -468KiB (-0.4%)\n - 64-bit dalvik cache total: -1928KiB (-0.8%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 26884697\nChange-Id: Iec7266ce67e6fedc107be78fab2e742a8dab2696\n" }, { "commit": "2ae48182573da7087bffc2873730bc758ec29696", "tree": "d6955329ad876aefd477f7ef8905b070b9ab95dd", "parents": [ "6915898b28cea6c9836ca1be6814d87e89cc6d76" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:05:09 2016 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:10:27 2016 +0000" }, "message": "Clean up NullCheck generation and record stats about it.\n\nThis removes redundant code from the generators and allows for easier\nstat recording.\n\nChange-Id: Iccd4368f9e9d87a6fecb863dee4e2145c97851c4\n" }, { "commit": "9cd6d378bd573cdc14d049d32bdd22a97fa4d84a", "tree": "be293c89806b919143b7dcd203bae14f5f4eaf04", "parents": [ "0e02ee9efbf1dbdde05d2b10f7307bbe191c52f5" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 15:24:47 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:25:29 2016 +0000" }, "message": "Associate slow paths with the instruction that they belong to.\n\nAlmost all slow paths already know the instruction they belong to,\nthis CL just moves the knowledge to the base class as well.\n\nThis is needed to be be able to get the corresponding dex pc for\nslow path, which allows us generate better native line numbers,\nwhich in turn fixes some native debugging stepping issues.\n\nChange-Id: I568dbe78a7cea6a43a4a71a014b3ad135782c270\n" }, { "commit": "0e02ee9efbf1dbdde05d2b10f7307bbe191c52f5", "tree": "19c9c3e25a8db4e5b53890fd72193383b5bb73e5", "parents": [ "72ca09cc2dd350adb932ef4a50eff668cca99c5e", "c7098ff991bb4e00a800d315d1c36f52a9cb0149" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:23:50 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Feb 24 10:23:50 2016 +0000" }, "message": "Merge \"Remove HNativeDebugInfo from start of basic blocks.\"" }, { "commit": "c7098ff991bb4e00a800d315d1c36f52a9cb0149", "tree": "3a150e927bc7f4894f5b148ec6f5a2b796cdd80d", "parents": [ "5322e55ab9a15996a197456ca39d9c77488cd5c1" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 14:30:11 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:21:57 2016 +0000" }, "message": "Remove HNativeDebugInfo from start of basic blocks.\n\nWe do not require full environment at the start of basic block.\nThe dex pc contained in basic block is sufficient for line mapping.\n\nChange-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa\n" }, { "commit": "936d5dc60fa3f4dadf3654db04d2b361dc0b745c", "tree": "660fcf62dab8f09de9c19568783ac6e2a0ac00f8", "parents": [ "39e4fab868a6052e0fab75e2668600b0e26daa42", "3acee732f9475fbfc6b046e0044b764e7ff5ac01" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Feb 17 14:47:03 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Feb 17 14:47:03 2016 +0000" }, "message": "Merge \"MIPS32: peek*/poke*, and String.charAt intrinsics.\"" }, { "commit": "6e332529c33be4d7dae5dad3609a839f4c0d3bfc", "tree": "cedd2e1beb170fd5821136fe974e3f34adfcddc2", "parents": [ "d3caabd4f85f86dd744da432993e12935d843a83" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Feb 02 16:15:27 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Feb 12 15:17:50 2016 +0000" }, "message": "ART: Remove HTemporary\n\nChange-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03\n" }, { "commit": "3acee732f9475fbfc6b046e0044b764e7ff5ac01", "tree": "3b87f8b93c427c05e7690ea8d14577ce3e9eb502", "parents": [ "34937e2ed46fa9f56d99e9f32e0bfad050e5e798" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 18 13:31:08 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Feb 10 16:12:56 2016 -0800" }, "message": "MIPS32: peek*/poke*, and String.charAt intrinsics.\n\n- byte libcore.io.Memory.peekByte(long address)\n- short libcore.io.Memory.peekShort(long address)\n- int libcore.io.Memory.peekInt(long address)\n- long libcore.io.Memory.peekLong(long address)\n- void libcore.io.Memory.pokeByte(long address, byte value)\n- void libcore.io.Memory.pokeShort(long address, short value)\n- void libcore.io.Memory.pokeInt(long address, int value)\n- void libcore.io.Memory.pokeLong(long address, long value)\n- char java.lang.String.charAt(int index)\n\nChange-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa\n" }, { "commit": "d967266cdfc8011c81ba6e9857a247c4a73bd0fc", "tree": "7bf469b0656c4819921799d814b2ca7a4f1705be", "parents": [ "ba5ea7003f071f85936ee351aff46f64a56ee096" ], "author": { "name": "Lazar Trsic", "email": "Lazar.Trsic@imgtec.com", "time": "Thu Sep 03 17:33:01 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 29 17:38:06 2016 +0100" }, "message": "MIPS64: Remove unaligned memory access from art generated code\n\nUnaligned memory access was caused by sd, ld, ldc1 and sdc1\ninstructions. Check if offset is unaligned and replace it\nwith two 32 bit memory accesses, if so.\n\nAdded assembler tests for new instructions, as well as assembler\ntests for LoadFromOffset, LoadFpuFromOffset, StoreToOffset and\nStoreFpuToOffset.\n\nChange-Id: I0228a4a2ce6c801eeb5b46952b8330e14468deb3\n" }, { "commit": "8ed1826a9da054920f2d39d34dfc7ba43337e4c9", "tree": "21f64788a548fa0f4f39417cf50c74c6df0b9c6f", "parents": [ "a7d507eb0fc55240700232a0b6269d1388e9b5a5" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 22 13:01:00 2016 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 22 15:20:21 2016 +0100" }, "message": "Fix MIPS64 booting problem\n\nAdd missing MarkGCCard in compareAndSwapObject intinsic.\n\nAdditionaly, don\u0027t do a null test in MarkGCCard if the value\ncannot be null for MIPS64.\n\nChange-Id: Iad50f9e6be8cd27fedb31abb00d5829498941696\n" }, { "commit": "58282f4510961317b8d5a364a6f740a78926716f", "tree": "5d97c0db9fe01dd6e8df2357ef11f614abb853e8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 12:45:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 16:39:30 2016 +0000" }, "message": "ART: Remove Baseline compiler\n\nWe don\u0027t need Baseline any more and it hasn\u0027t been maintained for\na while anyway. Let\u0027s remove it.\n\nChange-Id: I442ed26855527be2df3c79935403a25b1ee55df6\n" }, { "commit": "42249c3602c3d0243396ee3627ffb5906aa77c1e", "tree": "1e822a21c87331246cbde3923eac88fa315fa2cc", "parents": [ "922698ded1e80cad1ecce4c2172a88c76a216373" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 07 15:33:50 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 12 16:39:20 2016 -0800" }, "message": "Reduce code size by sharing slow paths.\n\nRationale:\nSharing identical slow path code reduces code size.\n\nBackground:\nCurrently, slow paths with the same dex-pc, same physical register\nspilling code, and identical stack maps are shared (making this\nonly useful for deopt slow paths). The newly introduced mechanism\nis sufficiently general to allow future improvements by e.g.\nallowing different dex-pc (by passing this to runtime) or even\nthe kind of slow paths (by passing runtime addresses to the slowpath).\n\nChange-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0\n" }, { "commit": "5f7b58ea1adfc0639dd605b65f59198d3763f801", "tree": "04556e673cdd3967cc967ff79931eab49e523956", "parents": [ "1201804d1813d7db0accead9721d67c40b3de564" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 23 19:49:34 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 23 09:59:07 2015 +0000" }, "message": "Rewrite HInstruction::Is/As\u003ctype\u003e().\n\nMake Is\u003ctype\u003e() and As\u003ctype\u003e() non-virtual for concrete\ninstruction types, relying on GetKind(), and mark GetKind()\nas PURE to improve optimization opportunities. This reduces\nthe number of relocations in libart-compiler.so\u0027s .rel.dyn\nsection by ~4K, or ~44%, and in .data.rel.ro by ~18K, or\n~65%. The file is 96KiB smaller for Nexus 5, including 8KiB\nreduction of the .text section.\n\nUnfortunately, the g++/clang++ __attribute__((pure)) is not\nstrong enough to avoid duplicated virtual calls and we would\nneed the C++ [[pure]] attribute proposed in n3744 instead.\nTo work around this deficiency, we introduce an extra\nnon-virtual indirection for GetKind(), so that the compiler\ncan optimize common expressions such as\n instruction-\u003eIsAdd() || instruction-\u003eIsSub()\nor\n instruction-\u003eIsAdd() \u0026\u0026 instruction-\u003eAsAdd()-\u003e...\nwhich contain two virtual calls to GetKind() after inlining.\n\nChange-Id: I83787de0671a5cb9f5b0a5f4a536cef239d5b401\n" }, { "commit": "299a93993fb8f3efbf0465cf674d80c3bcfdc66c", "tree": "1ba8d1cd2a34091317af08cbbe5cfa3fa52e549f", "parents": [ "fae1db92d8433d0f75258c190bcf2c940731f036" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 08 16:08:02 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Dec 17 14:14:26 2015 -0800" }, "message": "MIPS64: Fuse long and FP compare \u0026 condition in Optimizing.\n\nBug: 25559148\n\nChange-Id: I2d14ac75460a76848c71c08cffff6d7a18f5f580\n" }, { "commit": "a0e87b0a97fadd54540ec7e8331b61bebd82d378", "tree": "c1027e65fd859cf59f295ff3a5630404e3724db3", "parents": [ "d83b9042d67f2a7d5ca5a1f63819c97940033336" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Sep 24 22:57:20 2015 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Nov 21 22:18:50 2015 -0800" }, "message": "MIPS64: Support short and long branches\n\nChange-Id: I618c960bd211048166d9fde78d4106bd3ca42b3a\n" }, { "commit": "0debae7bc89eb05f7a2bf7dccd223318fad7c88d", "tree": "3da9656dc77d271b12c1b02793e7d713ae3da790", "parents": [ "991842a5273d20695dd5f35eb9a9e28c386c5b4b" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Nov 12 18:37:00 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Nov 17 15:12:00 2015 +0000" }, "message": "ART: Refactor GenerateTestAndBranch\n\nEach code generator implements a method for generating condition\nevaluation and branching to arbitrary labels. This patch refactors\nit for better clarity but also to generate fewer jumps when the true\nbranch is the fallthrough successor.\n\nThis is preliminary work for implementing HSelect.\n\nChange-Id: Iaa545a5ecbacb761c5aa241fa69140cf6eb5952f\n" }, { "commit": "00580bdbbb119a354c94a9c19928c1dcbd14a8f4", "tree": "722017e414952bccc6933a63e28b4ed5a214f1ff", "parents": [ "c4b24109473d50e4cc829be5d1e7c77fd21527f3" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 11 13:31:12 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 11 16:06:29 2015 -0800" }, "message": "MIPS64: fix calling conventions in LoadClass and field accesses\n\nThis fixes failures in test 529-checker-unresolved\n\nChange-Id: I6170c22059e9711b2fcc965b00d6e34edd839539\n" }, { "commit": "c857c746707dfd45d74b75cb7fa84484ca68cc2a", "tree": "0c223c9cb4999ffe9b04b3e264f5fea4c91d949a", "parents": [ "b203aad7a0db904efa8429d48b53e56583f61ec2" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Sep 23 15:12:39 2015 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Nov 06 13:03:43 2015 -0800" }, "message": "MIPS64: Improve integer division by constants\n\nThis also removes some unused instructions and instructions not\navailable on MIPS64R6.\n\nChange-Id: I44bfe12c60344312c88c45e97b6b07dcd5bdc630\n" }, { "commit": "53afca191ace3d7447b09097f9ea82a513075c52", "tree": "f037ef8007bcbe4632b5d06fab0a7aea5550ce61", "parents": [ "a930832a4ef0a2ef0835c5db4650750018ab0765" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Nov 05 16:34:23 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Nov 05 16:53:19 2015 -0800" }, "message": "MIPS64: Implement virtual intrinsic slow path\n\nThis fixes a crash in dex2oat while compiling boot.oat.\n\nChange-Id: I44fc92809902d7fc226c88b3e3f081b72cc19ce5\n" }, { "commit": "dc151b2346bb8a4fdeed0c06e54c2fca21d59b5d", "tree": "391d8ccb44ff9e6fc1c8fa8975e534e20cc002ff", "parents": [ "823e693aa946ba75cd047429e1290011a2ed8729" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 15 18:02:30 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 23 14:45:32 2015 +0100" }, "message": "Optimizing: Determine invoke-static/-direct dispatch early.\n\nDetermine the dispatch type of invoke-static/-direct in a\nspecial pass right after the type inference. This allows the\ninliner to pass the \"needs dex cache\" check and inline more.\nIt also allows the code generator to avoid requesting a\nregister location for the ArtMethod* for kDexCachePcRelative\nand direct methods.\n\nThe supported dispatch check handles also situations that\nthe CompilerDriver currently doesn\u0027t allow. The cleanup of\nthe CompilerDriver and required changes to Quick will come\nin a separate change.\n\nChange-Id: I3f8e903a119949e95871d8ab0a995f4731a13a07\n" }, { "commit": "f652cecb984c104d44a0223c3c98400ef8ed8ce2", "tree": "ec0cc193eccdd11a79f42f957a856d2ba57699e1", "parents": [ "b8b44983f861cfeeca66c624dd0f2a3fa71b4992" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Aug 25 16:11:42 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Oct 22 18:51:13 2015 +0200" }, "message": "MIPS: Initial version of optimizing compiler for MIPS32\n\nChange-Id: I370388e8d5de52c7001552b513877ef5833aa621\n" }, { "commit": "8c34ec1ede2608eb99a7e26253b6253931dcb7ab", "tree": "ac29638fad252e02b1cc98817b723482bf0d7ad8", "parents": [ "f992a6394b7a00b518971fa2390bc6532f0a5623" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Oct 14 11:23:48 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Oct 14 11:27:49 2015 +0200" }, "message": "Fix MIPS64 boot\n\nReturn register in FieldAccessCallingConventionMIPS64 was A0,\nbut it should be V0.\n\nWith this change, the system server doesn\u0027t crash.\n\nChange-Id: Id52f684658d235fd001d9784145f4ea5ed2938b6\n" }, { "commit": "e460d1df1f789c7c8bb97024a8efbd713ac175e9", "tree": "3511036fb18828dd0ee140d33a8bcd0535ebeab6", "parents": [ "25217af2a7cae96b32ba566aaf697288f3374c99" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 29 04:52:17 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 02 02:25:18 2015 +0100" }, "message": "Revert \"Revert \"Support unresolved fields in optimizing\"\n\nThe CL also changes the calling convetion for 64bit static field set\nto use kArg2 instead of kArg1. This allows optimizing to keep\nthe asumptions:\n- arm pairs are always of form (even_reg, odd_reg)\n- ecx_edx is not used as a register on x86.\n\nThis reverts commit e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1.\n\nChange-Id: I93159917565824084abc96775f31be1a4249f2f3\n" }, { "commit": "225b6464a58ebe11c156144653f11a1c6607f4eb", "tree": "3f1c6067c3841c892edaa1a60a61af9c559cb4e4", "parents": [ "6a9984e62c08bcd78c8e49dd40b1f0f9d53513b7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 28 12:17:40 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 10:49:35 2015 +0100" }, "message": "Optimizing: Tag arena allocations in code generators.\n\nAnd completely remove the deprecated GrowableArray.\n\nReplace GrowableArray with ArenaVector in code generators\nand related classes and tag arena allocations.\n\nLabel arrays use direct allocations from ArenaAllocator\nbecause Label is non-copyable and non-movable and as such\ncannot be really held in a container. The GrowableArray\nnever actually constructed them, instead relying on the\nzero-initialized storage from the arena allocator to be\ncorrect. We now actually construct the labels.\n\nAlso avoid StackMapStream::ComputeDexRegisterMapSize() being\npassed null references, even though unused.\n\nChange-Id: I26a46fdd406b23a3969300a67739d55528df8bf4\n" }, { "commit": "85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d", "tree": "c916b01b1608558a7d8c9d100274c4c6b6706386", "parents": [ "6766eae2d91e894b4ceab9f29cc983900e7bc0c7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 09 13:15:38 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 17 14:41:52 2015 -0700" }, "message": "ART: Refactor intrinsics slow-paths\n\nRefactor slow paths so that there is a default implementation for\ncommon cases (only arm64 with vixl is special). Write a generic\nintrinsic slow-path that can be reused for the specific architectures.\nMove helper functions into CodeGenerator so that they are accessible.\n\nChange-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550\n" }, { "commit": "e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "23a8e35481face09183a24b9d11e505597c75ebb" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "message": "Revert \"Support unresolved fields in optimizing\"\nbreaks debuggable tests.\n\nThis reverts commit 23a8e35481face09183a24b9d11e505597c75ebb.\n\nChange-Id: I8e60b5c8f48525975f25d19e5e8066c1c94bd2e5\n" }, { "commit": "23a8e35481face09183a24b9d11e505597c75ebb", "tree": "bcaafb6ea001349acbf160c2cc89334fab4a38dc", "parents": [ "175dc732c80e6f2afd83209348124df349290ba8" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 08 19:56:31 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:59 2015 +0100" }, "message": "Support unresolved fields in optimizing\n\nChange-Id: I9941fa5fcb6ef0a7a253c7a0b479a44a0210aad4\n" }, { "commit": "175dc732c80e6f2afd83209348124df349290ba8", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "5d01db1aa7634a012109d43e6403451b76de1daa" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Aug 25 15:42:32 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:51 2015 +0100" }, "message": "Support unresolved methods in Optimizing\n\nChange-Id: If2da02b50d2fa668cd58f134a005f1752e7746b1\n" }, { "commit": "fe157012b6d760c275d944ff83e8bea371c59b09", "tree": "a2b013dded6e25cab1d3ff5abf09c426904e142c", "parents": [ "aef880c4b872ccf1a63a3c563cb056ae117fc9c8", "ecc4366670e12b4812ef1653f7c8d52234ca1b1f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "message": "Merge \"Add OptimizingCompilerStats to the CodeGenerator class.\"" }, { "commit": "fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a", "tree": "3528c88e104dac8e58ae5370ab066b8b1dd0218f", "parents": [ "e295be4a95d7861f6ec179edf6565f58cad747cc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 15 10:15:55 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 16 13:21:33 2015 +0100" }, "message": "Optimizing: Tag arena allocations in HGraph.\n\nReplace GrowableArray with ArenaVector in HGraph and related\nclasses HEnvironment, HLoopInformation, HInvoke and HPhi,\nand tag allocations with new arena allocation types.\n\nChange-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d\n" }, { "commit": "ecc4366670e12b4812ef1653f7c8d52234ca1b1f", "tree": "fe7be52b1025b8122547b34d8765248d5959cd3a", "parents": [ "772cc4a2d4f978888d1b1e5a78c1c16a108260ed" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 13 13:33:12 2015 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 27 15:28:25 2015 +0100" }, "message": "Add OptimizingCompilerStats to the CodeGenerator class.\n\nJust refactoring, not yet used, but will be used by the incoming patch\nseries and future CodeGen specific stats.\n\nChange-Id: I7d20489907b82678120518a77bdab9c4cc58f937\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "b485915afd8a6396df7863b651dfe832038fd680", "tree": "4d12daee263e31d9603e962c1606cae3356faafe", "parents": [ "4a08e17a9db0f68b9623849bc288c31a47868fbc", "fc6a86ab2b70781e72b807c1798b83829ca7f931" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 14:52:36 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 26 14:52:36 2015 +0000" }, "message": "Merge \"Revert \"Revert \"ART: Implement try/catch blocks in Builder\"\"\"" }, { "commit": "fc6a86ab2b70781e72b807c1798b83829ca7f931", "tree": "90201491e811cf7be0e0469d7a06a828f4384cad", "parents": [ "d3eaade87ac079accca30473ef0a3b38ab600828" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 10:33:45 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 13:49:50 2015 +0100" }, "message": "Revert \"Revert \"ART: Implement try/catch blocks in Builder\"\"\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nThis reverts commit 3e18738bd338e9f8363b26bc895f38c0ec682824.\n\nChange-Id: I4f5ea961848a0b83d8db3673763861633e9bfcfb\n" }, { "commit": "3e18738bd338e9f8363b26bc895f38c0ec682824", "tree": "708013ef06cfb524f040b2b5c494f7f3cb84ac2c", "parents": [ "0b5c7d1994b76090afcc825e737f2b8c546da2f8" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "message": "Revert \"ART: Implement try/catch blocks in Builder\"\n\nCauses OutOfMemory issues, need to investigate.\n\nThis reverts commit 0b5c7d1994b76090afcc825e737f2b8c546da2f8.\n\nChange-Id: I263e6cc4df5f9a56ad2ce44e18932ca51d7e349f\n" }, { "commit": "0b5c7d1994b76090afcc825e737f2b8c546da2f8", "tree": "057eddf8830b1991f02af3c3ce1b63dee90dd2ad", "parents": [ "1dd3136d9f6b1c7d551897a2d96c8314e40f7324" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 11 11:17:49 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 25 16:58:08 2015 +0100" }, "message": "ART: Implement try/catch blocks in Builder\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nChange-Id: I415b985596d5bebb7b1bb358a46e08b7b04bb53a\n" }, { "commit": "f39e0641a6d1a6561b20f6a130d1e763788cd70b", "tree": "1679d6e1c2e77593d67fc519fe8cb8f94ddd6d5e", "parents": [ "a256ee9ccbd01407541958476f388ae7c687a9c2" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jun 23 11:33:45 2015 +0100" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 24 08:17:25 2015 -0400" }, "message": "Minor fixes to mips64 for the arch-specific optimisation framework.\n\nChange-Id: I9d49ea61c732e4fc6b3393aa8778951e29ce4efe\n" }, { "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907", "tree": "a0a488040883c14cc6cbec3186654137459d44ff", "parents": [ "8ec0e20347e13592539a8c0786b1db1735149800" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 22 11:57:36 2015 +0100" }, "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n" }, { "commit": "4dda3376b71209fae07f5c3c8ac3eb4b54207aa8", "tree": "0d96a327d1b3a7e09eff178a66c0b5fb946cfc85", "parents": [ "71af6f7aab7491665fe2d6beb9af4c251a99ad56" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 01 18:31:49 2015 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 19 15:43:58 2015 +0100" }, "message": "MIPS: Initial version of optimizing compiler for MIPS64R6.\n\nBug: 21555893\nChange-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf\nSigned-off-by: Alexey Frunze \u003cAlexey.Frunze@imgtec.com\u003e\nSigned-off-by: Douglas Leung \u003cdouglas.leung@imgtec.com\u003e\n" } ] }