)]}'
{
  "log": [
    {
      "commit": "0806f589a8a8e1fca573069b37761c320660aa63",
      "tree": "51a26fc5e59cca70a3f6875ece57aee39962221f",
      "parents": [
        "02338775e33b553be51d44ff60bb1ef8e527bd94"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Oct 11 20:14:20 2018 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Oct 25 18:33:55 2018 +0100"
      },
      "message": "ARM64: Support interm. address for object arrays.\n\nSupport IntermediateAddress on arm64 for object\narray reads in Baker read barrier configuration.\n\nThe patch brings minor boot.oat size reduction and\nperformance improvement on Puzzle benchmark.\n\nTest: test-art-target, test-art-host, gc_stress.\nTest: 527-checker-array-access-split.\n\nBug: 26601270\nBug: 32578862\n\nChange-Id: I781a911905038b36428964a990771fdf74e99bbd\n"
    },
    {
      "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92",
      "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7",
      "parents": [
        "321b3ca9a36d769283c64d4bdee0798db80af524"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 01 14:35:42 2017 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 02 10:11:02 2017 +0000"
      },
      "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n"
    },
    {
      "commit": "e764d2e50c544c2cb98ee61a15d613161ac6bd17",
      "tree": "112aa7ca459d2edb4f800897060a2407fcc622c7",
      "parents": [
        "ca6fff898afcb62491458ae8bcd428bfb3043da1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 05 14:35:55 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 09 10:39:22 2017 +0100"
      },
      "message": "Use ScopedArenaAllocator for register allocation.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n  BatteryStats.dumpCheckinLocked() : 25.1MiB -\u003e 21.1MiB\n  BatteryStats.dumpLocked(): 49.6MiB -\u003e 42.0MiB\nThis is because all the memory previously used by Scheduler\nis reused by the register allocator; the register allocator\nhas a higher peak usage of the ArenaStack.\n\nAnd continue the \"arena\"-\u003e\"allocator\" renaming.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 64312607\nChange-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01\n"
    },
    {
      "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1",
      "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07",
      "parents": [
        "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 14:49:14 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Oct 06 17:53:50 2017 +0100"
      },
      "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n"
    },
    {
      "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32",
      "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af",
      "parents": [
        "e1e347dace0ded83774999bb26c37527dcdb1d5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 21 22:50:39 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 25 15:45:01 2017 +0100"
      },
      "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n"
    },
    {
      "commit": "bc5460b850a0fa2d8dcf6c8d36b0eb86f8fe46a8",
      "tree": "0db1314987cd0f24c7294c4ad540c7f28e2739d9",
      "parents": [
        "c1bb1cd339b2ebea9c4770fb4d61bacd7d77746f"
      ],
      "author": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Thu Jul 20 16:07:36 2017 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Mon Aug 14 10:16:34 2017 +0200"
      },
      "message": "MIPS: Support MultiplyAccumulate for SIMD.\n\nMoved support for multiply accumulate from arm64-specific to\ngeneral instruction simplification.\nAlso extended 550-checker-multiply-accumulate test.\n\nTest: test-art-host, test-art-target\n\nChange-Id: If113f0f0d5cb48e8a76273c919cfa2f49fce667d\n"
    },
    {
      "commit": "9983e302384c12a975c8d2d5ae239f79fd8e1996",
      "tree": "4e4d269fe1a3d4f0f1b93cd972adab9f17aab8e0",
      "parents": [
        "bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jul 14 14:34:22 2017 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jul 14 17:25:39 2017 +0100"
      },
      "message": "Remove the old ARM code generator from ART\u0027s Optimizing compiler.\n\nThe AArch32 VIXL-based code generator has been the default\nARM code generator in ART for some time now. The old ARM\ncode generator does not compile anymore; retiring it.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db\n"
    },
    {
      "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0",
      "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788",
      "parents": [
        "7113885fcd983b33ee1e350865d21517d6297843"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 27 16:50:47 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu May 11 10:06:04 2017 +0100"
      },
      "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n"
    },
    {
      "commit": "02b1976a9d25fb3649f734962f1127786cf9dc81",
      "tree": "d2889650a4d04495fa230384fd7dad66e46d52f3",
      "parents": [
        "d21711eae1224c18690d1a460b5b986fb4885654",
        "66d691de219e840b3f84385d8bd1b7001562b0e5"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Apr 26 15:27:13 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Apr 26 15:27:15 2017 +0000"
      },
      "message": "Merge \"ARM64: Link-time generated thunks for ArrayGet Baker CC read barrier.\""
    },
    {
      "commit": "66d691de219e840b3f84385d8bd1b7001562b0e5",
      "tree": "4034e867246db26acaa1a36b89b823ce5d0f1a58",
      "parents": [
        "38870a8a2717ccf1bcd3faddc53b1999985bb29f"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Apr 07 17:53:39 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Apr 25 18:29:33 2017 +0100"
      },
      "message": "ARM64: Link-time generated thunks for ArrayGet Baker CC read barrier.\n\nTest: Added a test to relative_patcher_arm64\nTest: m test-art-target-gtest on Nexus 6P.\nTest: Nexus 6P boots.\nTest: testrunner.py --target on Nexus 6P.\nTest: Nexus 6P boots with heap poisoning.\nTest: testrunner.py --target on Nexus 6P with heap poisoning.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: Id0f23089c55cbb53b84305c11bb4b03718561ade\n"
    },
    {
      "commit": "f34dd206d0073fb3949be872224420a8488f551f",
      "tree": "b24b451af6efdd9f67c4cbd5c37ebb4ec6a4aaad",
      "parents": [
        "1f56cb5c594f5757085820b1042988d10f02bb0b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 17:41:46 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 20 00:21:29 2017 +0100"
      },
      "message": "ARM64: Support MultiplyAccumulate for SIMD.\n\nTest: test-art-host, test-art-target.\n\nChange-Id: I06af8415e15352d09d176cae828163cbe99ae7a7\n"
    },
    {
      "commit": "19c5419d21376dd69404736b998fbbb9da54af56",
      "tree": "1e15b39f7c6662b2939bbaa7f34560fcea72e7b4",
      "parents": [
        "c46e708aa0bd7a007f0de8db1cad8ef49166ca10"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Nov 04 13:44:09 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Nov 04 16:43:41 2016 +0000"
      },
      "message": "Revert \"Revert \"Enable IntermediateAddress for primitive arrays with read barriers.\"\"\n\nThis reverts commit 4a3aa578eff94eb10450fae1772deb7cb8ddc6a6.\n\nThe failing assertion (see b/30762467):\n\n08-09 11:32:46.767  1654  1656 F dex2oatd: art/compiler/optimizing/register_allocation_resolver.cc:325] Check failed: interval-\u003eGetDefinedBy()-\u003eIsActualObject() IntermediateAddress@InstanceFieldGet\n\nthat motivated the initial revert has been removed by a\nprevious CL (commit\n70e97462116a47ef2e582ea29a037847debcc029,\nhttps://android-review.googlesource.com/#/c/254920/).\n\nTest: ART host and target (ARM, ARM64) tests with `ART_USE_READ_BARRIER\u003dtrue`.\nBug: 26601270\nBug: 12687968\nChange-Id: I09cae0c6c38ca403924153e9f0eb0cc3ff4540e7\n"
    },
    {
      "commit": "91a6516103b8bf8bb75c3a2840cbdec7521e74a7",
      "tree": "d93043f578bfa5b8d76e8c175e6441b378c4a7b2",
      "parents": [
        "6a4abc633fa8580b06056ec6f80ced8ce7511277"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Sep 19 13:54:30 2016 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Sep 19 13:54:30 2016 +0100"
      },
      "message": "Remove the `CanTriggerGC` side-effects on a few instructions.\n\nThe side-effect was specified for these instructions as they call\nruntime. We now have a list of entrypoints that we know cannot trigger\nGC. We can avoid requiring the side-effect for those.\n\nTest: Run ART test suite on Nexus 5X and host.\n\nChange-Id: I0e0e6a4d701ce6c75aff486cb0d1bc7fe2e8dda4\n"
    },
    {
      "commit": "4a3aa578eff94eb10450fae1772deb7cb8ddc6a6",
      "tree": "abb3aa17279c6a9edc9dd1c0691738a7f7c69a10",
      "parents": [
        "12ecf0800d465acdaa3deccd383ff8ed3428a183"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Aug 15 13:17:06 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Aug 15 13:17:06 2016 +0000"
      },
      "message": "Revert \"Enable IntermediateAddress for primitive arrays with read barriers.\"\n\nThis CL breaks the angler-userdebug build with\n`ART_USE_READ_BARRIER\u003dtrue`.\n\nTest: Build angler-userdebug with `ART_USE_READ_BARRIER\u003dtrue`.\nBug: 30762467\nBug: 26601270\nBug: 12687968\n\nThis reverts commit 12ecf0800d465acdaa3deccd383ff8ed3428a183.\n\nChange-Id: Ia2069ac9436d2336311dd8d0f183c02e587586ae\n"
    },
    {
      "commit": "12ecf0800d465acdaa3deccd383ff8ed3428a183",
      "tree": "229f7438b82c945f4b3221f6c1033eaf96a9a1c6",
      "parents": [
        "d16ae7fe70d74091778e5952b7920df14866287f"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Aug 08 10:18:37 2016 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Aug 08 10:18:37 2016 +0100"
      },
      "message": "Enable IntermediateAddress for primitive arrays with read barriers.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 26601270\nBug: 12687968\nChange-Id: I6736ba7b1809bece1bf3cd82c69e4f42a0d3c4a7\n"
    },
    {
      "commit": "328429ff48d06e2cad4ebdd3568ab06de916a10a",
      "tree": "6290ac8afc3e93488382727f6765f548a2cfff04",
      "parents": [
        "79e73245140f4115039a7284b3797d701f368fe6"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jul 06 16:23:04 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jul 21 09:16:43 2016 +0000"
      },
      "message": "ARM: Port instr simplification of array accesses.\n\nAfter changing the addressing mode for array accesses (in\nhttps://android-review.googlesource.com/248406) the \u0027add\u0027\ninstruction that calculates the base address for the array can be\nshared across accesses to the same array.\n\nBefore https://android-review.googlesource.com/248406:\n    add IP, r[Array], r[Index0], LSL #2\n    ldr r0, [IP, #12]\n    add IP, r[Array], r[Index1], LSL #2\n    ldr r0, [IP, #12]\n\nBefore this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index1], LSL #2]\n\nAfter this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    ldr r0, [IP, r[Index1], LSL #2]\n\nLink to the original optimization:\n    https://android-review.googlesource.com/#/c/127310/\n\nTest: Run ART test suite on Nexus 6.\nChange-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f\n"
    },
    {
      "commit": "46817b876ab00d6b78905b80ed12b4344c522b6c",
      "tree": "6715bee60b0682a10437866c9617cb442146aa2f",
      "parents": [
        "f59149a151ee694484e21da7b3b207920dead5a6"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Mar 29 12:21:58 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Apr 19 18:33:06 2016 +0100"
      },
      "message": "Use iterators \"before\" the use node in HUserRecord\u003c\u003e.\n\nCreate a new template class IntrusiveForwardList\u003c\u003e that\nmimicks std::forward_list\u003c\u003e except that all allocations\nare handled externally. This is essentially the same as\nboost::intrusive::slist\u003c\u003e but since we\u0027re not using Boost\nwe have to reinvent the wheel.\n\nUse the new container to replace the HUseList and use the\niterators to \"before\" use nodes in HUserRecord\u003c\u003e to avoid\nthe extra pointer to the previous node which was used\nexclusively for removing nodes from the list. This reduces\nthe size of the HUseListNode by 25%, 32B to 24B in 64-bit\ncompiler, 16B to 12B in 32-bit compiler. This translates\ndirectly to overall memory savings for the 64-bit compiler\nbut due to rounding up of the arena allocations to 8B, we\ndo not get any improvement in the 32-bit compiler.\n\nCompiling the Nexus 5 boot image with the 64-bit dex2oat\non host this CL reduces the memory used for compiling the\nmost hungry method, BatteryStats.dumpLocked(), by ~3.3MiB:\n\nBefore:\n  MEM: used: 47829200, allocated: 48769120, lost: 939920\n  Number of arenas allocated: 345,\n  Number of allocations: 815492, avg size: 58\n  ...\n  UseListNode    13744640\n  ...\nAfter:\n  MEM: used: 44393040, allocated: 45361248, lost: 968208\n  Number of arenas allocated: 319,\n  Number of allocations: 815492, avg size: 54\n  ...\n  UseListNode    10308480\n  ...\n\nNote that while we do not ship the 64-bit dex2oat to the\ndevice, the JIT compilation for 64-bit processes is using\nthe 64-bit libart-compiler.\n\nBug: 28173563\nChange-Id: I985eabd4816f845372d8aaa825a1489cf9569208\n"
    },
    {
      "commit": "7fc6350f6f1ab04b52b9cd7542e0790528296cbe",
      "tree": "26a33ef7bb2e49a9b7c7d9436194a92cb447b317",
      "parents": [
        "b7f257f353b1eb2db2732939a0404c118316891d"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Feb 09 17:15:29 2016 +0000"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Mar 11 12:49:27 2016 +0000"
      },
      "message": "Integrate BitwiseNegated into shared framework.\n\nShare implementation between arm and arm64.\n\nChange-Id: I0dd12e772cb23b4c181fd0b1e2a447470b1d8702\n"
    },
    {
      "commit": "4a0dad67867f389e01a5a6c0fe381d210f687c0d",
      "tree": "91f1e70f4a2d0bd32aa7eb51e546f5330d72f772",
      "parents": [
        "d15ede2df7d157ea5480614fd18c2bf0d37a6c2a"
      ],
      "author": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Tue Jan 26 12:28:31 2016 +0300"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Feb 25 10:14:30 2016 +0000"
      },
      "message": "Revert \"Revert \"ARM/ARM64: Extend support of instruction combining.\"\"\n\nThis reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.\n\nChange-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6\n"
    },
    {
      "commit": "6b5afdd144d2bb3bf994240797834b5666b2cf98",
      "tree": "d536cd7b3aaf55c563e82c2c522521a91b2bb953",
      "parents": [
        "debeb98aaa8950caf1a19df490f2ac9bf563075b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "message": "Revert \"ARM/ARM64: Extend support of instruction combining.\"\n\nThe test fails its checker parts.\n\nThis reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.\n\nChange-Id: I49929e15950c7814da6c411ecd2b640d12de80df\n"
    },
    {
      "commit": "debeb98aaa8950caf1a19df490f2ac9bf563075b",
      "tree": "b2a7a7cc6fb2f56d4bcc6cecaa80035668f38dc4",
      "parents": [
        "6aadaef35ea52506db61e463910c2520b702ca5e"
      ],
      "author": {
        "name": "Ilmir Usmanov",
        "email": "i.usmanov@samsung.com",
        "time": "Fri Dec 11 11:39:44 2015 +0300"
      },
      "committer": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Thu Jan 21 11:07:38 2016 +0300"
      },
      "message": "ARM/ARM64: Extend support of instruction combining.\n\nCombine multiply instructions in the following way:\nARM64:\nMUL/NEG -\u003e MNEG\nARM32 (32-bit integers only):\nMUL/ADD -\u003e MLA\nMUL/SUB -\u003e MLS\n\nChange-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb\n"
    }
  ]
}