)]}' { "log": [ { "commit": "7f88c1a269754001bfcaf311b378cf1cc71acf84", "tree": "147bb988929e8bd8827c4b148f28da4c28c0ea70", "parents": [ "5247113f3277fd679e3e1beeb6fbfb30797aa481" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Tue Nov 06 11:42:41 2018 +0000" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Jan 30 14:09:25 2019 +0000" }, "message": "ART: Enable ISA features run-time detection for ARM64\n\nOn a target run-time detected ISA features can be more accurate than\ninstruction set features based on a build-time information such as an\ninstruction set variant or C++ defines. Build-time based features can\nbe too generic and do not include all features a target CPU supports.\n\nThis CL enables instruction feature run-time detection in the JIT/AOT\ncompilers:\n\n- The value \"runtime\" to the option \"--instruction-set-features\" to try\nto detect CPU features at run time. If a target does not support run-time\ndetection it has the same effect as the value \"default\".\n- Runtime uses \"--instruction-set-features\u003druntime\" if run-time detection is\nsupported.\n\nThe CL also cleans up how an instruction set feature string is processed\nby InstructionSetFeatures::AddFeaturesFromString. It used to make redundant\nuses of Trim in subclasses. The calls are replaced with DCHECKs\nverifying that feature names are already trimmed.\n\nTest: m test-art-target-gtest\nTest: m test-art-host-gtest\nTest: art/test.py --target --optimizing --interpreter --jit\nTest: art/test.py --host --optimizing --interpreter --jit\nTest: Pixel 3 UI booted\n\nChange-Id: I223d5bc968d589dba5c09f6b03ee8c25987610b0\n" }, { "commit": "8764dc3b3eda7f6f13ed7b584475503fe5bedd59", "tree": "e8f6e3a4a2596595ffdc8a517daaf37030482eae", "parents": [ "49b74a8c685acfe43dd33e3f51a24c486388bee1" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jan 07 15:20:12 2019 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 09 12:38:30 2019 -0800" }, "message": "ART: Use iosfwd more\n\nUse iosfwd where an include of ostream is unnecessary. Also move\ncallee_save_type.h to runtime.\n\nBug: 119869270\nTest: mmma art\nChange-Id: Id8995d6f524e4c491eb6f57fdffb940cf35d291f\n" }, { "commit": "c3e1895e7443c61b77f5c51cd2d18819cade57c1", "tree": "bc2705ee47091e37d683cafa020f53190708b089", "parents": [ "6623bc389c43efc87668ce7465e19b195e765e22" ], "author": { "name": "David Sehr", "email": "sehr@google.com", "time": "Fri May 11 16:59:31 2018 -0700" }, "committer": { "name": "David Sehr", "email": "sehr@google.com", "time": "Fri May 11 17:40:56 2018 -0700" }, "message": "Prepare to move ArtDexFileLoader to libdexfile\n\nMove file_utils and friends to libartbase so that ArtDexFileLoader can\nbe moved to libdexfile. This will clean up duplication and complexity\nwith zip file handling.\n\nBug: 78652467\nTest: make -j 40 test-art-host-gtest\nChange-Id: Ia5eac1f93caf3fa918b4b48803cbfd842035e29e\n" }, { "commit": "d747c13e19763b295cde7dc29a2cc3ed8585e93d", "tree": "e86d7f3fa6a351f6145bfa11c9018e8642245599", "parents": [ "7e25123127b0b02678a5101d0faa18b65895d723" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Oct 26 09:30:21 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jan 13 15:41:34 2017 +0000" }, "message": "ARM: Update `ArmInstructionSetFeatures` to track ARMv8-A.\n\nSome instructions introduced in ARMv8-A will be useful to improve\nthe generated code.\n\nAlso add a HasAtLeast() method to the InstructionSetFeatures class.\n(more info why this is needed in instruction_set_features.h).\n\nTest: mma test-art-target \u0026\u0026 mma test-art-host\n\nChange-Id: If42fa4f0b09d3255851c7b4d85271e7163f0b39c\nSigned-off-by: Alexandre Rames \u003calexandre.rames@linaro.org\u003e\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "b595b40c151c7e6de5e95944f6b993c57e780dd5", "tree": "6b66aec7d041d5ab49b5061f0af2e5776284f596", "parents": [ "6d2741f18be435c686bd774eecb7359c17ae2132" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Fri Sep 23 11:06:03 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Mon Jan 09 15:18:41 2017 +0000" }, "message": "Remove the unused SMP instruction set feature option.\n\nThe SMP option is currently not used in the ART codebase\n(and it rots away).\nSingle CPU systems that run SMP code should be able to deal\nwith it nicely (otherwise the CPU has some serious problems).\n\nTest: mma test-art-target \u0026\u0026 mma test-art-host\n\nChange-Id: Ifaab42b29de1062866a0af7525de2f834a4a5a57\n" }, { "commit": "0415b4e2169272f94f4aba9f3d56ec8105831f8b", "tree": "7caf8fce823d3b3ebe00cca06ce3f874786cae55", "parents": [ "75dccb7238714358fca9e5e993e4daabe24af085" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 06 15:17:07 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Oct 26 08:44:55 2016 -0700" }, "message": "ART: Change InstructionSetFeatures to return unique_ptr\n\nThis makes clear the ownership of the object.\n\nTest: m test-art-host\nChange-Id: I55fa734f04bc3046d370f4dcf98ce6b17c59e234\n" }, { "commit": "24a05f449a6b4b0e4944c2055f0c7490d6a09861", "tree": "6d05d580ae522e858a28b9d6c62b9ac9095548dd", "parents": [ "425587d25832145a45a0b76beaa93996b0226f0d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 03 13:46:54 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 03 14:22:56 2015 -0700" }, "message": "ART: Add support for \"silvermont\" variant\n\nThe variant is already supported in the build system and wired up\nfor the Nexus Player (fugu). The values are copied from the build\nsystem and correspond to documentation in, e.g.,\nhttp://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf\nchapter 15, section 1.1.\n\nChange-Id: I9facaa9d5b8bae3d98cf48f2969d02d11ebfe0e4\n" }, { "commit": "57b34294758e9c00993913ebe43c7ee4698a5cc6", "tree": "981821619027686f83fbe00445299b0522f1df05", "parents": [ "4945bfef00ac446d9c5458e55500229d463ab4c3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 14 15:45:59 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 11:32:48 2015 -0800" }, "message": "ART: Allow to compile interpret-only mips64 files\n\nInclude enough infrastructure to allow cross-compiling for mips64,\ninterpret-only. This includes the instruction-set-features, frame\nsize info and utils assembler.\n\nAlso add a disassembler for oatdump, and support in patchoat.\n\nNote: the runtime cannot run mips64, yet.\n\nChange-Id: Id106581fa76b478984741c62a8a03be0f370d992\n" }, { "commit": "d582fa4ea62083a7598dded5b82dc2198b3daac7", "tree": "c76704c266ef4687eab425612ddf3fd24f93fe8d", "parents": [ "f20076ff813b8012096ff31af236d59db3c0f4e1" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Nov 05 23:46:43 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Nov 13 16:17:46 2014 -0800" }, "message": "Instruction set features for ARM64, MIPS and X86.\n\nAlso, refactor how feature strings are handled so they are additive or\nsubtractive.\nMake MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler\nrather than #ifdefs that wouldn\u0027t have worked in cross-compilation.\nAdd SIMD features for x86/x86-64 proposed in:\n https://android-review.googlesource.com/#/c/112370/\n\nBug: 18056890\n\nChange-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666\n" } ] }