)]}'
{
  "log": [
    {
      "commit": "5f8741860d465410bfed495dbb5f794590d338da",
      "tree": "cf295594b5b018e96959ddf474e7c8b7374006b5",
      "parents": [
        "c670efd6ba9dbd1166bfd8c805bb6b2df7d4313a"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Mar 04 15:42:45 2015 -0500"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Mar 05 11:08:33 2015 +0000"
      },
      "message": "[optimizing] Use callee-save registers for x86\n\nAdd ESI, EDI, EBP to available registers for non-baseline mode. Ensure\nthat they aren\u0027t used when byte addressible registers are needed.\n\nChange-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    }
  ]
}