)]}' { "log": [ { "commit": "607fa7b07233a7233ebe21bba8f3e7c1925ae0f2", "tree": "a04f1074331ac82ad077044e3f373312f61e5901", "parents": [ "1dc387152a84193937bd1f88e9e10fff6449d695", "700a402244a1a423da4f3ba8032459f4b65fa18f" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue May 20 05:29:04 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 20 05:29:04 2014 +0000" }, "message": "Merge \"Now we have a proper C++ library, use std::unique_ptr.\"" }, { "commit": "700a402244a1a423da4f3ba8032459f4b65fa18f", "tree": "4c22fcda04d271bd55a37aff30650214af17a90c", "parents": [ "047c11adcbcbc0bcf210defdfcbada763961ffee" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 16:49:03 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 22:27:39 2014 -0700" }, "message": "Now we have a proper C++ library, use std::unique_ptr.\n\nAlso remove the Android.libcxx.mk and other bits of stlport compatibility\nmechanics.\n\nChange-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61\n" }, { "commit": "082833c8d577db0b2bebc100602f31e4e971613e", "tree": "a92e43ebea394629dfb43adcce878404de5bc330", "parents": [ "6b522855f913617e00c1783264436145d00cc533" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat May 17 23:16:26 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 19 20:02:10 2014 -0700" }, "message": "Quick compiler, out of registers fix\n\nIt turns out that the register pool sanity checker was not\nworking as expected, leaving some inconsistencies unreported.\nThis could result in \"out of registers\" failures, as well\nas other more subtle problems.\n\nThis CL fixes the sanity checker, adds a lot more check and cleans\nup the previously undetected episodes of insanity.\n\nCherry-pick of internal change 468162\n\nChange-Id: Id2da97e99105a4c272c5fd256205a94b904ecea8\n" }, { "commit": "2afe49450f2e018f18b5de45428b9174bfd6f196", "tree": "2d6f96d2dfc4c8baaef172259a824708e510225e", "parents": [ "84e524207b23d58a1b1e5f4443000ccac97c4184" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Mon May 19 10:25:33 2014 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Mon May 19 10:26:17 2014 -0700" }, "message": "Follow up to \"Add ISA directory to image and odex pathnames.\"\n\nChange-Id: I7f08cc3052fbed93a56ccf1ab7675ae8bc129da9\n" }, { "commit": "84e524207b23d58a1b1e5f4443000ccac97c4184", "tree": "6eb6204994d342a653fba4eea275a536a720b036", "parents": [ "f04544ffdb801946d087ae1322c890e34e185156", "0e12bdc49744eb6d5c29b9611a8dbe10bac4cd53" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Mon May 19 16:50:20 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 19 16:50:21 2014 +0000" }, "message": "Merge \"Add ISA directory to image and odex pathnames.\"" }, { "commit": "4f3f3fa1dde1bb0c89485012f7e6396be2ad2850", "tree": "6b07b706beba9e0a4ffc577d2c01870435369848", "parents": [ "bf17a08fb48fa296acb09904d4c10ba42f63f55d", "ddb311fdeca82ca628fed694c4702f463b5c4927" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 19 09:24:53 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 19 09:24:53 2014 +0000" }, "message": "Merge \"Build live ranges in preparation for register allocation.\"" }, { "commit": "ddb311fdeca82ca628fed694c4702f463b5c4927", "tree": "24acde84ed7d0229c36d9bbca2a421acdff9d7a1", "parents": [ "27710fa87cc7fc0f205a6b5a46f418a0cf9a5171" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 16 09:28:54 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 19 10:17:11 2014 +0100" }, "message": "Build live ranges in preparation for register allocation.\n\nChange-Id: I7ae24afaa4e49276136bf34f4ba7d62db7f28c01\n" }, { "commit": "f832284dd847ff077577bb5712225430bbbb3b67", "tree": "44f6b91098639c6ebc438b4ec998d0dc128cef9a", "parents": [ "8f0776768712b2021aa8fb649b51017b9f0fc7a9" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 16 10:59:25 2014 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Sun May 18 12:50:33 2014 -0700" }, "message": "Delete ClassHelper and fix compaction bug in GetDirectInterface\n\nCleanup helps to prevent compaction bugs. Fixed a fairly serious\ncompaction error caused by calling ClassHelper::GetDirectInterface\nwithout handling the case where it causes thread suspension due to\nResolveType.\n\nBug: 8981901\n\nChange-Id: I82b3bb6dd48d21eb6ece7aae0733c4a23c2bc408\n" }, { "commit": "f0972a410a0665dbe32bd96df09a572d69f9f3a3", "tree": "7e68b84a8395c72bdacb293c9e42cb3817f14668", "parents": [ "de1129a26e0474ea8bb9112938ebb867163969fd" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Fri May 16 17:43:39 2014 +0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri May 16 17:10:20 2014 -0700" }, "message": "Fix generic jni issue in ArtMethod::GetQuickFrameInfo\n\nThe 64-bit host mode fails to start due to incorrect\ndetection of GetQuickGenericJniTrampoline.\nThe quick_code is 32-bit and taken from oat file, but\nGetQuickGenericJniTrampoline returnf 0x7fffxx (64-bit)\naddress of trampoline and execution went to incorrect way.\n\nSome clean-up.\n\nOriginal Author: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\nChange-Id: I0952443b2a9f6833ad37ec373837ae208681fad7\n" }, { "commit": "0e12bdc49744eb6d5c29b9611a8dbe10bac4cd53", "tree": "aba31f1d671b4816fb63fca00b985ab0d2b6a12b", "parents": [ "de1129a26e0474ea8bb9112938ebb867163969fd" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Wed May 14 17:44:28 2014 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri May 16 16:14:50 2014 -0700" }, "message": "Add ISA directory to image and odex pathnames.\n\nBug: 14882223\nBug: 14694978\nChange-Id: Ic1b5ae836b8e91ea461dcd4f3da8e38dc3bec00f\n" }, { "commit": "ed4b6267dde3bc93fae9ce7000880ca017e04114", "tree": "142b04950b26985f836089ad8fdea68bec9f7f30", "parents": [ "49f0ca7660b340d89ed5892e3a38a6b66b279e5e", "d65c51a556e6649db4e18bd083c8fec37607a442" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Fri May 16 18:06:42 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 16 18:06:43 2014 +0000" }, "message": "Merge \"ART: Add support for constant vector literals\"" }, { "commit": "d65c51a556e6649db4e18bd083c8fec37607a442", "tree": "97fcb17ae74a587c6ef756dda6f4b03db5e9950f", "parents": [ "1e97c4a4ab9f17d1394b952882d59d894b1e3c74" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Apr 29 16:55:20 2014 -0400" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri May 16 11:04:27 2014 -0700" }, "message": "ART: Add support for constant vector literals\n\nAdd in some vector instructions. Implement the ConstVector\ninstruction, which takes 4 words of data and loads it into\nan XMM register.\n\nInitially, only the ConstVector MIR opcode is implemented. Others will\nbe added after this one goes in.\n\nChange-Id: I5c79bc8b7de9030ef1c213fc8b227debc47f6337\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "49f0ca7660b340d89ed5892e3a38a6b66b279e5e", "tree": "1be6a33f34ba2e7b8a20a208330df9060852d0d0", "parents": [ "1e97c4a4ab9f17d1394b952882d59d894b1e3c74", "db2633ce0358c704f97130a94b582602cb01d14a" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 16 17:41:50 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 16 17:41:50 2014 +0000" }, "message": "Merge \"Change ObjectLock to take Handle instead of Handle pointer.\"" }, { "commit": "db2633ce0358c704f97130a94b582602cb01d14a", "tree": "ab941b728fe4343eb9872abc85755640bf059800", "parents": [ "f59c6dda4928cfb05d32a56fd161e3f86a9ca560" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 16 09:59:29 2014 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 16 10:36:37 2014 -0700" }, "message": "Change ObjectLock to take Handle instead of Handle pointer.\n\nChange-Id: I9abdcdc5c9c9174634336b9250ab24c6aee434ec\n" }, { "commit": "1e97c4a4ab9f17d1394b952882d59d894b1e3c74", "tree": "1942cbd3407f75e81e21200f56211aa8ed3bb767", "parents": [ "c001b0952513690216f9a14153a839d569a91538", "9ee801f5308aa3c62ae3bedae2658612762ffb91" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Fri May 16 17:31:55 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 16 17:31:56 2014 +0000" }, "message": "Merge \"Add x86_64 code generation support\"" }, { "commit": "c830430ed65497c2268649d8e78121364e31b184", "tree": "8e79160de1296e8f6301c9bbb10d48f1d81d1f8d", "parents": [ "c006db38389748e5fa9508c4ef32cc57fd68a014" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Thu May 15 17:21:01 2014 +0100" }, "committer": { "name": "Stuart Monteith", "email": "srdmarm@gmail.com", "time": "Fri May 16 12:52:59 2014 +0100" }, "message": "AArch64: Fix quick compiler monitor implementation.\n\nAlso with some small fixes :\n1. Enable some dex byte code to compile.\n2. Copy the register definition from runtime.cc.\n3. A quick fix for \"cmp Wn, Wm\" in the assembler.\n4. Optimise GenMoveException a bit by using xzr.\n5. Fix improper use of StoreValueWide() on 32-bit value in FlushIns().\n6. Fix one debug assert in the assembler.\nIt can pass all cases in run-all-test, except 044 which also fails with\nthe interpreter.\n\nChange-Id: I9cc0253f1039c78d5100640235ac33e884b02560\n" }, { "commit": "8f1a4d4e92e9572dc1b5eaf33f03d390c4ff801a", "tree": "fcf787dd087cfeaf16aefa2b84a80547ccba9f7d", "parents": [ "27710fa87cc7fc0f205a6b5a46f418a0cf9a5171" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 16 09:36:00 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 16 09:47:02 2014 +0100" }, "message": "Workaround for multi-line comment error when compiled with g++.\n\nChange-Id: I2f6921d698688526bc52cd7dd33fd39c6853dc09\n" }, { "commit": "27710fa87cc7fc0f205a6b5a46f418a0cf9a5171", "tree": "143e2cf1176eee3555236ad863b22c51b3a74613", "parents": [ "b374fdba01c1c8fd59c1d0f0887451acdf24e90f", "0d3f578909d0d1ea072ca68d78301b6fb7a44451" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 16 08:10:05 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 16 08:10:05 2014 +0000" }, "message": "Merge \"Linearize the graph before creating live ranges.\"" }, { "commit": "0d3f578909d0d1ea072ca68d78301b6fb7a44451", "tree": "5a90ec26839afa06294a46e67a4c4481982c47bf", "parents": [ "c2ffcecb61e474f29f3c6a8721dfd00e0252b1f8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 14 09:43:38 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 16 09:07:31 2014 +0100" }, "message": "Linearize the graph before creating live ranges.\n\nChange-Id: I02eb5671e3304ab062286131745c1366448aff58\n" }, { "commit": "380d24d9af676d047148083774fa634b77a00634", "tree": "d4c3070b228c88c7f9b0f11151e565da1c596782", "parents": [ "e1a71b2a6e899645b006c29ba37695f521545a5b", "507dfdd147c97bfbadebfd63584d094b6a4e7b47" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri May 16 00:06:58 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 16 00:06:59 2014 +0000" }, "message": "Merge \"Compatibility layer to transition from UniquePtr to std::unique_ptr.\"" }, { "commit": "507dfdd147c97bfbadebfd63584d094b6a4e7b47", "tree": "cce43931b6dcd088cb2932c2491f86116353a27f", "parents": [ "922ddb30982d2597eab634d8b8598bec0eb7d3b7" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 15 16:42:40 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 15 16:50:51 2014 -0700" }, "message": "Compatibility layer to transition from UniquePtr to std::unique_ptr.\n\nUse ART_WITH_STLPORT (enabled for the target) to cause the use of UniquePtr,\nfor the host switch to std::unique_ptr. For now the type remains called\nUniquePtr.\nMake dalvik compile with clang on the host, move its build to C++11.\n\nChange-Id: I5ba8d2757904bc089ed62047ea03de3c0853fb12\n" }, { "commit": "e1a71b2a6e899645b006c29ba37695f521545a5b", "tree": "ab68aabb74810e4b1214edc7ea663e0957aa3c43", "parents": [ "922ddb30982d2597eab634d8b8598bec0eb7d3b7", "5678455bdf9ebf2bd88ab39a9aeb6e08b7c6e245" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Thu May 15 22:07:33 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 15 22:07:34 2014 +0000" }, "message": "Merge \"ART: A Compile Filter for x86_64\"" }, { "commit": "13ff8cd5d29c66de49506b0d7dddf8e0a959e104", "tree": "8b10f0a96cf225fe8cbd0a7ac8a25d205b98d9e0", "parents": [ "b2c3e10deb6a2f069748c7a48e778a5da66900fd", "fe8cf8b1c1b4af0f8b4bb639576f7a5fc59f52ea" ], "author": { "name": "Bill Buzbee", "email": "buzbee@google.com", "time": "Thu May 15 19:55:32 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 15 19:55:32 2014 +0000" }, "message": "Merge \"Quick Compiler: fix Arm cts failures\"" }, { "commit": "fe8cf8b1c1b4af0f8b4bb639576f7a5fc59f52ea", "tree": "5b29b62d8d700b96a8f99c421c007bbdcfed79f6", "parents": [ "3ba5511665ffd31cc766fe7774a94eb18696a845" ], "author": { "name": "Bill Buzbee", "email": "buzbee@google.com", "time": "Thu May 15 13:57:54 2014 +0000" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu May 15 12:53:02 2014 -0700" }, "message": "Quick Compiler: fix Arm cts failures\n\nFixes move_wide_16#testN1, move_wide_16#testN2\n\nTwo bugs for the price of one (thanks CTS!)\n\nFirst, the new stack overflow checking code was broken for very\nlarge frames. For Arm on method entry, we only have 1 available\ntemp register, r12, until argument registers are flushed.\nPreviously, for explicit checks on large frames,\nr12 was immediately loaded with the stack_end value. However,\nlater on when the frame is extended, if the frame size exceeds\nthe range of a reg-reg-imm subtract, the codegen utilities will\nallocate a new temporary register to complete the operation. r12\nwas getting clobbered. Similarly, for medium-large frames r12\ncould get clobbered during frame creation.\n\nWhat we should always do when directly using fixed registers like\nthis is to lock them to prevent them from being allocated as a\ntemp. The other half of the first bug is easily solved by delaying\nthe load of stack_end until after the new sp is computed. We\u0027ll\nincrease the stall cost, but this is an uncommon case.\n\nThe second bug was likely a typo in LoadValueDisp(). I\u0027m a bit\nsurprised we hadn\u0027t hit this one earlier - but perhaps it was\nrecently introduced. The wrong base register was being used in\nthe non-float, wide, excessive offset case (which I suppose is also\nsomewhat uncommon).\n\nCherry-pick of internal commit If5b30f729e31d86db604045dd7581fd4626e0b55\n\nChange-Id: If5b30f729e31d86db604045dd7581fd4626e0b55\n" }, { "commit": "b2c3e10deb6a2f069748c7a48e778a5da66900fd", "tree": "e169cabde7c6b44c346273ed49d5a5bf6d1c1c1e", "parents": [ "3ba5511665ffd31cc766fe7774a94eb18696a845", "b14329f90f725af0f67c45dfcb94933a426d63ce" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu May 15 19:34:40 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 15 19:34:41 2014 +0000" }, "message": "Merge \"ART: Fix MonitorExit code on ARM\"" }, { "commit": "b14329f90f725af0f67c45dfcb94933a426d63ce", "tree": "eca2720bdc759d2e4b5058bc022f595303ebb971", "parents": [ "30b65201aa9c953433dbde1288e9b1b883042cd1" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu May 15 11:16:06 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu May 15 12:32:44 2014 -0700" }, "message": "ART: Fix MonitorExit code on ARM\n\nWe do not emit barriers on non-SMP systems. But on ARM, we have\nplaces that need to conditionally execute, which is done through\nan IT instruction. The guide of said instruction thus changes\nbetween SMP and non-SMP systems.\n\nTo cleanly approach this, change the API so that GenMemBarrier\nreturns whether it generated an instruction. ARM will have to\nquery the result and update any dependent IT.\n\nThrow a build system error if TARGET_CPU_SMP is not set.\n\nFix runtime/Android.mk to work with new multilib host.\n\nBug: 14989275\nChange-Id: I9e611b770e8a1cd4ca19367d7dae0573ec08dc61\n" }, { "commit": "93dcff30c9bea0d6c7ca3a71a1bf460336c3467d", "tree": "3a1d4da1bf1ec9c4397c52e084d1056939c34034", "parents": [ "30b65201aa9c953433dbde1288e9b1b883042cd1" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 15 09:11:23 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 15 09:11:23 2014 -0700" }, "message": "Fix CompilationUnit constructor issues.\n\nEnsure target64 is initialized. Switch from NULL to nullptr as the former gives\ncompilation errors with std::unique_ptr from libc++.\n\nChange-Id: I7153368d9324d10ef257f7c7ce9571a1753e5ba8\n" }, { "commit": "a2eca52f55e545c6f90807ce8bbf778495c4a6f6", "tree": "67e2a2a07513e9b0d1945f9dfd13bdb9398be141", "parents": [ "23d2b95b1d1c92898336a4ebf5c0281f79fb7581" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed May 14 17:37:41 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed May 14 17:43:12 2014 -0700" }, "message": "ART: Fix oat_test for 64b\n\nThe QuickEntryPoints structure has a size dependent on the pointer\nsize.\n\nChange-Id: I369353200430a6ccaccded7589105312fd411b97\n" }, { "commit": "a1926cdbd05314accb55cc7d8fcb37fb361bbf8a", "tree": "0fa125c44bee6c6e7b6d9dccaedb7907a9a123d7", "parents": [ "5200a9bc07e9b27dbe9c95a3043ba8265128b1a3", "9b9dec8bbcb812315eb0b68b3465c6c567f09527" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed May 14 23:18:50 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 14 23:18:52 2014 +0000" }, "message": "Merge \"ART: Fix ARM dmb placement in monitor-exit\"" }, { "commit": "5200a9bc07e9b27dbe9c95a3043ba8265128b1a3", "tree": "ef338fa58b323cd49db6eda4ace4388831d0a2eb", "parents": [ "5493f0b59b31453c725a32da7de3b6b60c3df713", "421c53742610c053543f8c84e04d5e0c5185d68c" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed May 14 22:28:33 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 14 22:28:33 2014 +0000" }, "message": "Merge \"Address comments from HandleScope change.\"" }, { "commit": "421c53742610c053543f8c84e04d5e0c5185d68c", "tree": "8cd10900e452dc77f0637f9ee18f3e4347ea4b9f", "parents": [ "d0916f36d27b643bca970f3645c38f44270c74ef" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed May 14 14:11:40 2014 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed May 14 14:11:40 2014 -0700" }, "message": "Address comments from HandleScope change.\n\nFor:\nhttps://android-review.googlesource.com/#/c/93793\n\nChange-Id: I020d22a1508bf4f1770e6806d70e4fbb9a0fa0ab\n" }, { "commit": "c2ffcecb61e474f29f3c6a8721dfd00e0252b1f8", "tree": "34d20940d660098d0bb813cec0a1dd8aadca3f69", "parents": [ "f54fcba62745f897b9e741594dc5f4b2143601f6", "f635e63318447ca04731b265a86a573c9ed1737c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 14 13:27:44 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 14 13:27:45 2014 +0000" }, "message": "Merge \"Add a compilation tracing mechanism to the new compiler.\"" }, { "commit": "f635e63318447ca04731b265a86a573c9ed1737c", "tree": "47cab84a6ac47d8a4f5f281e3eabdf1780f220d0", "parents": [ "d115735fe5523ff72319f0968f773683323c7f79" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 14 09:43:38 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 14 14:26:11 2014 +0100" }, "message": "Add a compilation tracing mechanism to the new compiler.\n\nCode mostly imported from: https://android-review.googlesource.com/#/c/81653/.\n\nChange-Id: I150fe942be0fb270e03fabb19032180f7a065d13\n" }, { "commit": "f54fcba62745f897b9e741594dc5f4b2143601f6", "tree": "c3e6f99deb651b6cca681395cf5168eb6c67b877", "parents": [ "5c13d43f69a5c893b4ee7abf02772ad526b3d263", "26ee07a9dbdff5d7ea61ff412e5fb7f510972aad" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Wed May 14 13:24:39 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 14 13:24:39 2014 +0000" }, "message": "Merge \"Support any cpu register sequence in LoadArgRegs\"" }, { "commit": "5c13d43f69a5c893b4ee7abf02772ad526b3d263", "tree": "7a84542f6047724e31a376d4ec2b7b67c98088c5", "parents": [ "d115735fe5523ff72319f0968f773683323c7f79", "9bf549d472462e4d1888a97c218a8c26fe3bfefb" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Wed May 14 13:22:45 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 14 13:22:45 2014 +0000" }, "message": "Merge \"x86_64: Handle UnsafeGet/Put equal to x86\"" }, { "commit": "d115735fe5523ff72319f0968f773683323c7f79", "tree": "bbc1edd4e14faf70c048f99d30a144857ee32fc4", "parents": [ "d0916f36d27b643bca970f3645c38f44270c74ef", "c93ac8b73b5772e43b6dd1cc9e1deee79ca68849" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 14 10:23:03 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 14 10:23:04 2014 +0000" }, "message": "Merge \"Fix special getter/setter to use RegClassForFieldLoadStore().\"" }, { "commit": "c93ac8b73b5772e43b6dd1cc9e1deee79ca68849", "tree": "12167d8a9d26cbbec96737d25b0f9d2466900b2d", "parents": [ "ad930da1d67968600aab8441c24f5c4cc6e001bd" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 13 17:53:49 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 14 10:24:49 2014 +0100" }, "message": "Fix special getter/setter to use RegClassForFieldLoadStore().\n\nThis ensures correct register class is used for volatile\nload/store in these getters and setters.\n\nBug: 14112919\nChange-Id: Ib7aa83d441fb007e97f9acc2a778bc20ffed837c\n" }, { "commit": "5678455bdf9ebf2bd88ab39a9aeb6e08b7c6e245", "tree": "9e720da92c2c848e920a8f4ef13d341e4010d284", "parents": [ "d0916f36d27b643bca970f3645c38f44270c74ef" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue May 13 12:12:00 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed May 14 06:06:13 2014 +0000" }, "message": "ART: A Compile Filter for x86_64\n\nThis patch enables an x86_64 compile filter for everything\nwe\u0027re not ready to compile right now.\n\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\nChange-Id: I9ba87cf7f05e3465f12fd16a87b54f9649baf88a" }, { "commit": "26ee07a9dbdff5d7ea61ff412e5fb7f510972aad", "tree": "1dc424e41913cc598411bb24a49ab56b5b043d3c", "parents": [ "d0916f36d27b643bca970f3645c38f44270c74ef" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Tue May 13 12:58:19 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Wed May 14 10:39:58 2014 +0700" }, "message": "Support any cpu register sequence in LoadArgRegs\n\nThe LoadArgRegs was designed only for case when\narg1.reg \u003c arg2.reg \u003c arg3.reg which is not true for x86_64 ABI.\nNow LoadArgRegs supports three args passed by any cpu register.\n\nChange-Id: I62f58c47ec12b8e3f8124724cb3b5371dde8173f\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" }, { "commit": "9bf549d472462e4d1888a97c218a8c26fe3bfefb", "tree": "5d45f342f51a44536f76c1ff9edf4bb33dbafcac", "parents": [ "d0916f36d27b643bca970f3645c38f44270c74ef" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Mon May 12 11:14:46 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Wed May 14 10:36:03 2014 +0700" }, "message": "x86_64: Handle UnsafeGet/Put equal to x86\n\nThis patch extends \"Handle x86_64 architecture equal to x86\"\nand covers UnsafeGet/UnsafePut.\n\nChange-Id: Ib07cfc217c7825cff0b49cfbb9151452d62b1b68\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" }, { "commit": "9b9dec8bbcb812315eb0b68b3465c6c567f09527", "tree": "f932bc2f8e60cf2aceb71c48cbb580460712a2cf", "parents": [ "d0916f36d27b643bca970f3645c38f44270c74ef" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue May 13 19:01:42 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue May 13 19:01:42 2014 -0700" }, "message": "ART: Fix ARM dmb placement in monitor-exit\n\nThis moves the dmb in quick-compiled monitor-exit before the str\nperfoming the unlock.\n\nChange-Id: I231f98ff21eb7bac45b4a1b7ff57316deeb858cc\n" }, { "commit": "20cdc069f06f34828e51bcf89597bebe5df445d5", "tree": "916f48e3aa5c688fb5b0642f4a6963f595b64a93", "parents": [ "b720c4b7c6e484c9d0740d805c8d7c3dbeb2a545", "d5185344e19d9feb7ac268369e0af6a467d1cb48" ], "author": { "name": "Kenny Root", "email": "kroot@google.com", "time": "Tue May 13 22:03:04 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 13 22:03:05 2014 +0000" }, "message": "Merge \"Changes for vogar compatibility\"" }, { "commit": "d5185344e19d9feb7ac268369e0af6a467d1cb48", "tree": "bf5e7174ff631a86b5776ff6ddfa0dfa9de810fb", "parents": [ "a47dcbf4bc226b5bbf30618fc052e7c79672af7a" ], "author": { "name": "Kenny Root", "email": "kroot@google.com", "time": "Tue May 13 14:47:05 2014 -0700" }, "committer": { "name": "Kenny Root", "email": "kroot@google.com", "time": "Tue May 13 14:47:11 2014 -0700" }, "message": "Changes for vogar compatibility\n\nMake sure dex2oat can make an image with an empty list of image_classes.\nAdd in some checks to make sure that no bad arguments sneak into\nCompilerDriver.\n\nIf we\u0027re not on the ART_TARGET, we should check for the \"hostdex\"\nversions of the libraries to substitute in our libart version.\n\nChange-Id: I5e8485c6089d25664492f0217b43ef64ca84c061\n" }, { "commit": "eb8167a4f4d27fce0530f6724ab8032610cd146b", "tree": "bcfeaf13ad78f2dd68466bbd0e20c71944f7e854", "parents": [ "6fb66a2bc4e1c0b7931101153e58714991237af7" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed May 07 15:43:14 2014 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue May 13 14:45:54 2014 -0700" }, "message": "Add Handle/HandleScope and delete SirtRef.\n\nDelete SirtRef and replaced it with Handle. Handles are value types\nwhich wrap around StackReference*.\n\nRenamed StackIndirectReferenceTable to HandleScope.\n\nAdded a scoped handle wrapper which wraps around an Object** and\nrestores it in its destructor.\n\nRenamed Handle::get -\u003e Get.\n\nBug: 8473721\n\nChange-Id: Idbfebd4f35af629f0f43931b7c5184b334822c7a\n" }, { "commit": "9ee801f5308aa3c62ae3bedae2658612762ffb91", "tree": "86ed7ec36fe4a06bcc0b37df6661ac112888c0f6", "parents": [ "cd6e04f738ee17b3e8ec51c1f14d636fa2a89a55" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Mon May 12 11:31:37 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Wed May 14 00:40:57 2014 +0700" }, "message": "Add x86_64 code generation support\n\nUtilizes r0..r7 in register allocator, implements spill/unsill\ncore regs as well as operations with stack pointer.\n\nChange-Id: I973d5a1acb9aa735f6832df3d440185d9e896c67\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" }, { "commit": "ad930da1d67968600aab8441c24f5c4cc6e001bd", "tree": "8ce7f544da7b4b0be26d19e85c70e2861b068da1", "parents": [ "6f2b602999a9b5253de98e4c8749f821b0046ac2", "7624d25dad2d1ba25969ae704fccf68649103ae5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 13 15:56:12 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 13 15:56:14 2014 +0000" }, "message": "Merge \"Move quick frame info to OatQuickMethodHeader.\"" }, { "commit": "7624d25dad2d1ba25969ae704fccf68649103ae5", "tree": "de72194b76a4e23e0b15ec4085447ae7e4425815", "parents": [ "e1910f1d802dff79bba5ef61e1c4fd0b95f6e5b0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 02 14:40:15 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 13 11:43:22 2014 +0100" }, "message": "Move quick frame info to OatQuickMethodHeader.\n\nRename OatMethodHeader to OatQuickMethodHeader, move frame\ninfo from OatMethodOffsets to OatQuickMethodHeader. Retrieve\nthe info from other places for non-quick methods (portable\ncompiled bytecode or jni stub, generic jni, runtime,\nabstract and proxy).\n\nThis change has a libcore/ companion CL\n \"Remove ArtMethod\u0027s quick fields for frame size and spills.\"\n https://android-review.googlesource.com/94164\n\nBug: 11767815\nChange-Id: I0e31a7875d76732e1ec479c86b9b5ca01203507f\n" }, { "commit": "622d9c31febd950255b36a48b47e1f630197c5fe", "tree": "8a7f14ce3c6c087955ad5fe91a3ce7d5b5a82461", "parents": [ "98a8a542f95e41c09d214a329a940b270f08f5b3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 12 16:11:02 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 13 09:06:14 2014 +0100" }, "message": "Add loop recognition and CFG simplifications in new compiler.\n\nWe do three simplifications:\n- Split critical edges, for code generation from SSA (new).\n- Ensure one back edge per loop, to simplify loop recognition (new).\n- Ensure only one pre header for a loop, to simplify SSA creation (existing).\n\nChange-Id: I9bfccd4b236a00486a261078627b091c8a68be33\n" }, { "commit": "3ec5da20f27da3bb8cea7ae29538c30c4b1549b4", "tree": "bb36ce97e41a5d1927525f6710bd145ad324751e", "parents": [ "048b5d0fb1643316da5b666dea9e98c954626200" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 12 18:43:28 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 12 18:43:28 2014 -0700" }, "message": "ART: Fix typo in ThreadOffset modification\n\nChange-Id: Ifc3bd44a2a8442dcc242f4abcb17ae2acbc3b4e7\n" }, { "commit": "2f244e9faccfcca68af3c5484c397a01a1c3a342", "tree": "2a67c935f90e9c7c1cdf55d7d3c22cfbacab2be6", "parents": [ "e920cfd076f8cc806818bc115690c45289ed742c" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu May 08 03:35:25 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 12 17:34:19 2014 -0700" }, "message": "ART: Add more ThreadOffset in Mir2Lir and backends\n\nThis duplicates all methods with ThreadOffset parameters, so that\nboth ThreadOffset\u003c4\u003e and ThreadOffset\u003c8\u003e can be handled. Dynamic\nchecks against the compilation unit\u0027s instruction set determine\nwhich pointer size to use and therefore which methods to call.\n\nMethods with unsupported pointer sizes should fatally fail, as\nthis indicates an issue during method selection.\n\nChange-Id: Ifdb445b3732d3dc5e6a220db57374a55e91e1bf6\n" }, { "commit": "0c5e8417a1e82f6e31fbfc33be7e64d9073d6ef4", "tree": "9ec318c4a117d02a8276d25c0451ed148dbb4767", "parents": [ "9757e3d7488d88a27dc33331d4c7242e6092e739", "ba57451494946a128703e1cbd8bf5969ee8dc598" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 12 22:23:15 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 12 22:23:15 2014 +0000" }, "message": "Merge \"Quick compiler: fix compile-time perf regression\"" }, { "commit": "ba57451494946a128703e1cbd8bf5969ee8dc598", "tree": "b2f4702946b6f5feb7f59bac94debe3508c18149", "parents": [ "e1910f1d802dff79bba5ef61e1c4fd0b95f6e5b0" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 12 15:13:16 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 12 15:13:16 2014 -0700" }, "message": "Quick compiler: fix compile-time perf regression\n\nThe recent changes to the temp register liveness tracking\nintroduced a measureable compile-time performance regression.\nThis CL cleans it up.\n\nChange-Id: Id698b93e957f0ecab7ddfab94727f85e49cf10cf\n" }, { "commit": "7e0a8b49ecb4946db455027844f33efbfb2bd1a4", "tree": "55e3bdb3dc00954f263d5d7125ccf47cbe55a5b2", "parents": [ "b170b3e89e717c2d84a3ee7987f7460520fb9e17", "0f89dac7336251f7921621a926319d461837840f" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 12 18:50:14 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 12 18:50:15 2014 +0000" }, "message": "Merge changes Icf9afbab,If2409101\n\n* changes:\n AArch64: Fix the usage of IP0, IP1 as temporary registers\n AArch64: Fix the usage of Thread Register for arm64\n" }, { "commit": "0dc242d6fc1254e6ca1c31e08e612bbf45644b17", "tree": "a3389b2a7642745cd71843e903a77ea4282be284", "parents": [ "6663c90d2f94b0035fabcaee1f26fd840c9f9161" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 12 16:22:14 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 12 16:48:58 2014 +0100" }, "message": "Avoid unnecessary copy/load in EvalLoc() and LoadValue().\n\nEvalLoc()/EvalLocWide() are used to prepare a register where\na value is subsequently stored, so they shouldn\u0027t copy the\nold value to the new register for register class mismatch.\n\nThe only exception where we actually need a copy is\nLoadValue()/LoadValueWide(), so we inline the old code that\nmakes the copy there. We also avoid loading inexpensive\nconstants when the value is already in the register.\n\nChange-Id: I07519e9d4d9b3f7272233d196435f3035e4a3ca9\n" }, { "commit": "d111c6eeb01955964d9c7f68126adcb1e1824ab3", "tree": "0feb1c424f517a7750375971c3605db16212c110", "parents": [ "e1910f1d802dff79bba5ef61e1c4fd0b95f6e5b0" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sun May 11 21:09:53 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 12 05:04:46 2014 -0700" }, "message": "Quick compiler: RegStorage tweak\n\nPreviously, the RegStorage struct allowed for up to 32 physical\nregisters per register class. Although this is sufficient to\nhandle instruction encodings for all targets, some targets may\nre-use the register number encoding for different physical elements.\n\nFor example, Arm64 uses register encoding 0x1f for both the stack\npointer and the zero register. This change adds a bit to the low\nregister number, allowing 0..63. Targets can use this extra\nencoding space to differentiate between multiple uses of the same\nencoding pattern.\n\nChange-Id: I11f2ebbce8865a08627eef5868bb51fae6421c33\n" }, { "commit": "e1910f1d802dff79bba5ef61e1c4fd0b95f6e5b0", "tree": "e86bcfc81a26b452e105f8431db34a06a22d36aa", "parents": [ "f92a45609352fb1dc3460a07d83284b353270221", "30adc7383a74eb3cb6db3bf42cea3a5595055ce1" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sun May 11 15:43:27 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Sun May 11 15:43:28 2014 +0000" }, "message": "Merge \"Quick compiler: Fix liveness tracking\"" }, { "commit": "30adc7383a74eb3cb6db3bf42cea3a5595055ce1", "tree": "923d05c55cd5fd9b441bc7ee6737c0831986546f", "parents": [ "a77530fd7f13971574c458a987d7025a44a3b5b4" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri May 09 15:10:18 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat May 10 22:04:57 2014 -0700" }, "message": "Quick compiler: Fix liveness tracking\n\nRework temp register liveness tracking to play nicely with aliased\nphysical registers, and re-enable liveness tracking optimization.\n\nAdd a pair of x86 utility routines that act like UpdateLoc(),\nbut only show in-register live temps if they are of the expected\nregister class.\n\nChange-Id: I92779e0da2554689103e7488025be281f1a58989\n" }, { "commit": "90cf3eefb4cd4dbd7ccd514738055b4d193981fe", "tree": "90a205aac6c6c734bb9e980b592f15a6fbb0413f", "parents": [ "5bd9f09a3645f6f82d31af70d04638a6256de4b7", "69f08baaa4b70ce32a258f3da43cf12f2a034696" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 09 15:19:47 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 09 15:19:47 2014 +0000" }, "message": "Merge \"Clean up ScopedArenaAllocatorAdapter.\"" }, { "commit": "69f08baaa4b70ce32a258f3da43cf12f2a034696", "tree": "33f8b5a6675ef8b3b1755fa8e88f6b7dae33b857", "parents": [ "18694f430b1e499954e5e4fcdbd6ac07a07763ae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Apr 11 12:28:11 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 09 15:38:54 2014 +0100" }, "message": "Clean up ScopedArenaAllocatorAdapter.\n\nMake the adapter equality-comparable, define aliases for\ncontainers using the adapter and use those aliases.\nFix DebugStackIndirectTopRefImpl assignment.\n\nChange-Id: I689aa8a93d169f63a659dec5040567d7b1343277\n" }, { "commit": "0f89dac7336251f7921621a926319d461837840f", "tree": "febe5ec75aca80018b43a64df84995220f92c1ef", "parents": [ "63206f3038d3d6e1cb24166726613808a4b0ad8c" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu May 08 13:52:53 2014 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri May 09 14:01:28 2014 +0100" }, "message": "AArch64: Fix the usage of IP0, IP1 as temporary registers\n\nThis patch fixes the usage of temporary registers by using VIXL\u0027s\nUseScratchRegisterScope. For the primitives used by the trampoline\ncompiler we explicitly exclude IP0, IP1 from the temporary list.\n\nChange-Id: Icf9afbabd93214302891ddd536ce03a9c181463b\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "63206f3038d3d6e1cb24166726613808a4b0ad8c", "tree": "08058c7cf718eac9c87e32436f87cbde04ab7ff0", "parents": [ "5bd9f09a3645f6f82d31af70d04638a6256de4b7" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Wed May 07 18:40:49 2014 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri May 09 14:01:28 2014 +0100" }, "message": "AArch64: Fix the usage of Thread Register for arm64\n\nThis patch cleans-up the usage of x18 as TR for Arm64. As described in\nthe Arm64 Procedure Call Standard, the recommended usage for x18 is to\ncarry inter-procedural state (i.e. ART thread information).\n\nHowever, since x18 is a temporary register there is no guarantee that on\ncalls to external functions x18 is preserved. Thus on JNI calls we need\nto save and restore x18 before coming back to managed runtime. For the\nJNI compiler trampoline we move x18 (temporary register - caller saved)\nto x19 (ETR, callee saved) before calling into native code, and\nrestore it on the way back.\n\nChange-Id: If24091018d640027a497517a9238bf4a80d013aa\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "674744e635ddbdfb311fbd25b5a27356560d30c3", "tree": "c61c3979cbb25bda24954d41f19c64521fbe3b9d", "parents": [ "18694f430b1e499954e5e4fcdbd6ac07a07763ae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 24 15:18:26 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 08 18:45:59 2014 +0100" }, "message": "Use atomic load/store for volatile IGET/IPUT/SGET/SPUT.\n\nBug: 14112919\nChange-Id: I79316f438dd3adea9b2653ffc968af83671ad282\n" }, { "commit": "8b1f6050ae4f6291d0ed082cf5d2efed2da0eef4", "tree": "9bc9bd3dd6bfbd8a092a67f47c2f9259fdae446e", "parents": [ "b60717ae27a33c8a48aeade62e84dcaf27f39ecf", "9ed427724a18dc24f9eb2ddf39e4729bea203c2e" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 08 01:31:44 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 08 01:31:44 2014 +0000" }, "message": "Merge \"X86: EmitArrayImm shouldn\u0027t truncate to 16 bits\"" }, { "commit": "e45fb9e7976c8462b94a58ad60b006b0eacec49f", "tree": "1d8139f92fb127fc931c6e5c9ca2ed2c8dc871b9", "parents": [ "410d87ff51e9432768924d2f294592818f93c244" ], "author": { "name": "Matteo Franchin", "email": "matteo.franchin@arm.com", "time": "Tue May 06 10:10:30 2014 +0100" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed May 07 14:54:16 2014 -0700" }, "message": "AArch64: Change arm64 backend to produce A64 code.\n\nThe arm backend clone is changed to produce A64 code. At the moment\nthis backend can only compile simple methods (both leaf and non-leaf).\n\nMost of the work on the assembler (assembler_arm64.cc) has been done.\nSome work on the LIR generation layer (functions such as OpRegRegImm\n\u0026 friends) is still necessary. The register allocator still needs to\nbe adapted to the A64 instruction set (it is mostly unchanged from\nthe arm backend). Offsets for helpers in gen_invoke.cc still need to\nbe changed to work on 64-bit.\n\nChange-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921\n" }, { "commit": "9ed427724a18dc24f9eb2ddf39e4729bea203c2e", "tree": "a8e514e25448b48d77310ddc95b41c708b98a6d2", "parents": [ "f23a719218ffaa37a85482e40509e62275554774" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 07 17:26:12 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 07 17:26:12 2014 -0400" }, "message": "X86: EmitArrayImm shouldn\u0027t truncate to 16 bits\n\nThe code in X86Mir2Lir::EmitArrayImm() always truncates the immediate\nvalue to 16 bits. This can\u0027t be right. The code in EmitImm() will check\nthe expected immediate size from the entry.\n\nChange-Id: I75b3b96e41777838b0f243d65f3f2ded2e1dbdd2\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "410d87ff51e9432768924d2f294592818f93c244", "tree": "dc1de40eb82349e3b70cafe6c5f48021fed93ee9", "parents": [ "052a647973b590c9d5007a2e16f313f4e32a70bd", "3bf7c60a86d49bf8c05c5d2ac5ca8e9f80bd9824" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 07 17:31:25 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 07 17:31:26 2014 +0000" }, "message": "Merge \"Cleanup ARM load/store wide and remove unused param s_reg.\"" }, { "commit": "052a647973b590c9d5007a2e16f313f4e32a70bd", "tree": "fb2e79844d15b80da9af520c2983921c79b55fd1", "parents": [ "221b86d96f6e1971d24e3d6a283352c58cedbd32", "9e06c8cd4a2e1471754470e09aaab63c0795b4af" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Wed May 07 15:17:09 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 07 15:17:10 2014 +0000" }, "message": "Merge \"AArch64: Add fake arm64 backend, and disable it by method filter.\"" }, { "commit": "221b86d96f6e1971d24e3d6a283352c58cedbd32", "tree": "f80439dc10bf971004472a7aa609aa0a9cff65eb", "parents": [ "60280e50c1ef4a7ef286670975a81f8384138f42", "b5c9b4008760c9042061490f22aaff990ed04c9a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 07 15:15:46 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 07 15:15:46 2014 +0000" }, "message": "Merge \"ART: BitVector and Optimization changes\"" }, { "commit": "3bf7c60a86d49bf8c05c5d2ac5ca8e9f80bd9824", "tree": "03c0831585d4477eae4a3b906b256389274e8142", "parents": [ "f23a719218ffaa37a85482e40509e62275554774" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 07 14:55:43 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 07 15:11:48 2014 +0100" }, "message": "Cleanup ARM load/store wide and remove unused param s_reg.\n\nUse a single LDRD/VLDR instruction for wide load/store on\nARM, adjust the base pointer if needed. Remove unused\nparameter s_reg from LoadBaseDisp(), LoadBaseIndexedDisp()\nand StoreBaseIndexedDisp() on all architectures.\n\nChange-Id: I25a9a42d523a68addbc11abe44ddc55a4401df98\n" }, { "commit": "9e06c8cd4a2e1471754470e09aaab63c0795b4af", "tree": "c8f7889b9740c9189ac0f11720ff9e18a41b1102", "parents": [ "7189fee4268c70d7ed0151e988ff7c7cd85f2a30" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Tue May 06 18:06:07 2014 +0100" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Wed May 07 15:06:29 2014 +0100" }, "message": "AArch64: Add fake arm64 backend, and disable it by method filter.\n\nJust create an ArmCodeGenerator for arm64, but currently no code will\nbe generated for arm64.\n\nThe method filter can:\n1. Skip methods with unsupported prototype.\n2. Skip methods with unsupported dalvik byte code.\n3. Skip methods with invocation to unsupported prototype.\n\nThese are temporary codes and should be removed later. But with this\npatch, it won\u0027t break anything when we merge partly implemented arm64\nbackend later.\n\nChange-Id: Ib9180d7b8a978f0a5ebaf6b4893e7e3724897113\n" }, { "commit": "99380ed2f0f108a3110a3243e57e9863e74095cb", "tree": "4703e9056f1b63a967e09a8331d9c3ecd1cca9e9", "parents": [ "f23a719218ffaa37a85482e40509e62275554774" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 07 07:53:06 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 07 07:53:06 2014 -0400" }, "message": "ART: Ensure X86 OpRegCopyWide preserves src\n\nX86Mir2Lir::OpRegCopyWide will clobber r_src if it is assigning a value\nin an XMM register to a pair of GPRs. This change introduces a\ntemporary to preserve the input value.\n\nChange-Id: I02af5174007c9572e597f8efb0da34f21882a3a8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "f23a719218ffaa37a85482e40509e62275554774", "tree": "d04b4d12264758169a7d6c8ede2427f1078249f3", "parents": [ "290fda3acf3d9ce60f7ac3903fabfb01d3521d0f", "804d09372cc3d80d537da1489da4a45e0e19aa5d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 07 09:33:54 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 07 09:33:54 2014 +0000" }, "message": "Merge \"Build live-in, live-out and kill sets for each block.\"" }, { "commit": "804d09372cc3d80d537da1489da4a45e0e19aa5d", "tree": "b226350fdf3dc0c55a11e1615010c8475f167f90", "parents": [ "0095e0b8380a8802f40a21928800b9df6e11f1d7" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 02 08:46:00 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 07 10:32:11 2014 +0100" }, "message": "Build live-in, live-out and kill sets for each block.\n\nThis information will be used when computing live ranges of\ninstructions.\n\nChange-Id: I345ee833c1ccb4a8e725c7976453f6d58d350d74\n" }, { "commit": "290fda3acf3d9ce60f7ac3903fabfb01d3521d0f", "tree": "e09287b2b04275a2d2e8745c2b4426b764d87bce", "parents": [ "91152bc2ab6e60add80dd017e30e57dce40a8ae0", "455759b5702b9435b91d1b4dada22c4cce7cae3c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 07 09:29:14 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 07 09:29:14 2014 +0000" }, "message": "Merge \"Remove LoadBaseDispWide and StoreBaseDispWide.\"" }, { "commit": "91152bc2ab6e60add80dd017e30e57dce40a8ae0", "tree": "fb85fa9507464242bb9939223b17d60048e87517", "parents": [ "7189fee4268c70d7ed0151e988ff7c7cd85f2a30", "f8c762b8cbd4a223c697d7e7bdb976fb39224cb8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 07 09:18:12 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 07 09:18:13 2014 +0000" }, "message": "Merge \"ART: ChildBlockIterator Implementation\"" }, { "commit": "455759b5702b9435b91d1b4dada22c4cce7cae3c", "tree": "73df437e7b8e1ca1b78be8d7fb2d38fec01b9dee", "parents": [ "7189fee4268c70d7ed0151e988ff7c7cd85f2a30" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 06 20:49:36 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 07 10:10:19 2014 +0100" }, "message": "Remove LoadBaseDispWide and StoreBaseDispWide.\n\nJust pass k64 or kDouble to non-wide versions.\n\nChange-Id: I000619c3b78d3a71db42edc747c8a0ba1ee229be\n" }, { "commit": "7189fee4268c70d7ed0151e988ff7c7cd85f2a30", "tree": "88c353fd9752d7deb4afb914e5444197fa85e442", "parents": [ "68f8e40c90b323346c15d3f54f5884ef7e7af8c5", "43ec8737d8356dbff0a90bee521fb0e73438da47" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Tue May 06 23:46:11 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 23:46:11 2014 +0000" }, "message": "Merge \"AArch64: Added arm64 quick backend as an arm clone.\"" }, { "commit": "43ec8737d8356dbff0a90bee521fb0e73438da47", "tree": "50f1d735b006b8aaed1570da696332d285b643e6", "parents": [ "069849e1469b55984d9e208b2ada345aa57f8947" ], "author": { "name": "Matteo Franchin", "email": "matteo.franchin@arm.com", "time": "Mon Mar 31 15:00:14 2014 +0100" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue May 06 16:43:26 2014 -0700" }, "message": "AArch64: Added arm64 quick backend as an arm clone.\n\nCreated a new directory arm64 under compiler/dex/quick which contains\na copy of the 32-bit arm backend. In following CLs, this code will\nbe replaced/modified to support Aarch64.\n\nChange-Id: I06c468db8d588e339eecf4d7d85276d5e334a17a\n" }, { "commit": "72d32629303f8f39362a4099481f48646aed042f", "tree": "0ff613168c3bf2e12799594c9211f9a1694119e2", "parents": [ "47ebd77a6d249403a34d242908749b7446da2a82" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue May 06 16:20:11 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue May 06 16:23:19 2014 -0700" }, "message": "Give Compiler a back reference to the driver.\n\nThe compiler driver is a single object delegating work to the compiler, rather\nthan passing it through to every Compiler call make it a member of Compiler so\nthat it maybe queried. This simplifies the Compiler API and makes the\nrelationship to CompilerDriver more explicit.\nRemove reference arguments that contravene code style.\n\nChange-Id: Iba47f2e3cbda679a7ec7588f26188d77643aa2c6\n" }, { "commit": "47ebd77a6d249403a34d242908749b7446da2a82", "tree": "3478bb35ad26144d4247f1a3baed1139c9bbb39f", "parents": [ "484f4dadeef13fd7c0459e0c6934f53ba914e3a4", "752e205de95ca9d4f4e825173a3cefd831a3b933" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue May 06 22:13:47 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 22:13:47 2014 +0000" }, "message": "Merge \"ART: Improve fused compare long branch\"" }, { "commit": "80475df914f9dbdbb1f4b42e87e75d375d50a629", "tree": "db40a29f8c2a8d60fdc405ac4aa28d8c4990dc96", "parents": [ "fc733a14e2b0eaf4ac0f386ac784706bf66de16c", "0add77a86599260aba3ea4b56e9db3da6bb881a8" ], "author": { "name": "Bill Buzbee", "email": "buzbee@android.com", "time": "Tue May 06 21:56:18 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 21:56:18 2014 +0000" }, "message": "Merge \"ART: Ensure use counts updated when adding SSA reg\"" }, { "commit": "1f1d2513a11eaaa59601d7599ac2e80ddfa1bcf5", "tree": "6c79b4c5babe26d3ae83c06ae3b7119293315359", "parents": [ "9780f97d4864f33150407707e6ca09a8a7a20914", "660188264dee3c8f3510e2e24c11816c6b60f197" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue May 06 21:39:56 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 21:39:56 2014 +0000" }, "message": "Merge \"ART: Use utils.h::RoundUp instead of explicit bit-fiddling\"" }, { "commit": "b5c9b4008760c9042061490f22aaff990ed04c9a", "tree": "c3fc539b056dadcad2c47c9899caeecc5f2d00ae", "parents": [ "36b65964d128471d917c2efc69c81bc50ef9360b" ], "author": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Wed Apr 30 14:52:00 2014 -0700" }, "committer": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Tue May 06 13:47:51 2014 -0700" }, "message": "ART: BitVector and Optimization changes\n\n- The BitVector has a function SameBitsSet that is a bit upside down\n - This patch fixes it.\n\n- Two optimizations are fixed also:\n - The null check pass uses now same bits set instead of equal due to a\n subsequent change that will make it not always the case that the\n compared bitvectors be of the same size.\n - The fused optimization supposes a predecessor will have an instruction.\n\nChange-Id: I9ef1c793964b18dc0f47baf9d1f361448bb053a3\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\n" }, { "commit": "99b0578036179849aa9fb7b8ef378bd20fabc71e", "tree": "1e71ef33877bc01b22405d712f5ca4d9da19e178", "parents": [ "36b65964d128471d917c2efc69c81bc50ef9360b", "5cd33753b96d92c03e3cb10cb802e68fb6ef2f21" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Tue May 06 19:46:11 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 19:46:11 2014 +0000" }, "message": "Merge \"Handle implicit stack overflow without affecting stack walks\"" }, { "commit": "f8c762b8cbd4a223c697d7e7bdb976fb39224cb8", "tree": "2dd352e29e243027472a74b7996d53bed24f8811", "parents": [ "36b65964d128471d917c2efc69c81bc50ef9360b" ], "author": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Fri May 02 12:54:37 2014 -0700" }, "committer": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Tue May 06 12:18:00 2014 -0700" }, "message": "ART: ChildBlockIterator Implementation\n\n- Added the API to be able to walk through a BasicBlock\u0027s children directly.\n- When calling Reset(GrowableArray*), there is an assignment to the g_list_\n member. This is not possible with the g_list_ being const.\n\nChange-Id: I25d06484fd93848d80ccf96a1324058370b2ee46\nSigned-Off-By: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\n" }, { "commit": "36b65964d128471d917c2efc69c81bc50ef9360b", "tree": "485c2883d04d23c63f983305cb4bbdbc0e499a85", "parents": [ "0095e0b8380a8802f40a21928800b9df6e11f1d7", "2637f2e9bf4fc5591994b7c0158afead88321a7c" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue May 06 17:15:00 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 17:15:00 2014 +0000" }, "message": "Merge \"ART: Update and correct assemble_x86.cc\"" }, { "commit": "2637f2e9bf4fc5591994b7c0158afead88321a7c", "tree": "f0012a9d263127dd356cd39e1a4368fc6c773730", "parents": [ "66762055847a40fe4454782826d2bb7a4ea9e316" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 30 10:10:47 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue May 06 12:38:51 2014 -0400" }, "message": "ART: Update and correct assemble_x86.cc\n\nCorrect the definition of some X86 instructions in the file.\nAdd some new instructions and the code to emit them properly.\n\nAdded EmitMemCond()\n\nChange-Id: Icf4b70236cf0ca857c85dcb3edb218f26be458eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "752e205de95ca9d4f4e825173a3cefd831a3b933", "tree": "fbcf4e66b55bf1b7ca9585c2a3cb4b9da4d70319", "parents": [ "6ab0d9fe1abec72f5fe4841a8124fadf55400977" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu May 01 10:19:04 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue May 06 09:09:41 2014 -0400" }, "message": "ART: Improve fused compare long branch\n\nThe code generated by a fused compare long with an immediate value is\nmuch longer than comparing to a runtime value. Rewrite the code to\nimprove it.\n\nThe special cases are \u003d\u003d or !\u003d to 0, and whether the source is a\ntemporary value or not. Try to handle all of these well. For all\nexcept \u003d\u003d and !\u003d, we can use a \u0027cmp\u0027 instruction for the upper word, in\norder to set the carry flag properly, rather than a \u0027sub\u0027 into a temp.\n\nAlso, we have to handle the \u003c\u003d and \u003e cases properly, in order to get the\ncorrect code generated, in the same manner as\nX86Mir2Lir::GenFusedLongCmpBranch().\n\nChange-Id: Ic29bf89ff2c06916d7fc996926997888ea013ba7\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "0095e0b8380a8802f40a21928800b9df6e11f1d7", "tree": "08fe88a88345716ea6468682c18903440a890525", "parents": [ "6ab0d9fe1abec72f5fe4841a8124fadf55400977", "89fde26f586883e04d295d6e30954cb5a0dc37bf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 06 12:52:50 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 12:52:51 2014 +0000" }, "message": "Merge \"ART: Add a last item in the MIROptimizationFlagPositions enumeration\"" }, { "commit": "0add77a86599260aba3ea4b56e9db3da6bb881a8", "tree": "df2129b88907d4f9739ab93907f2e10803fdd80b", "parents": [ "66762055847a40fe4454782826d2bb7a4ea9e316" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon May 05 22:28:55 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue May 06 07:18:03 2014 -0400" }, "message": "ART: Ensure use counts updated when adding SSA reg\n\nEnsure that matching data structures are updated when adding SSA\nregisters late in the compile.\n\nChange-Id: I8e664dddf52c1a9095ba5b7a8df84e5a733bbc43\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "6ab0d9fe1abec72f5fe4841a8124fadf55400977", "tree": "9ac3fca744fe35496f4f0fa4a01c45104ce118cc", "parents": [ "2a12ad460af139a03c3e9bf5fc7886a7521b333e", "f529d776ca9f48b115714f6c79677755ecc37d24" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 06 08:20:55 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 06 08:20:56 2014 +0000" }, "message": "Merge \"Make all registers available when allocating an output register.\"" }, { "commit": "660188264dee3c8f3510e2e24c11816c6b60f197", "tree": "cd18ee6c9328650110f06d14905468ea320342b4", "parents": [ "2a12ad460af139a03c3e9bf5fc7886a7521b333e" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 05 20:47:19 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 05 20:47:19 2014 -0700" }, "message": "ART: Use utils.h::RoundUp instead of explicit bit-fiddling\n\nChange-Id: I249a2cfeb044d3699d02e13d42b8e72518571640\n" }, { "commit": "f29a4244bbc278843237f0ae242de077e093b580", "tree": "a7364eb7915712e022cd4dcf67b18e2ecf31d7e3", "parents": [ "fac805ba18254db0cb84661dc2085763730e95e7" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Mon May 05 20:28:47 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Tue May 06 08:14:06 2014 +0700" }, "message": "x86_64: Fix frame size calculation for 64-bit\n\nCalculate frame size in the same way as calculated in patch\n\"64bit changes to the stack walker for the Quick ABI\"\n\nChange-Id: I8c2458f5973536a84f3fd6ad56167b5cfafa9ab4\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" }, { "commit": "0b8027003514c4fa6a850e5087076e991daaf4c3", "tree": "5706dcea2be54aa41001d816f951104923248040", "parents": [ "680d662800eb98c219d80cfc4b9285f2ac2ecfad", "37498b6719347190f45472ad44ea21de563585eb" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 05 21:07:45 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 05 21:07:45 2014 +0000" }, "message": "Merge \"x86_64: Fix Array::DataOffset in calls\"" }, { "commit": "37498b6719347190f45472ad44ea21de563585eb", "tree": "17d7062e614ae709ac5156ceb1292a44e88ddd64", "parents": [ "eafef7db77cfbe6bc05d9b07221c198bc8ceaa8a" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Mon May 05 20:33:38 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Tue May 06 03:14:52 2014 +0700" }, "message": "x86_64: Fix Array::DataOffset in calls\n\nCalculates offset using utility function\n\nChange-Id: I19339537f4458dcae931897f4ee282f5c40746d2\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" }, { "commit": "5cd33753b96d92c03e3cb10cb802e68fb6ef2f21", "tree": "b2217cb48e1f1db1aae7a92f8d5dbac5f2d95603", "parents": [ "8ea5baa10b04e9dbd0f0cf14b0358fe8b956bb2e" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Tue Apr 15 15:57:58 2014 -0700" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon May 05 12:44:15 2014 -0700" }, "message": "Handle implicit stack overflow without affecting stack walks\n\nThis changes the way in which implicit stack overflows are handled\nto satisfy concerns about changes to the stack walk code.\n\nInstead of creating a gap in the stack and checking for it in\nthe stack walker, use the ManagedStack infrastructure to concoct\nan invisible gap that will never be seen by a stack walk.\n\nAlso, this uses madvise to tell the kernel that the main stack\u0027s\nprotected region will probably never be accessed, and instead\nof using memset to map the pages in, use memcpy to read from\nthem. This will save 32K on the main stack.\n\nAlso adds a \u0027signals\u0027 verbosity level as per a review request.\n\nBug: 14066862\nChange-Id: I5257305feeaea241d11e6aa6f021d2a81da20b81\n" }, { "commit": "8ea5baa10b04e9dbd0f0cf14b0358fe8b956bb2e", "tree": "f12adc6e4b395f8c85927e5ef9b203aa5b62d1e9", "parents": [ "7c6247134c734f7ad205c6065f71cec3dbbf7204", "091cc408e9dc87e60fb64c61e186bea568fc3d3a" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 05 16:58:01 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 05 16:58:01 2014 +0000" }, "message": "Merge \"Quick compiler: allocate doubles as doubles\"" }, { "commit": "091cc408e9dc87e60fb64c61e186bea568fc3d3a", "tree": "b4c19f918a083768b9d940afbb34f9fa388d4e95", "parents": [ "eafef7db77cfbe6bc05d9b07221c198bc8ceaa8a" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Mar 31 10:14:40 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 05 09:55:24 2014 -0700" }, "message": "Quick compiler: allocate doubles as doubles\n\nSignificant refactoring of register handling to unify usage across\nall targets \u0026 32/64 backends.\n\nReworked RegStorage encoding to allow expanded use of\nx86 xmm registers; removed vector registers as a separate\nregister type. Reworked RegisterInfo to describe aliased\nphysical registers. Eliminated quite a bit of target-specific code\nand generalized common code.\n\nUse of RegStorage instead of int for registers now propagated down\nto the NewLIRx() level. In future CLs, the NewLIRx() routines will\nbe replaced with versions that are explicit about what kind of\noperand they expect (RegStorage, displacement, etc.). The goal\nis to eventually use RegStorage all the way to the assembly phase.\n\nTBD: MIPS needs verification.\nTBD: Re-enable liveness tracking.\n\nChange-Id: I388c006d5fa9b3ea72db4e37a19ce257f2a15964\n" }, { "commit": "c45b8b582be5c98941ca3869fcdc9a08d520da41", "tree": "c84c980418c224dd317f2962fcfbd18d9785c3b0", "parents": [ "eafef7db77cfbe6bc05d9b07221c198bc8ceaa8a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sat May 03 01:39:59 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sat May 03 22:52:59 2014 -0700" }, "message": "Create stack traces in unstarted runtimes.\n\nUse to diagnose failed initialization in dex2oat of boot (-verbose:compiler).\nFix identity hashCode, ArtMethod.getMethodName, IntegralToString.convertInt and\nuse of Void when called from a unstarted runtime.\n\nChange-Id: I2d536174b59e2e5f19519f93fc6b5916652fb6cd\n" }, { "commit": "8cede9508666c53b116857563e433460daffe43f", "tree": "9527f3b02a98b648237c959e41136660918f0a28", "parents": [ "a54c22c0041306f6881694f4c305e655b10e37be", "b40c6a768aa8df4774d2a8c3ac7045237cc748cd" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri May 02 22:55:43 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 02 22:55:43 2014 +0000" }, "message": "Merge \"ART: Fix assembler_test to use ScratchFile\"" } ], "next": "29a2648821ea4d0b5d3aecb9f835822fdfe6faa1" }