)]}' { "log": [ { "commit": "e8861b30ac8b2b1ca49386f9c9218f1d6fedc511", "tree": "70ec1c5dc2b917211b9bf0428f2806694f725744", "parents": [ "3f4dcdf6c99f90a2301304d26ce29dc637b4be7f" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Fri Apr 18 17:06:15 2014 +0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Apr 25 10:42:13 2014 -0700" }, "message": "ART: Enables x86_64 disassembly\n\nThis patch\n (a) cuts a REX prefix from the instruction and\n (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes.\n\nChange-Id: I2674678224ca27746b33d4006ed38d497972309f\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "fba52f1b4bf753790c1d98265c4b0fabb54c7536", "tree": "a9feb49c87ae2ec5cde2dd45913840e1f9977ade", "parents": [ "9623c6668962559e818d1e7f05a58dcb96c71fa9" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Apr 15 15:41:47 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Thu Apr 17 13:17:30 2014 +0700" }, "message": "ART: Fixes an issue with REX prefix for instructions with no ModRM byte\n\nThere are instructions (such as push, pop, mov) in the x86 ISA\nthat encode first operands in their opcodes (opcode + reg).\nIn order to enable an extended 64bit registers (R9-R15) a special\nprefix REX.B should be emitted before such instructions.\n\nThis patch fixes the issue when REX.R prefix was emitted before\ninstructions with no MorRM byte. So, the REX-prefix was simply\nignored by CPU for those instructions whose operands are encoded\nin their opcodes.\n\nThis patch makes the jni_compiler_test passed with JNI compiler\nenabled for x86_64 target.\n\nChange-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "dd7624d2b9e599d57762d12031b10b89defc9807", "tree": "c972296737f992a84b1552561f823991d28403f0", "parents": [ "8464a64a50190c06e95015a932eda9511fa6473d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 17:43:00 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Apr 01 08:24:16 2014 -0700" }, "message": "Allow mixing of thread offsets between 32 and 64bit architectures.\n\nBegin a more full implementation x86-64 REX prefixes.\nDoesn\u0027t implement 64bit thread offset support for the JNI compiler.\n\nChange-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147\n" }, { "commit": "99ad7230ccaace93bf323dea9790f35fe991a4a2", "tree": "095705c674703953bf4c50f6a30a105420b770b5", "parents": [ "a9e3d2ccfdbf7f4c7b1508bcb2b774037399b1d4" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Feb 25 17:41:08 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Mar 26 16:20:09 2014 -0700" }, "message": "Relaxed memory barriers for x86\n\nX86 provides stronger memory guarantees and thus the memory barriers can be\noptimized. This patch ensures that all memory barriers for x86 are treated\nas scheduling barriers. And in cases where a barrier is needed (StoreLoad case),\nan mfence is used.\n\nChange-Id: I13d02bf3f152083ba9f358052aedb583b0d48640\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "38e12034f1ef2b32e98b6e49cb36b7cc37a7f1be", "tree": "9a879d4034bce742c8b5ef0680c2da2d8da5139d", "parents": [ "fb5b21d1d598b6b42e5d5ca1dac4a040832558fb" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:06:14 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:16:04 2014 -0700" }, "message": "x86-64 disassembler support.\n\nChange-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0\n" }, { "commit": "4028a6c83a339036864999fdfd2855b012a9f1a7", "tree": "c86f355cb39adc7a14469f0a4e5727623fbda443", "parents": [ "0b2b3dbaa3db62c0af0d2f23f6aa1c539afe7443" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Feb 19 20:06:20 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 20 15:46:42 2014 -0800" }, "message": "Inline x86 String.indexOf\n\nTake advantage of the presence of a constant search char or start index\nto tune the generated code.\n\nChange-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "614c2b4e219631e8c190fd9fd5d4d9cd343434e1", "tree": "8236046426615c78eb6b2f6c2ca29b63d5665d97", "parents": [ "6b3697fec487b355d107b693c965919bf5fff906" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Jan 28 17:05:21 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Feb 11 18:10:33 2014 -0800" }, "message": "Support to generate inline long to FP bytecodes for x86\n\nlong-to-float and long-to-double are now generated inline instead of calling\na helper routine. The conversion is done by using x87.\n\nChange-Id: I196e526afec1be212898baceca8527549c3655b6\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "2c498d1f28e62e81fbdb477ff93ca7454e7493d7", "tree": "94654433a4dae83ab75d432304dcc0358aefeb1c", "parents": [ "1dcff62155e8477eb114c8a86eb1beb0797ffc11" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Jan 29 16:02:57 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Feb 05 22:42:21 2014 -0800" }, "message": "Specializing x86 range argument copying\n\nThe ARM implementation of range argument copying was specialized in some cases.\nFor all other architectures, it would fall back to generating memcpy. This patch\nupdates the x86 implementation so it does not call memcpy and instead generates\nloads and stores, favoring movement of 128-bit chunks.\n\nChange-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "7ea5dafc81b2bba7cabad26130bb75dc8f709803", "tree": "dfd021549d31697d4c142699e38fb8fa00e64c58", "parents": [ "6e65720d99bd3387b72d528a46291f1ed8184ede", "4708dcd68eebf1173aef1097dad8ab13466059aa" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jan 28 00:29:31 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 28 00:29:31 2014 +0000" }, "message": "Merge \"Improve x86 long multiply and shifts\"" }, { "commit": "d3266bcc340d653e178e3ab9d74512c8db122eee", "tree": "1a3cf8b8e828994c57c533157bc1f84e50c24a14", "parents": [ "26a302b2bb07d754b958a4013116946fbbd78c62" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jan 24 12:55:31 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jan 24 14:38:53 2014 -0800" }, "message": "Reduce x86 sequence for GP pair to XMM\n\nAdded support for punpckldq which is useful for interleaving\n32-bit values from two xmm registers.\n\nThis new instruction is now used for transfers from GP pairs\nto XMM in order to reduce path length.\n\nChange-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "4708dcd68eebf1173aef1097dad8ab13466059aa", "tree": "92614e1fe36cccda1d2fd7c662c43482ec8bcc85", "parents": [ "a278ac31a1beeebd093ec64026d27a02fdc28807" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 22 09:05:18 2014 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 24 11:49:06 2014 -0800" }, "message": "Improve x86 long multiply and shifts\n\nGenerate inline code for long shifts by constants and do long\nmultiplication inline. Convert multiplication by a constant to a\nshift when we can. Fix some x86 assembler problems and add the new\ninstructions that were needed (64 bit shifts).\n\nChange-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2bf31e67694da24a19fc1f328285cebb1a4b9964", "tree": "e24b7ec3569ea26e91f1a10179b7d1912f594d7e", "parents": [ "3f5b42f1d31c877abca2571a51dd0a5055a9b94c" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 23 12:13:40 2014 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 24 10:01:41 2014 -0800" }, "message": "Improve x86 long divide\n\nImplement inline division for literal and variable divisors. Use the\ngeneral case for dividing by a literal by using a double length multiply\nby the appropriate constant with fixups. This is the Hacker\u0027s Delight\nalgorithm.\n\nChange-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "bd288c2c1206bc99fafebfb9120a83f13cf9723b", "tree": "a9f154c4338b888de313517e95ae6a7ee22e7f1f", "parents": [ "51f46ad5edd888b58d706569342c1a0f51e6ae15" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Dec 20 17:27:23 2013 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Jan 08 11:28:46 2014 -0800" }, "message": "Add conditional move support to x86 and allow GenMinMax to use it\n\nX86 supports conditional moves which is useful for reducing branchiness.\nThis patch adds support to the x86 backend to generate conditional reg\nto reg operations. Both encoder and decoder support was added for cmov.\n\nThe x86 version of GenMinMax used for generating inlined version Math.min/max\nhas been updated to make use of the conditional move support.\n\nChange-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "d19b55a05b52b7f7da9f894eba63ed03e2a62283", "tree": "06c50a4d0121eae129e8dc920166e2e3953e3468", "parents": [ "f723f0cdc693f81581c0781fa472b1c85a8b42d6" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 12 09:55:34 2013 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 12 13:05:18 2013 -0800" }, "message": "Disassemble more x86 instructions\n\nBy using oatdump on the core.oat, I found a couple more instructions\nthat didn\u0027t disassemble properly. These included another form of imul\nand some FP instructions used by the JNI code.\n\nNow the only unknown opcodes I could find seem to be literal data at\nthe end of the method.\n\nChange-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "f723f0cdc693f81581c0781fa472b1c85a8b42d6", "tree": "5d7b37796a71156d805340d88c0bd7f0078bd153", "parents": [ "8755359a35a4aa915fe3753633015263c7e97b74" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 11 17:50:58 2013 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Dec 11 17:50:58 2013 -0800" }, "message": "Add missing x86 imul opcode to disassembler\n\nWhen playing with ART, I noticed that an integer multiply didn\u0027t\ndisassemble properly. This patch adds the instruction.\n\nChange-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "70b797d998f2a28e39f7d6ffc8a07c9cbc47da14", "tree": "e5607068be133899ff9111e33327e0c2aa525cd1", "parents": [ "057c74a3a2d50d1247d4e6472763ca6f59060762" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 03 15:25:24 2013 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 03 18:32:29 2013 +0000" }, "message": "Unsafe.compareAndSwapLong() intrinsic for x86.\n\nChange-Id: Idbc5371a62dfdd84485a657d4548990519200205\n" }, { "commit": "a8b4caf7526b6b66a8ae0826bd52c39c66e3c714", "tree": "3393e7eeea6ae173caa59edd18b7c2c4c014650a", "parents": [ "17088bbded68e35da8050a40206dfd3cbba9e6d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 24 15:08:57 2013 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 28 18:30:48 2013 +0000" }, "message": "Add byte swap instructions for ARM and x86.\n\nChange-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d\n" }, { "commit": "02ed4c04468ca5f5540c5b704ac3e2f30eb9e8f4", "tree": "fd568452f4ae81868087e9a5f6c04a9051d0ef83", "parents": [ "28c2300d9a85f4e7288fb5d94280332f923b4df3" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Sep 06 13:10:04 2013 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Sep 09 08:33:36 2013 -0700" }, "message": "Move disassembler out of runtime.\n\nBug: 9877500.\nChange-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29\n" }, { "commit": "7934ac288acfb2552bb0b06ec1f61e5820d924a4", "tree": "43f3acd8af7fd34d4ae7b64f6e06bb8429d74bb8", "parents": [ "fb331d7ca004f39608fcfdae49d38df90c702ea9" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 26 10:54:15 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 26 11:55:10 2013 -0700" }, "message": "Fix cpplint whitespace/comments issues\n\nChange-Id: Iae286862c85fb8fd8901eae1204cd6d271d69496\n" }, { "commit": "1895ea386ca78573302483f589ebabd8ce1480e7", "tree": "d8c2d27ac746f29c8248fe17fd6b8e9872556fc4", "parents": [ "3e3d591f781b771de89f3b989830da2b6ac6fac8" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Thu Jul 18 13:28:37 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Thu Jul 18 14:38:27 2013 -0700" }, "message": "Fix cpplint readability/fn_size issues\n\nChange-Id: I1efdb07a948a2af49db1a9d21ccab16dacc03a54\n" }, { "commit": "7940e44f4517de5e2634a7e07d58d0fb26160513", "tree": "ac90242d96229a6942f6e24ab137bc1f8f2e0025", "parents": [ "5cd9e3b122f276f610980cbaf0d2ad6ed4cd9088" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 12 13:46:57 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 12 17:49:01 2013 -0700" }, "message": "Create separate Android.mk for main build targets\n\nThe runtime, compiler, dex2oat, and oatdump now are in seperate trees\nto prevent dependency creep. They can now be individually built\nwithout rebuilding the rest of the art projects. dalvikvm and jdwpspy\nwere already this way. Builds in the art directory should behave as\nbefore, building everything including tests.\n\nChange-Id: Ic6b1151e5ed0f823c3dd301afd2b13eb2d8feb81\n" }, { "commit": "5e588b3c9af58ef54dcdd2cf129472dbe923a5bf", "tree": "eee70f1d6111554feff40ebb4f0cadf8dd4e1a3a", "parents": [ "3afa4c1bae71f3d3cd7004b9b215facbdff22e63" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 21 15:05:09 2013 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Feb 21 15:09:17 2013 -0800" }, "message": "Output Intel group 0 prefixes.\n\nChange-Id: If1908f8fd4d0c5e1f019732e8945af501fe62e8c\n" }, { "commit": "e222ee0b794f941af4fb1b32fb8224e32942ea7b", "tree": "0b9f5fe6398663c9d871881cf7de28eca8bdfc6f", "parents": [ "1aa246dec5abe212f699de1413a0c4a191ca364a" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Dec 13 14:41:43 2012 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Dec 13 15:24:45 2012 -0800" }, "message": "Move stringpiece.h and stringprintf.h to base/.\n\nChange-Id: I7f71b4a12f99c5f81771146c66629ae5a947b229\n" }, { "commit": "07ed66b5ae659c452cbe1ab20c3dbf1d6f546461", "tree": "2350745da33df6fcb9fb0c9059e55ea5d5ea8f67", "parents": [ "76b6167407c2b6f5d40ad895b2793a6b037f54b2" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Dec 12 18:34:25 2012 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Dec 12 18:35:05 2012 -0800" }, "message": "Move logging.h into base/logging.h.\n\nChange-Id: Id68f85f7c3a71b156cb40dec63f94d4fb827f279\n" }, { "commit": "2bcb4a496b7aa00d996df3a070524f7568fb35a1", "tree": "8422ab8d65b7422008094b2eaadec0dad87b2df3", "parents": [ "efc6369224b036a1fb77849f7ae65b3492c832c0" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Nov 08 10:39:18 2012 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 16 14:01:34 2012 -0800" }, "message": "Add \"kind\" argument to Get/SetVReg.\n\nIn order to determine where a register is promoted its necessary to know\nthe kind of use of the register.\nExtend notion of precise-ness to numeric verifier register types.\nDump verifier output in oatdump.\nDump vregs with their location or constant value.\nIntroduce indenting ostream utility.\n\nChange-Id: Ia3d29497877976bc24465484743bca08236e1768\n" }, { "commit": "b23a7729cf7855fa05345d03a4d84111d5ec7172", "tree": "5313e076b19387db3cbcac95225d3f098f19451d", "parents": [ "137e88f798857321f4007631fdf052d2830ec2c4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 09 16:54:26 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 09 16:54:26 2012 -0700" }, "message": "Dump maps inline in disassembled code.\n\nIn pursuit of Bug: 7250540, dump mapping and GC map tables inline such\nas:\n\n0x607333a8: f8dfe11c ldr.w lr, [pc, #284] ; 0x6076416d\n0x607333ac: 1c05 mov r5, r0\n0x607333ae: f8df0144 ldr.w r0, [pc, #324] ; 0x6003ba08\n0x607333b2: 9a0b ldr r2, [sp, #44]\n0x607333b4: f04f0b2f orr r11, pc, ThumbExpand(47)\n0x607333b8: 1c29 mov r1, r5\n0x607333ba: 465b mov r3, r11\n0x607333bc: 2900 cmp r1, #0\n0x607333be: f0008070 beq.w +224 (0x607334a2)\n0x607333c2: 47f0 blx lr\nsuspend point dex PC: 44\nGC map objects: v2 (r7), v3 (r5), v6 ([sp + #84]), v7 (r6)\n...\n\nAs GC map and mapping tables are inline, don\u0027t dump them.\nAlso dump dex instructions before code.\n\nChange-Id: I9f0c04182a4cda6844027eae22e8151f2827dc99\n" }, { "commit": "77ae36b35d47393335bf5399cab9c91ccf08e88f", "tree": "736bfd865e7bfd7caf6c8bc282fa9d04d16232f7", "parents": [ "e37543ed52379bcf08f57ebb3510846294a7102c" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Aug 07 14:18:16 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Aug 07 16:24:08 2012 -0700" }, "message": "Fix and enable inlining of some intrinsics on x86.\n\nInlined min/max int, String isEmpty/length, and abs int/long.\n\nChange-Id: I24aa1b403ee5c8437d63c58dbe1504494ce106ef\n" }, { "commit": "8302576126efae240eb21c7545cda7982437bd26", "tree": "c49a698c034951cc6f3799472dabefb5ccdaaf7f", "parents": [ "937b73eea7a473395f3572e0db1fdc9c6a094db5" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 11:08:56 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 11:08:56 2012 -0700" }, "message": "Added thin-lock fast path for monitor-enter/exit on x86.\n\nChange-Id: Iba187ae1acde6e341ae510d4b47f59e6984fc354\n" }, { "commit": "854029c13351fd3a8f7794eb6c2c73af0fde8ac8", "tree": "3f2968be0023fa1d22303e74a989a1961ea402c9", "parents": [ "22fc28eb95191a1957025b219452c09c7fbb6bd0" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jul 23 17:31:30 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Jul 24 16:33:07 2012 -0700" }, "message": "Fixes to x86 register promotion and load hoisting.\n\nFixed a check to ensure that the mvzxb source register can be byte\naccessed, not the destination reg.\n\nDisabled branch fusion for x86 since code generation for that is\nunimplemented.\n\nChanged regId mask for x86 to allow proper masking of double registers.\n\nAlso added more output to the disassembler.\n\nChange-Id: Idc0a949755ec9ae7b6d5dba38caa5ac01fcc5713\n" }, { "commit": "703f2cd1f4d1eb5ab5c9792ca2de9ffb39378203", "tree": "652ceef30d52a13854c14bb0a6f586e96421f625", "parents": [ "e6e0651c7f0480e18d648200f8958c3463e82a2f" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jul 13 17:25:52 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jul 20 17:21:18 2012 -0700" }, "message": "Numerous fixes to enable PromoteRegs, though it\u0027s still broken.\n\n- Fixed ThrowNullPointerFromCode launchpad to load the array length\n directly into the necessary arg reg without clobbering the array\n pointer, since that value may be live afterwards.\n\n- genArrayPut use a temporary reg for bytes if the source reg is \u003e\u003d 4,\n since x86 can\u0027t express this.\n\n- Fixed the order that core regs are spilled and unspilled.\n\n- Correctly emit instructions when base \u003d\u003d rBP and disp \u003d\u003d 0.\n\n- Added checks to the compiler to ensure that byte opcodes aren\u0027t used\n on registers that can\u0027t be byte accessed.\n\n- Fixed generation of a number of ops which use byte opcodes, including\n floating point comparison, int-to-byte, and and-int/lit16.\n\n- Added rBP, rSI, and rDI to spill registers for the x86 jni compiler.\n\n- Various fixes and additions to the x86 disassembler.\n\nChange-Id: I365fe7dec5cc64d181248fd58e90789f100b45e7\n" }, { "commit": "fdffdf898f12d91765c7dbe7bcb1ccbbcd2b72d1", "tree": "87a7c98d46415dce49aea9a9c73a1351a5d64626", "parents": [ "f1f863695b28f630abb772f50170fefaddc2fb91" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Jul 11 16:08:43 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jul 12 14:32:54 2012 -0700" }, "message": "Fixes to enable TrackLiveTemps optimization on x86.\n\n- Created new kRegRegStore instruction class for Movdrx, where the\n source is first, and the destination is second.\n\n- Reverted neg_float and neg_double implementation to prevent confusion\n of register types when optimizations are performed.\n\n- Swapped order of loads for wide values to prevent base pointer from\n being clobbered when the base pointer equals the low destination reg.\n\n- Implemented opRegCopyWide for general purpose reg source to floating\n point reg destination and vice versa.\n\n- Added more opcode coverage to x86 disassembler.\n\nChange-Id: I4e58eec91742cc51333003fa5a678ba5b23eb575\n" }, { "commit": "e296248a124ed8287b38a9225463696c18d84cd6", "tree": "ffa3305cfb89082b39982d5d617f408c13cf3e66", "parents": [ "837210218c82a4f8e69304e58f8d018dbeb313b8" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jun 28 11:29:57 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jun 28 11:39:22 2012 -0700" }, "message": "Fixes for x86 compiler optimizations.\n\nx86 works with all but a few optimizations turned on, and the broken\nones are still disabled for now. This change includes:\n\n- Flagging of opcodes to incidate register use and def. Also, made\n flagging more complete for loads/stores and set/use ccodes.\n\n- Fixes to load store elimination, though it still doesn\u0027t work yet.\n\n- Prevent double values that are loaded or stored from losing their\n FP_DOUBLE flag. Later optimizations use this sizing.\n\n- Renumbering of DOUBLE registers so they alias with FP regs when\n masked.\n\n- Add support in the disassembler to recognize shifts.\n\nChange-Id: I758cdce418409fdd84206ce295005d5c9ab635f8\n" }, { "commit": "174651dea03956e160a2cff0d842954823c49134", "tree": "cee1f154612afe918a0640ee8aa33644b604c039", "parents": [ "640529bdc78deaeb8d1f3e95da90f9eb5ce9806d" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Apr 19 15:27:22 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Apr 19 16:01:28 2012 -0700" }, "message": "Fixed x86 division and modulus and merged their entry points.\n\nAlso enabled compilation of fill-array-data instructions in x86\n(untested), and improved x86 disassembly.\n\nChange-Id: Ia3d8d0766080d01f1c228f9283085024cadd528b\n" }, { "commit": "16b5c294c37460b51dc1f5296000cc80bbd33419", "tree": "93724e7c43a919cda2298719120895fa705bc529", "parents": [ "54a3e919ef3c8788e39a21696944d00826c25af3" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 20:37:16 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 20:37:16 2012 -0700" }, "message": "Disassemble x86 0xd0 and 0xd1 shifts.\n\nChange-Id: Id061e1971e7a829f57bb83e5299d999d1da8d21e\n" }, { "commit": "14178a99fd397737124e65d5ccb9446f85c5ca93", "tree": "5d6a25f1cc4ca806985ea6450b6dcffaa83c8ae3", "parents": [ "3ea0f42467790809fcfc9fc861605d465808090f" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 17:24:51 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 17:24:51 2012 -0700" }, "message": "Always show the sign of an x86 relative branch, like we do for architectures.\n\nChange-Id: I7f3d4d72179b741064832f9032c9801e201b3b4f\n" }, { "commit": "bf989802bfcd0a0e1d27feb6b67b19cccb7b31e8", "tree": "d2597060cc7ca7e299260aeb6a0256443df0f417", "parents": [ "5450e0ef824b71d9cccc4b322048cabc96f141e6" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 16 16:07:49 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 16 16:07:49 2012 -0700" }, "message": "SSE disassembler support.\n\nChange-Id: I43f5d52ea960e9410cd4db61a14e16eb919419fc\n" }, { "commit": "92301d97693ea52f5f6a9bc62d0c7fc611f87c7b", "tree": "79a55125e94fe1906b354d3d74277354b5aa1706", "parents": [ "b92bcabcbb28f69fe99e1c2f2e5559ab2c47aa60" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 10 15:57:52 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 10 15:57:52 2012 -0700" }, "message": "Decode thread offsets in x86 disassembly.\n\nChange-Id: I924521998c743e61f94cc0d5d71ef53d531d8b56\n" }, { "commit": "0589ca9245849df238812444952c674e01361f2a", "tree": "6c1abb39d336da73c49267b8ba231e2542356ec3", "parents": [ "28fa76d17d741238da86dbdb47f721ae97c9eac8" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 18:26:20 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 18:26:20 2012 -0700" }, "message": "Disassemble x86 opcode 0xc7.\n\nThis was our most popular unknown opcode by far. Example (now):\n\n 0x0007: move-exception v0\n 0x60f51fe8: 648B0578000000 mov eax, fs:[0x78]\n 0x60f51fef: 64C7057800000000000000 mov fs:[0x78], 0\n\nChange-Id: I39d8dde72503a4c418b2d4f5cb7e238ae576d74c\n" }, { "commit": "28fa76d17d741238da86dbdb47f721ae97c9eac8", "tree": "de34f96fbbda6d650db267bd595a20191b9a07cf", "parents": [ "82914b6164fd0109531391975389e4f0ff6832c8" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 17:31:46 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 09 17:59:35 2012 -0700" }, "message": "A dirty (but useful) hack to decode thread offsets in disassembly.\n\nPlus more readable x86 formatting.\n\nAlso fix a bug decoding LDR (immediate, Thumb) encoding T1.\n\nChange-Id: I95c79d3fb4d912d1ef386b5843abd37d3652a476\n" }, { "commit": "7caad77632ae121c9f64c488e3f8f710e2c4813d", "tree": "6b12ff6e0c27529f5434c5655b3306a1f79bd379", "parents": [ "4855cd516d97c9728fa58312acdf6c4b8b81397a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 30 01:07:54 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 04 09:56:48 2012 -0700" }, "message": "Implement various missing parts of the X86 compiler\n\nChange-Id: I76f08580600befe268328f8cf7102c6146460c5e\n" }, { "commit": "0f3c55331439970e01af67f80ac117c473bc04cf", "tree": "cfa28ad2a58af1ffddb0a2ce90443ad4606743c3", "parents": [ "273cf36d199cf73de3cf61a559ad27c9d23f9825" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Mar 30 14:51:51 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Mar 30 14:51:51 2012 -0700" }, "message": "Kill constants.h and fix some copyright headers.\n\nChange-Id: I51c04d731d6de035328781d8ac134ad6fcf49897\n" }, { "commit": "b25c3f6a86dc634ce44fb2849385b49465caa84d", "tree": "f359c72d821d913f78b977d8dde0fc7023afb511", "parents": [ "fc9e6fabed89d948fa8c0e9d673e430076712c60" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Mar 26 16:35:06 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Mar 26 17:11:59 2012 -0700" }, "message": "Fix cpplint\u0027s whitespace complaints.\n\nChange-Id: I11fd2db2badf7bd98e7866ca2155d8ef1e112408\n" }, { "commit": "706a10ea53a32455c6b3ffc5e5e0e1f6f191ec2a", "tree": "445e94f7b51a5d2b21366afabdf58128116cd065", "parents": [ "9f798f9c7e92a5437c8ad901bb17b9c4e1e9e209" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 23 17:00:55 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 23 23:05:07 2012 -0700" }, "message": "X86 disassembler.\n\nChange-Id: Ie38c55979931f365ec20073a651cfbccc4b86bb4\n" } ] }