)]}' { "log": [ { "commit": "889da94a5931a68ca527dc7320ff0b5de69917fc", "tree": "1c5d50e5a63f35073ba7b6b84f6f6b5f965d7c62", "parents": [ "d78f319c52888d1c45d17ce1521e4f78db2d7119" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Apr 30 13:03:14 2021 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Apr 30 16:58:11 2021 +0000" }, "message": "Fix gtests with mini-debug-info enabled by default.\n\nEnsure we can generate mini-debug-info if it is enabled by default.\nThe tests don\u0027t explicitly generate the info on background thread.\n\nTest: test.py -g\nChange-Id: If3cf9a067ce683f728d553394e1407beeadae670\n" }, { "commit": "55ab7e84c4682c492b6fa18375b87ffc5d0b23bb", "tree": "5fcc2567a1a4e6ae73dead2f70c69bc03b0a64bb", "parents": [ "ac27ac01490f53f9e2413dc9b66fbb2880904c96" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 27 21:02:28 2020 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Fri Feb 05 11:34:38 2021 +0000" }, "message": "ARM64: Support SVE VL other than 128-bit.\n\nArm SVE register size is not fixed and can be a\nmultiple of 128 bits. To support that the patch\nremoves explicit assumptions on the SIMD register\nsize to be 128 bit from the vectorizer and code\ngenerators and enables configurable SVE vector\nlength autovectorization, e.g. extends SIMD register\nsave/restore routines.\n\nTest: art SIMD tests on VIXL simulator.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n with FVP arg:\n -C SVE.ScalableVectorExtension.veclen\u003d[2,4]\n (SVE vector [128,256] bits wide)\n\nChange-Id: Icb46e7eb17f21d3bd38b16dd50f735c29b316427\n" }, { "commit": "8ba4de1a5684686447a578bdc425321fd3bccca6", "tree": "20c24450b24950266ccc235306e3ad2109c57497", "parents": [ "32bf6d39bc020cacfc655ce60630f4a0da3b45cf" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Dec 04 21:10:23 2019 +0000" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Thu Feb 04 06:16:33 2021 +0000" }, "message": "ART: Implement predicated SIMD vectorization.\n\nThis CL brings support for predicated execution for\nauto-vectorizer and implements arm64 SVE vector backend.\n\nThis version passes all the VIXL simulator-runnable tests in\nSVE mode with checker off (as all VecOp CHECKs need to be\nadjusted for an extra input) and all tests in NEON mode.\n\nTest: art SIMD tests on VIXL simulator.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n\nChange-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f\n" }, { "commit": "3a73ffb70151dbc99fa41f300a237f8c29783e0e", "tree": "8debef1b372e5bea27d5265a9019446229955e3d", "parents": [ "e585964df42e9fd2fab6f209810cb03e1b261ab1" ], "author": { "name": "Alex Light", "email": "allight@google.com", "time": "Mon Jan 25 14:11:05 2021 +0000" }, "committer": { "name": "Alex Light", "email": "allight@google.com", "time": "Mon Jan 25 07:01:32 2021 -0800" }, "message": "Revert^4 \"Partial Load Store Elimination\"\n\nThis reverts commit 791df7a161ecfa28eb69862a4bc285282463b960.\nThis unreverts commit fc1ce4e8be0d977e3d41699f5ec746d68f63c024.\nThis unreverts commit b8686ce4c93eba7192ed7ef89e7ffd9f3aa6cd07.\n\nWe incorrectly failed to include PredicatedInstanceFieldGet in a few\nconditions, including a DCHECK. This caused tests to fail under the\nread-barrier-table-lookup configuration.\n\nReason for revert: Fixed 2 incorrect checks\n\nBug: 67037140\nTest: ./art/test/testrunner/run_build_test_target.py -j70 art-gtest-read-barrier-table-lookup\n\nChange-Id: I32b01b29fb32077fb5074e7c77a0226bd1fcaab4\n" }, { "commit": "791df7a161ecfa28eb69862a4bc285282463b960", "tree": "a43b022307ea2df82a360164bdf2627cd07eb5b1", "parents": [ "805769bb3800c1e47b0a76ce2c5ebb270a4ac69d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 23 13:28:56 2021 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Jan 24 17:18:55 2021 +0000" }, "message": "Revert \"Revert^2 \"Partial Load Store Elimination\"\"\n\nThis reverts commit fc1ce4e8be0d977e3d41699f5ec746d68f63c024.\n\nBug: 67037140\n\nReason for revert: Fails read-barrier-table-lookup tests.\n\nChange-Id: I373867c728789bc14a4370b93a045481167d5f76\n" }, { "commit": "fc1ce4e8be0d977e3d41699f5ec746d68f63c024", "tree": "b656aa7c9e62aa181dfbf7fd4f2a0d32b8bf0704", "parents": [ "c6da1be58086e873c9695f8c4c1a3a8ca718696e" ], "author": { "name": "Alex Light", "email": "allight@google.com", "time": "Fri Jan 22 14:05:13 2021 +0000" }, "committer": { "name": "Alex Light", "email": "allight@google.com", "time": "Fri Jan 22 07:15:51 2021 -0800" }, "message": "Revert^2 \"Partial Load Store Elimination\"\n\nThis reverts commit 47ac53100303e7e864b7f6d65f17b23088ccf1d6.\n\nThere was a bug in LSE where we would incorrectly record the\nshadow$_monitor_ field as not having a default initial value. This\ncaused partial LSE to be unable to compile the Object.identityHashCode\nfunction, causing crashes. This issue was fixed in a parent CL. Also\nupdated all Offsets in LSE_test to be outside of the object header\nregardless of configuration.\n\nTest: ./test.py --host\nBug: 67037140\n\nReason for revert: Fixed issue with shadow$_monitor_ field and offsets\n\nChange-Id: I4fb2afff4d410da818db38ed833927dfc0f6be33\n" }, { "commit": "47ac53100303e7e864b7f6d65f17b23088ccf1d6", "tree": "95730c6ba84ef0eebca6236428c8ba51c5eaf280", "parents": [ "51d771db35cc0647bc1fd2a32ed6348d181a7a41" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 22 08:41:08 2021 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 22 08:41:39 2021 +0000" }, "message": "Revert \"Partial Load Store Elimination\"\n\nThis reverts commit b8686ce4c93eba7192ed7ef89e7ffd9f3aa6cd07.\n\nBug: 67037140\n\nReason for revert: Fails a few tests.\n\nChange-Id: Icf0635bffbfbba93bf0a5b854a9582c418198136\n" }, { "commit": "b8686ce4c93eba7192ed7ef89e7ffd9f3aa6cd07", "tree": "1721ee940f978736a2212d693271ee698897cb0b", "parents": [ "625048049558d394d50b6e98885b8c210e481bf1" ], "author": { "name": "Alex Light", "email": "allight@google.com", "time": "Mon Nov 02 08:48:33 2020 -0800" }, "committer": { "name": "Alex Light", "email": "allight@google.com", "time": "Thu Jan 21 17:58:10 2021 +0000" }, "message": "Partial Load Store Elimination\n\nAdd partial load-store elimination to the LSE pass. Partial LSE will\nmove object allocations which only escape along certain execution\npaths closer to the escape point and allow more values to be\neliminated. It does this by creating new predicated load and store\ninstructions that are used when an object has only escaped some of the\ntime. In cases where the object has not escaped a default value will\nbe used.\n\nTest: ./test.py --host\nTest: ./test.py --target\nBug: 67037140\n\nChange-Id: Idde67eb59ec90de79747cde17b552eec05b58497\n" }, { "commit": "98873affc25ef6bc96f8c65f828f28530b8f3fcd", "tree": "be471ad310edb1aa3a7b3df44528905ec7ce9a6c", "parents": [ "771708f3f0a15c1ae50617b4141c5f5dd47bf94f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 16 12:10:03 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 08 13:44:10 2021 +0000" }, "message": "arm64: Implement VarHandle intrinsics for byte array views.\n\nUsing benchmarks provided by\n https://android-review.googlesource.com/1420959\non blueline little cores with fixed frequency 1420800:\n before after\nGetByteArrayViewInt 27.093 0.024\nSetByteArrayViewInt 28.067 0.024\nGetByteArrayViewBigEndianInt 27.142 0.026\nSetByteArrayViewBigEndianInt 28.040 0.025\n\nTest: testrunner.py --target --64 --optimizing\nBug: 71781600\nChange-Id: I604326675042bd63dce8ec15075714003ca9915d\n" }, { "commit": "c8178f5eb06aa54f78237145d7fdc05609c02962", "tree": "e69d3979efb81ca752f5f2d469279e26f22329aa", "parents": [ "e8cdb0bb53e42316e8c7379d41a647ca672c4bee" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 24 10:38:16 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 02 20:20:49 2020 +0000" }, "message": "arm64: Clean up VarHandle intrinsics implementation.\n\nFix some typos and update some table lookup code that\u0027s\ncurrently unused. Bring in a few things from arm (naming,\nstatic assertion, pull an expression to a named variable).\n\nTest: testrunner.py --target --64 --optimizing\nBug: 71781600\nChange-Id: If2f2c4417942a272a8ad672c6b876e0569f8827c\n" }, { "commit": "d6bd107ed83502eb0bbaf66911ab036ecf74612d", "tree": "81686cdcb1e29b7fc077a9ba31db4c448ac7d007", "parents": [ "f6332e8b09599bea16666e9bbc6bdfd0c3fb2cef" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 30 18:42:01 2020 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 30 18:46:19 2020 +0000" }, "message": "Fix invokeinterface sharpened with kRuntimeCall.\n\nBug: 174260111\nBug: 173677667\n\nTest: 728-imt-conflict-zygote\nTest: atest com.android.bootimageprofile.BootImageProfileTest#testSystemServerProfile\nTest: adb install com.google.android.art.apex\nChange-Id: Ie600a0c8c8eb38d9084b796bac9184c06ea0a2f4\n" }, { "commit": "a07de551da5147f3635c665a31f262cf65647118", "tree": "d6f8199cc45ab8b6ef779f97ef0e8f0d04520ef8", "parents": [ "4483d2a4ed7e6c018e304c234484940ec0476039" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Sun Nov 01 22:42:43 2020 +0000" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Mon Nov 16 14:31:54 2020 +0000" }, "message": "Revert^2 \"ART: Fix breaking changes from recent VIXL update.\"\n\nThis reverts commit eeaf47f7c9bbad29afab84a0f199a5751d9c616b.\n\nAlso fixes the gtest failure when VIXL simulator stack\nwas overflown.\n\nTest: test-art-target, test-art-host.\nTest: ART_USE_READ_BARRIER\u003dfalse \\\n SANITIZE_HOST\u003daddress \\\n ASAN_OPTIONS\u003d\u0027detect_leaks\u003d0\u0027 \\\n SOONG_ALLOW_MISSING_DEPENDENCIES\u003dtrue \\\n ART_HEAP_POISONING\u003dtrue m test-art-host-gtest\n\nChange-Id: Ibc1f21204940083879f767d6993127bdde8326af\n" }, { "commit": "32c2eb81320f24b5bab24754204b8be95faa08b0", "tree": "6c8d6978f05d2046baf26829d7ba00ae8ef647ad", "parents": [ "b209a043a0d5965f25dcb9fde2049df493dcf602" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 10 16:58:47 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 13 08:59:35 2020 +0000" }, "message": "arm64: Implement VarHandle GetAndSet intrinsics.\n\nAdd an extra test to 160-read-barrier-stress. The main path\nis sufficiently exercised by 712-varhandle-invocations.\n\nUsing benchmarks provided by\n https://android-review.googlesource.com/1420959\non blueline little cores with fixed frequency 1420800:\n before after\nGetAndSetStaticFieldInt 23.809 0.027\nGetAndSetStaticFieldString 27.112 0.035\nGetAndSetFieldInt 26.988 0.028\nGetAndSetFieldString 29.626 0.034\nGetAndSetAcquireStaticFieldInt 23.900 0.025\nGetAndSetAcquireStaticFieldString 27.084 0.034\nGetAndSetAcquireFieldInt 26.972 0.026\nGetAndSetAcquireFieldString 29.617 0.032\nGetAndSetReleaseStaticFieldInt 23.876 0.027\nGetAndSetReleaseStaticFieldString 27.093 0.035\nGetAndSetReleaseFieldInt 26.969 0.028\nGetAndSetReleaseFieldString 29.609 0.034\n\nTest: testrunner.py --target --64 --optimizing\nTest: Repeat with ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue.\nTest: Repeat with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP.\n (Ignore two pre-existing checker test failures.)\nBug: 71781600\nChange-Id: I6a03858b1446354919cd4d08348ef93b725aafc6\n" }, { "commit": "e17530a19a717879c8dd8e70073de6aaf4ee455f", "tree": "745e7e23519d37ae5fcafcf9f63c5e707779ce1b", "parents": [ "bb6cda60e4418c0ab557ea4090e046bed8206763" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 11 17:02:26 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 12 10:53:53 2020 +0000" }, "message": "arm64: Fix VarHandle intrinsics for non-Baker read barrier.\n\nIt turns out the artReadBarrierSlow() ignores the passed\nreference and reloads the field from the object. This makes\nsome of the VarHandle intrinsics broken for the TABLELOOKUP\nconfiguration. This change disables the broken variants of\nthese intrinsics (but leaves support code in place) and\ncleans up locations for those variants that remain active.\n\nAlso refactor reference argument checks and do a few other\nsmall cleanups (renames, comment updates, etc.).\n\nTest: testrunner.py --target --64 --optimizing\nTest: Repeat with ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue.\nTest: Repeat with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP.\n (Ignore two pre-existing checker test failures.)\nBug: 71781600\nChange-Id: I8d28a4883771a8db2b283737bb643b36c7038c26\n" }, { "commit": "1bff99f706a1b1a4c1799e0f037d9f59f303587a", "tree": "06cabecf52fbd336a2e65dbde991c45ce10bc64a", "parents": [ "b15e8797d2ca6fb480a940887c66dd2aae7c9065" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 02 15:07:33 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 10 10:36:19 2020 +0000" }, "message": "arm64: Implement VarHandle CAS intrinsics.\n\nAnd refactor Unsafe CAS intrinsics for code reuse.\n\nAdd extra tests to the 160-read-barrier-stress to test the\nslow paths. The main path is sufficiently exercised by the\n712-varhandle-invocations test. The refactored Unsafe CAS is\nalready covered by 004-Unsafe and 160-read-barrier-stress.\n\nUsing benchmarks provided by\n https://android-review.googlesource.com/1420959\non blueline little cores with fixed frequency 1420800:\n before after\nCompareAndSetStaticFieldInt 24.721 0.026\nCompareAndSetStaticFieldString 29.015 0.032\nCompareAndSetFieldInt 27.237 0.028\nCompareAndSetFieldString 31.326 0.033\nWeakCompareAndSetStaticFieldInt 24.735 0.027\nWeakCompareAndSetStaticFieldString 28.970 0.031\nWeakCompareAndSetFieldInt 27.252 0.028\nWeakCompareAndSetFieldString 31.309 0.036\nWeakCompareAndSetPlainStaticFieldInt 24.738 0.026\nWeakCompareAndSetPlainStaticFieldString 29.004 0.030\nWeakCompareAndSetPlainFieldInt 27.252 0.027\nWeakCompareAndSetPlainFieldString 31.326 0.035\nWeakCompareAndSetAcquireStaticFieldInt 24.728 0.026\nWeakCompareAndSetAcquireStaticFieldString 28.977 0.030\nWeakCompareAndSetAcquireFieldInt 27.250 0.027\nWeakCompareAndSetAcquireFieldString 31.306 0.034\nWeakCompareAndSetReleaseStaticFieldInt 24.738 0.026\nWeakCompareAndSetReleaseStaticFieldString 28.994 0.032\nWeakCompareAndSetReleaseFieldInt 27.250 0.028\nWeakCompareAndSetReleaseFieldString 31.312 0.035\nCompareAndExchangeStaticFieldInt 23.898 0.026\nCompareAndExchangeStaticFieldString 28.544 0.032\nCompareAndExchangeFieldInt 26.787 0.027\nCompareAndExchangeFieldString 31.022 0.034\nCompareAndExchangeAcquireStaticFieldInt 23.957 0.026\nCompareAndExchangeAcquireStaticFieldString 28.586 0.031\nCompareAndExchangeAcquireFieldInt 26.785 0.026\nCompareAndExchangeAcquireFieldString 31.011 0.033\nCompareAndExchangeReleaseStaticFieldInt 23.963 0.026\nCompareAndExchangeReleaseStaticFieldString 28.511 0.032\nCompareAndExchangeReleaseFieldInt 26.729 0.027\nCompareAndExchangeReleaseFieldString 30.938 0.034\n\nTest: testrunner.py --target --64 --optimizing\nTest: Repeat with ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue.\nTest: Repeat with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP.\n (Ignore two pre-existing checker test failures.)\nBug: 71781600\nChange-Id: I01b2218bb812bc636a941f9bd67c844aee5f8b41\n" }, { "commit": "de91ca90389e4b41ed27b320a6c43ff56a6d75ff", "tree": "2e18ff33d30fce88d578ea68b8b1037755aececc", "parents": [ "9ca92fb4646eccff9f972f6a2a21709676b65460" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 27 13:41:40 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 29 15:42:52 2020 +0000" }, "message": "Refactor Integer.valueOf() intrinsic implementation.\n\nPrepare for Reference.getReferent() intrinsic implementation\nby a refactoring to separate the retrieval of an intrinsic\nmethod\u0027s declaring class to its own helper function, rather\nthan being a part of a larger one.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: aosp_blueline-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing --jit\nBug: 170286013\nChange-Id: Ib6c0e55d0c6fcc932999428f21c51afe32ab7ef2\n" }, { "commit": "eeaf47f7c9bbad29afab84a0f199a5751d9c616b", "tree": "3b1572bd8c3cd89dbe060b52d1760bd857e999ed", "parents": [ "1f3612f93759823d630e117be5216f694e0702e9" ], "author": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Wed Oct 28 15:59:29 2020 +0000" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Oct 28 17:42:50 2020 +0000" }, "message": "Revert \"ART: Fix breaking changes from recent VIXL update.\"\n\nRevert submission 1331125-VIXL_UPDATE_SVE\n\nReason for revert: broken build git_master-art-host/art-gtest-heap-poisoning @ 6936943\nReverted Changes:\nIc10af84a0:Merge remote-tracking branch \u0027aosp/upstream-master...\nI752a0b0ba:ART: Fix breaking changes from recent VIXL update....\n\nBug: 171879890\nChange-Id: Idb0d5c2e88948d799a4ef2c828be2828ea2270ea\n" }, { "commit": "4955036617ff4940bd35fa8ce63f0728c1042902", "tree": "20ebe9c047b9ed5e21e99f2f0a00a3946fa731e8", "parents": [ "036b0708c12a33469db4a5adde9ded152b5eb700" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Jul 05 18:23:03 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 28 12:03:34 2020 +0000" }, "message": "ART: Fix breaking changes from recent VIXL update.\n\nAlso fixes the vixl-related headers includes.\n\nTest: test-art-target, test-art-host\n\nChange-Id: I752a0b0baf741aa2a0693253155042104c8b3b27\n" }, { "commit": "eb9eb00868106af52386d7113a8aafaa6d44e8b6", "tree": "05b1243b30b31d6e2d3215ebdaa329c90d9875f8", "parents": [ "5fa36f99fdb5617d1ced977c637dcaa2762704fc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 02 13:54:19 2020 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Oct 19 17:01:09 2020 +0000" }, "message": "Faster @CriticalNative for boot image.\n\nThe @CriticalNative call does not need the target method, so\nwe can avoid one instruction on x86, x86-64 and arm64. The\ncurrent approach for arm does not allow such optimization.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_blueline-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --64 --optimizing\nBug: 112189621\nChange-Id: I11b7e415be2697757cbb11c9cccf4058d1d72d7d\n" }, { "commit": "8d34a182fea1b24f7b8361b55e930cb953cf3fb2", "tree": "4f5ed9d9ac417dfd69fd18f64412b2272c448e05", "parents": [ "8ecbc4e844fc3b73e6a5c5151eda914d53297180" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 16 09:46:58 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 07 08:32:52 2020 +0000" }, "message": "Change interface conflict stub to take the interface method.\n\nTo avoid doing dex cache lookup, pass the interface method instead. This\ncosts a few hundred KBs on speed compiled APKs (\u003c 0.5% code size), but\nimproves performance when hitting a conflict (as seen on dogfood data).\n\nFor nterp, we currently pass the conflict method instead of the\ninterface method. We need to handle default methods before optimizing\nit.\n\nThis removes our last use of dex cache in compiled code. A follow-up CL\nwill remove the NeedsDexCacheOfDeclaringClass from HInvokeInterface.\n\nTest: test.py\n\nChange-Id: I3cdd4543ad7d904b3e81950af46a48a48af6991a\n" }, { "commit": "2d98dc23d6e9b74ef004d4358d6c3d53503b12a7", "tree": "52e950bc8fead0bbb93cef38b17cec9723604fe1", "parents": [ "cd8ffcbca3e25c3ee8c0ffeaadac4167db6f2b58" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 01 11:21:37 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 02 10:02:09 2020 +0000" }, "message": "arm64: VarHandle.{get,set}{Opaque,Acquire,Volatile}.\n\nExtend the VarHandle.{get,set} for fields to similar\nvariants with additional memory ordering requirements.\n\nTest: testrunner.py --target --64 -t 712-varhandle-invocations\nTest: Repeat with ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue.\nTest: Repeat with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP.\nBug: 65872996\nChange-Id: I400802a1e089a5a81149316f88bb90979f8988e6\n" }, { "commit": "8f63f1084b013a129f66cf8a7ed8ab1cae9f02aa", "tree": "6e9bbf5ad71a55f701f740e2995e0b84e9b87307", "parents": [ "7aa2bfc09541ea5d2516738de84c24cd0269fed0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 28 12:10:28 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 30 13:58:32 2020 +0000" }, "message": "Faster access to unresolved classes from compiled code.\n\nAdd two new load kinds to LoadClass, similar to kBssEntry\nbut using the access-checking entrypoint on the slow-path.\nOne is used for classes that are in the literal package and\nthe other for classes outside the literal package of the\ncompiling class. Associate new .bss entries with these load\nkinds and update them from entrypoints based on the resolved\nclass properties. If the resolved class is public, both\ntypes of entries can be updated, otherwise only the package\nlocal entry can be updated and only if the defining class\nloader of the class is the same as the caller\u0027s defining\nclass loader (which is identical for all code in an oat\nfile) because the run time access check for same package\nrequires both class loader and literal package name match.\n\nTest: Additional tests in 727-checker-unresolved-class.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_blueline-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nBug: 161898207\nChange-Id: I281e06ac2825caf81c6d7ee3128af833abd39992\n" }, { "commit": "6d69b52f331f788cbd1f21ffd5b87cb3b39965e4", "tree": "2bca1001afb4c3fc45cbb198765c51aa65e45c42", "parents": [ "e407d97b0f25562110511d025058dcefdacca623" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 23 14:47:28 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 23 14:47:28 2020 +0100" }, "message": "Move MethodLoadKind out of HInvokeStaticOrDirect.\n\nTo prepare for using it in HInvokeInterface. For consistency, also move\nCodePtrLocation.\n\nTest: test.py\nChange-Id: I84f973764275002e2adb71080ebc833b2bafb975\n" }, { "commit": "c679fe3915fee6c490c1e8478a6c455f62c10a3f", "tree": "f0f676afba57ee13a3e040bce1a5636d5e6b838a", "parents": [ "952c0904d46f4170c6a2578c19a702a0499e57f4" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Sep 14 14:02:40 2020 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Sep 18 12:23:51 2020 +0000" }, "message": "ARM: Optimize div/rem when dividend is compared with a non-negative\n\nWhen a divisor is a positive constant and a dividend is compared with a\nnon-negative value, the result of the comparison can guarantee that the\ndividend is non-negative. In such a case there is no need to generate\ninstructions correcting the result of div/rem.\n\nThe CL implements this optimization for ARM32/ARM64.\n\nTest: 411-checker-hdiv-hrem-pow2\nTest: 411-checker-hdiv-hrem-const\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\nChange-Id: If1dc1389f6e34d2be3480ef620a626f389ca53a5\n" }, { "commit": "a41ea2708d143b5982f1969864513b62706d11d4", "tree": "dfe5d58ffb7dd6d9220e87430416b8ea2deef617", "parents": [ "1e2d5679e56364b090c989427f43ad6273359904" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 07 15:24:36 2020 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Sep 11 10:33:12 2020 +0000" }, "message": "arm64: VarHandle.get/set intrinsic for fields.\n\nTest: testrunner.py --target --64 --optimizing -t 712-varhandle-invocation\nTest: Repeat with ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue.\nTest: Repeat with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP.\nBug: 65872996\nChange-Id: Ic0ec2eba7b493ef3b1d15291b67e0214e6e2de0e\n" }, { "commit": "e6c0f2a75bd969253279580e2e4772e54787034b", "tree": "79598b2b6b457d9c718ddb18e29a0211a73ae85a", "parents": [ "63c0c2d9da31d26781f5e77aba6125f0d0988795" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Sep 07 08:30:52 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 08 13:51:53 2020 +0000" }, "message": "Pass a full MethodReference of the invoke in HInvoke nodes.\n\nCleanup to ensure we don\u0027t make mistakes when passing a dex method index\nto the HInvoke constructor, and we know which dex file it relates to.\n\nTest: test.py\nChange-Id: I625949add88a6b97e1dafeb7aed37961e105d6aa\n" }, { "commit": "4313ccb65b6d77821b1fb976d76a90f1000adaea", "tree": "d083f10b003e4e377927af876aedef3375a464ca", "parents": [ "2ff0cb1d29989f1a92824d225de76037ff31cec4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Aug 26 17:01:15 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 27 13:39:54 2020 +0000" }, "message": "Introduce a kTieredHotnessMask.\n\nTo be used by the baseline compiler for when to trigger optimized\ncompilation. Before we were using the nterp threshold, but there may be\na need to have different ones.\n\nTest: test.py\nBug: 112676029\nChange-Id: I98e97ad8cfa50a6546c927960fad1567263a7354\n" }, { "commit": "095dc4611b8001861f8d0e621f9df704a933754a", "tree": "edbbd5b116d8caaceb4ce4605343f3e0d59c11c1", "parents": [ "ed29dcee8b5d7e62bb119d2366f3b95dd5f96163" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Aug 17 16:40:28 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Aug 24 09:06:03 2020 +0000" }, "message": "Move the profiling info out of ArtMethod.\n\nInstead, keep a map in JitCodeCache.\n\nBug: 112676029\nTest: test.py\nChange-Id: I5ab769a9b7b3214af7832478d1b06c9e9adbf8b8\n" }, { "commit": "0f3d7acf40b2ba1b04a9b359950a30b6314ace07", "tree": "fe25b27252489b17dd9865ddf688649dc9495ff7", "parents": [ "50fe6dc170402600936d72a5fd729b5ebda0294b" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu Aug 06 16:28:37 2020 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue Aug 18 15:10:01 2020 +0100" }, "message": "ART: Add HasNonNegativeInputAt and HasNonNegativeOrMinIntInputAt\n\nWhen it can be quickly checked that an input operand in non-negative,\nadditional optimizations can be applied during code generation.\n\nThe CL adds HasNonNegativeInputAt and HasNonNegativeOrMinIntInputAt\nwhich can be used to check if the input operand of an instruction at\nthe index is non-negative. They guarantee that at the time of checks\nthe instruction can have non-negative inputs. Other optimizations after\nthat might break the invariant.\n\nOptimizations HRem/HDiv for ARM32/ARM64 are moved to used the new methods.\n\nTest: 411-checker-hdiv-hrem-pow2\nTest: 411-checker-hdiv-hrem-const\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\nChange-Id: Icf8574699e003bba194097c4e39660de16aa53d9\n" }, { "commit": "a0130e8d2842a9a82e4fd4e811ee699272eb2e0b", "tree": "1468e015b7c4b001e40d847cf1448311706516e7", "parents": [ "75c8b635178d0c59691c2bc22f3bd1101d5516b5" ], "author": { "name": "Andra Danciu", "email": "andradanciu@google.com", "time": "Thu Jul 23 12:34:56 2020 +0000" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri Jul 24 10:11:54 2020 +0000" }, "message": "Prepare compiler for adding VarHandle support.\n\nThis commit prepares the ground for adding VarHandle support\nin the compiler. The intrinsic locations builder and code\ngenerator are now triggered for HInvokePolymorphic nodes.\nVarHandle and MethodHandle intrinsics are marked as unimplemented\nrather than unreachable.\n\nSince the Varhandle intrinsics are not implemented yet, the\nfunctionality is not changed (i.e. the intrinsics are evaluated\nat runtime and not compiled). I manually tested that the intrinsic\nVisit* methods are triggered for the VarHandle methods.\n\nBug: b/65872996\nTest: art/test.py --host -r -t 713-varhandle-invokers\nTest: art/test.py --host --all-compiler -r\n\nChange-Id: I3333728c5f16d8dc4f92ceae2738ed59b3e31e6a\n" }, { "commit": "f9388416a3315b93d0cf14eeaf8df49a7c4da176", "tree": "f90d73c779cc16bf2a532b102820a2c7ecdd30e9", "parents": [ "af92a0f06fe3ab2618ccc220df3dacc3a20d8bb1" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu Jul 02 15:25:13 2020 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu Jul 02 17:23:25 2020 +0100" }, "message": "ARM: Optimize Div/Rem by positive const for non-negative dividends\n\nWhen a constant divisor is positive and it can be proved that dividends\nare non-negative, there is no need to generate instructions correcting\nthe result.\n\nThe CL implements this optimization for ARM32/ARM64.\n\nTest: 411-checker-hdiv-hrem-const\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\nChange-Id: Idf9aa740f14700000948b5ca58311be403a269ee\n" }, { "commit": "af92a0f06fe3ab2618ccc220df3dacc3a20d8bb1", "tree": "a1825765fba713b9805a26b35743506907cdefe8", "parents": [ "8d799686ff11ef800a8489272f4e0b36b6ab21b3" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jun 26 13:28:33 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 02 10:49:08 2020 +0000" }, "message": "ARM: Optimize Div/Rem by 2^n for non-negative dividends\n\nWhen it can be proved that dividends are non-negative or the min integer\nif their type is integral, there is no need to generate instructions\ncorrecting the result.\n\nThe CL implements this optimization for ARM32/ARM64.\n\nTest: 411-checker-hdiv-hrem-pow2\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\n\nChange-Id: I11211a42918b5801fce8e78f305e69549739c23c\n" }, { "commit": "dec7817522eeaf8f88dcae9ce065969aeebda3b3", "tree": "a15fd16ccb4a1929ec60584ead8f095b565c9e3e", "parents": [ "ea4d7d2d52dd9795cf39eccd46cb07551c62392f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 19 15:31:23 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 22 08:05:28 2020 +0000" }, "message": "Optimizing: Introduce {Increase,Decrease}Frame().\n\nAnd use it to clean up code generators.\n\nAlso fix CFI in MaybeIncrementHotness() for arm/arm64/x86.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --host --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nTest: aosp_cf_x86_phone-userdebug boots.\nTest: aosp_cf_x86_phone-userdebug/jitzygote boots.\nTest: # On blueline:\n testrunner.py --target --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nBug: 112189621\nChange-Id: I524e6c3054ffe1b05e2860fd7988cd9995df2963\n" }, { "commit": "86c8752f64629325026945cd4eabd1dcea224acb", "tree": "9dc2be978f9e784a3ce16fa29d46941a94ac1c94", "parents": [ "f97a859e85f703644d897f0e3e1bc54315557aaa" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 11 16:55:55 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 19 08:26:46 2020 +0000" }, "message": "Direct calls to @CriticalNative methods.\n\nEmit direct calls from compiled managed code to the native\ncode registered with the method, avoiding the JNI stub.\n\nGolem results:\nart-opt-cc x86 x86-64 arm arm64\nNativeDowncallStaticCritical +12.5% +62.5% +75.9% +41.7%\nNativeDowncallStaticCritical6 +55.6% +87.5% +72.1% +35.3%\nart-opt x86 x86-64 arm arm64\nNativeDowncallStaticCritical +28.6% +85.6% +76.4% +38.4%\nNativeDowncallStaticCritical6 +44.6% +44.6% +74.6% +32.2%\n\nTest: Covered by 178-app-image-native-method.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nTest: testrunner.py --target --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nTest: aosp_cf_x86_phone-userdebug boots.\nTest: aosp_cf_x86_phone-userdebug/jitzygote boots.\nBug: 112189621\nChange-Id: I8b37da51e8fe0b7bc513bb81b127fe0416068866\n" }, { "commit": "6587d9110bd7f836e43db16f3f676da996218aef", "tree": "437d06a8e60fd70aaafaf2b167dfe636a303c68a", "parents": [ "1912a5c7b9400009e361b0db52da77cc78f1cd77" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jun 12 10:51:43 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 17 08:00:58 2020 +0000" }, "message": "ART: Simplify HRem to reuse existing HDiv\n\nA pattern seen in libcore and SPECjvm2008 workloads is a pair of HRem/HDiv\nhaving the same dividend and divisor. The code generator processes\nthem separately and generates duplicated instructions calculating HDiv.\n\nThis CL adds detection of such a pattern to the instruction simplifier.\nThis optimization affects HInductionVarAnalysis and HLoopOptimization\npreventing some loop optimizations. To avoid this the instruction simplifier\nhas the loop_friendly mode which means not to optimize HRems if they are in a loop.\n\nA microbenchmark run on Pixel 3 shows the following improvements:\n\n | little cores | big cores\narm32 Int32 | +21% | +40%\narm32 Int64 | +46% | +44%\narm64 Int32 | +27% | +14%\narm64 Int64 | +33% | +27%\n\nTest: 411-checker-instruct-simplifier-hrem\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py --target --optimizing --jit --interpreter\nTest: run-gtests.sh\n\nChange-Id: I376a1bd299d7fe10acad46771236edd5f85dfe56\n" }, { "commit": "9922f00cf68aac69209216a0726a45eb6338763c", "tree": "7e43b55e85ed17443af1c6be6532dafbb8550495", "parents": [ "16527e892b13c9e1fb34f8d2e9993e58a72ac662" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 15:05:15 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 09 10:03:58 2020 +0000" }, "message": "arm/arm64: Clean up intrinsic slow paths.\n\nGeneralize and use the slow path template IntrinsicSlowPath\nfrom intrinsics_utils.h.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boot image is unchanged.\nChange-Id: Ia8fa4e1b31c1f190fc5f02671336caec15e4cf4d\n" }, { "commit": "695348f4b0541f4373b46eac5830cdd87f71c076", "tree": "f2f6019f0c394f99aaaf9f2f7deec16bf6116b0f", "parents": [ "1f5300a211202442a07607830c6550773ca50b50" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 19 14:42:02 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 20 08:41:09 2020 +0000" }, "message": "Add compiler type to CompilerOptions.\n\nLet CompilerOptions hold the information whether it is AOT\nor JIT compilation, or Zygote JIT for shared code.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: aosp_taimen-userdebug boots.\nChange-Id: Id9200572406f8e43d99b8b61ef0e3edf43b52fff\n" }, { "commit": "0ddb338f084b1c46efbfa7a79ad6aa1b63a24ded", "tree": "e36eaa49dd79914622fff402f6ca2e829646c3fb", "parents": [ "8bcba2264f5ba66ef8820e3963e838a67bd6215f" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon May 18 11:15:46 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 15:10:40 2020 +0000" }, "message": "ARM64: Combine LSR+ADD into ADD_shift for Int32 HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nIn case of Int32 the multiplication is done into a 64-bit register\nhigh 32 bits of which are only used.\nThe multiplication result might need some ADD/SUB corrections.\nCurrently it is done by extracting high 32 bits with LSR and applying\nADD/SUB. However we can do correcting ADD/SUB on high 32 bits and extracting\nthose bits with the final right shift. This will eliminate the\nextracting LSR instruction.\n\nThis CL implements this optimization.\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I5ba557aa283291fd76d61ac0eb733cf6ea975116\n" }, { "commit": "1439e573517bb9f0b115aef5d3bbd9090751ebd6", "tree": "d6a1a4aed01719e988a8ac0fb81ed2843667d75f", "parents": [ "4be256069c494550037c81272ca4c27bd4a139df" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 12 12:43:09 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 18 09:11:30 2020 +0000" }, "message": "ART: Optimize ADD/SUB+ADD_shift into ADDS/SUBS+CINC for HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nThe multiplication result might need some corrections to be finalized.\nThe last correction is to increment by 1, if the result is negative.\nCurrently it is done with \u0027add result, temp_result, temp_result, lsr #31 or #63\u0027.\nSuch ADD usually has latency 2, e.g. on Cortex-A55.\nHowever if one of the corrections is ADD or SUB, the sign can be detected\nwith ADDS/SUBS. They set the N flag if the result is negative.\nThis allows to use CINC which has latency 1:\n adds temp_result, temp_result, dividend\n cinc out, temp_result, mi\n\nThis CL implements this optimization.\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: Ia6aac6771908e992c86e32fe1694a82bd1b7af0b\n" }, { "commit": "f91fc1220f1b77c55317ff50f4dde8e6b043858f", "tree": "3b8416a4fa9b9278d1114d4002485e0cb1c704bf", "parents": [ "33c091eaaa0febedc93cff820def75b122fde867" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 13 09:21:00 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 15 14:09:54 2020 +0000" }, "message": "Optimizing: Run gtests without creating the Runtime.\n\nThe only Optimizing test that actually needs a Runtime is\nthe ReferenceTypePropagationTest, so we make it subclass\nCommonCompilerTest explicitly and change OptimizingUnitTest\nto subclass CommonArtTest for the other tests.\n\nOn host, each test that initializes the Runtime takes ~220ms\nmore than without initializing the Runtime. For example, the\nConstantFoldingTest that has 10 individual tests previously\ntook over 2.2s to run but without the Runtime initialization\nit takes around 3-5ms. On target, running 32-bit gtests on\ntaimen with run-gtests.sh (single-threaded) goes from\n~28m47s to ~26m13s, a reduction of ~9%.\n\nTest: m test-art-host-gtest\nTest: run-gtests.sh\nChange-Id: I43e50ed58e52cc0ad04cdb4d39801bfbae840a3d\n" }, { "commit": "968db3c09e5059e30044d69f1a5fd9bcd937392e", "tree": "5496a327556b30ac2cd1877b515fa852688036bd", "parents": [ "2750a9884d7579f301c7ff65a6daaf8520af7902" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu May 07 12:44:10 2020 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 12 10:35:49 2020 +0100" }, "message": "ARM64: Combine LSR+ASR into ASR for Int32 HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nThe multiplication is done by multiplying 32-bit numbers into a 64-bit\nresult. The high 32 bits of the result are used. In case of Int32 LSR\nis used to get those bits. After that there might be correction\noperations and ASR. When there are no correction operations between LSR\nand ASR they can be combined into one ASR.\n\nThis CL implements this optimization.\n\nImprovements (Pixel 3):\n little core big core\n jit_aot/LoadCheck.RandomSumInvokeStaticMethod 7.1% 8.3%\n jit_aot/LoadCheck.RandomSumInvokeUserClass 4.6% 12.0%\n benchmarksgame/fasta 3.3% 1.0%\n benchmarksgame/fasta_4 2.4% 2.6%\n benchmarksgame/fastaredux 2.2% 2.2%\n SPECjvm2k8 MPEGAudio 1.7% 1.0%\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I5267b38d3a58319e24152917fabe836d5b346bce\n" }, { "commit": "a6653d304faa3bbd981507570a4ac1107760c6a7", "tree": "6dc333f6f19b932c0fd739b4862c3800b3a51b45", "parents": [ "4d0f795aaa9abd1b36e2704b3851b2cc39c70cdd" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 05 16:30:24 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 07 09:04:21 2020 +0000" }, "message": "ART: Refactor InstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant\n\nInstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant handles\nboth Int32 and Int64 cases. However Int32 cases can have additional\noptimizations. Having them in GenerateDivRemWithAnyConstant makes code\ndifficult to read.\n\nThis CL splits the code of GenerateDivRemWithAnyConstant to:\n* GenerateInt32DivRemWithAnyConstant\n* GenerateInt64DivRemWithAnyConstant\n* GenerateResultDivRemWithAnyConstant\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I267331c026e87d6a233b593586f1b74759382896\n" }, { "commit": "1a719e4de83532a1dcd9ddfad2c92d4130f28ea9", "tree": "445026effb3298ca8e962701ee01f65785be6fe6", "parents": [ "e33dca6d44463606168330d2f84bc616e8c147f6" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Jul 18 14:24:55 2019 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Mon May 04 08:19:17 2020 +0000" }, "message": "RFC: ARM64: Split arm64 codegen into scalar and vector (SVE and NEON).\n\nThis is a first CL in the series of introducing arm64 SVE support\nin ART. The patch splits the codegen functionality into scalar and\nvector ones and for the latter introduces NEON and SVE\nimplementations. SVE one currently is an exact copy of NEON one -\nfor the sake of testing and an easy diff when the next CL comes\nwith an actual SVE instructions support.\n\nThe patch effectively doesn\u0027t change any behavior; NEON mode is\nused for vector instructions, tests pass.\n\nTest: test-art-target.\nChange-Id: I5f7f2c8218330998e5a733a56f42473526cd58e6\n" }, { "commit": "c8150b5def82058c23df377a5006a78e7668afeb", "tree": "8f0e15b91cd55b978ca7f152206f0a550353810a", "parents": [ "b2028739a2db03623ed76f5028ede1333c48f4c9" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 31 18:28:00 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Apr 17 10:35:45 2020 +0000" }, "message": "ART: Refactor SIMD slots and regs size processing.\n\nART vectorizer assumes that there is single size of SIMD\nregister used for the whole program. Make this assumption explicit\nand refactor the code.\n\nNote: This is a base for the future introduction of SIMD slots of\nsize other than 8 or 16 bytes.\n\nTest: test-art-target, test-art-host.\nChange-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c\n" }, { "commit": "c1cd1330c65e8b9b13bcd93bd9634eed6453c5dc", "tree": "4fe4f02f8107e761f246745259260356a3bac12f", "parents": [ "08a1d1ba90c69e4b39f2df90eacee2c5413f8b4e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 25 13:08:24 2020 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 25 13:08:24 2020 +0000" }, "message": "Fix braino in arm64 codegen.\n\nPointers are 64bit there...\n\nBug: 148303458\nTest: 597-deopt-busy-loop\nChange-Id: Iee003f883665e4a668068b8e056380abc2f5fab4\n" }, { "commit": "796aa2cfcde9c88fa0a3176899e25bab3468ebd2", "tree": "9f4be44ef08e5abbdcb16ed6e8d15459bb743222", "parents": [ "57cacb720e6f995aa1a42df6e2e6470a9ec57261" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 10:20:05 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 11:31:30 2019 +0000" }, "message": "[baseline] Check that the profiling info is not null.\n\nZygote cannot allocate profiling infos.\n\nTest: 689-zygote-jit-deopt\nChange-Id: I85e8b7f16b81ba4de435a5417dbb2588c34414b0\n" }, { "commit": "57cacb720e6f995aa1a42df6e2e6470a9ec57261", "tree": "bb73a113c94bc397cd7c99a4c64e033bf29b9803", "parents": [ "013d1ee96b928f3bda9031e94d4a69f827133ce6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Dec 08 22:07:08 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 09:48:00 2019 +0000" }, "message": "Refactor OSR related code to prepare for \"true\" OSR.\n\n- Make the compiler restore all callee-save registers.\n- Make the compiler return any value in a core register: this simplifies\n the current stub, and will also avoid having to look at the return\n type (and reading the shorty) when returning to an nterp frame.\n- Add OsrData and offsets of its members to be used by nterp.\n\nTest: test.py\nBug: 27094810\nChange-Id: Ifa4f4877ab8b1f0c6a96feccea30c909942eb2fa\n" }, { "commit": "9b5271e53a76cbe3d269d1b70da7f13b9d944db1", "tree": "ff89e3a40d274e812f5727d7ff7930d19d447d35", "parents": [ "a00b54b74bee06c006b8bebfbef85e2801de293c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 04 14:39:46 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 04 14:39:46 2019 +0000" }, "message": "Get the baseline information from the graph.\n\nBaseline could be set by the compiler options or the JIT.\n\nTest: test.py\nBug: 119800099\nChange-Id: I702bd7642dfd3353c9ad99cb6ac425c090e16101\n" }, { "commit": "a59af8aeaad8fe7d68d8f8de63eab9cf85b6ab31", "tree": "83195c74b135731cc4555254763a8f449691c1b0", "parents": [ "5c8cc64b5f1580faf510f27527e7e22987174963" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 17:42:32 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 03 14:32:09 2019 +0000" }, "message": "JIT baseline: trigger optimized compilation on hotness threshold.\n\n- Add a new hotness count in the ProfilingInfo to not conflict with\ninterpreter hotness which may use it for OSR.\n- Add a baseline flag in the OatQuickMethodHeader to identify baseline\ncompiled methods.\n- Add a -Xusetieredjit flag to experiment and test.\n\nBug: 119800099\nTest: test.py with Xusetieredjit to true\n\nChange-Id: I8512853f869f1312e3edc60bf64413dee9143c52\n" }, { "commit": "20036d80f246b564331e0943aa07ec3b50fc15d9", "tree": "68c421f9da0c7ff7453ba5093203b94f9ec283c6", "parents": [ "36ec598a4d887746291d003c97c2cb28b5987768" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 28 16:15:00 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 28 17:16:57 2019 +0000" }, "message": "JIT baseline: don\u0027t update inline caches for intrinsics.\n\nWe already know the target.\n\nBug: 119800099\nTest: test.py --baseline\nChange-Id: I14cdafe233fec83a1f69e307326858c591309c34\n" }, { "commit": "e2a3aa988630b3c2952ac44943f03dde60454195", "tree": "acee7012af6e2b161c91e6cd8b7b4d12eb5aa927", "parents": [ "a2c4d61e482a15974e3e220bcd62a64043ee536f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 25 17:52:58 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 14:04:43 2019 +0000" }, "message": "Baseline JIT: update inline caches in compiled code.\n\nIn trying to remove profiling from interpreter, to speed up\ninterpreter performance.\n\nBug: 119800099\nTest: test.py --baseline\nChange-Id: Ica1fa41a889b31262d9f5691b30a31fbcec01b34\n" }, { "commit": "7d48dcd51db4b950c22ec78ef3caa53fdf4214d3", "tree": "72600968b1daf5682018880f20ca07610e62b8e7", "parents": [ "f05f04b429a63eb036f501866a863109f05b95b2" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Oct 16 12:46:28 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 31 14:56:52 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API\n\nVIXL has had FPRegister as an alias for VRegister for backward\ncompatibility. In the latest upstream VIXL the alias has been removed and all\nFPRegister based API has became VRegister based. As AOSP VIXL is being\nupdated to the latest upstream VIXL all uses of FPRegister based API\nmust be replaced with VRegister based API.\nThis CL moves ART from FPRegister based API to VRegister based API.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I12541c16d0557835ea19c8667ae18c6601359b05\n" }, { "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0", "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f", "parents": [ "e2727154f25e0db9a5bb92af494d8e47b181dfcf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n" }, { "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf", "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8", "parents": [ "c78860b91ae07eed92f86876e7a03132adea6fcd" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 10 10:46:42 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 08:22:00 2019 +0000" }, "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n - before:\n arm: 2396152\n arm64: 3345280\n - after:\n arm: 2016176 (-371KiB, -15.9%)\n arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n" }, { "commit": "2bb44fe818f2bf1d867a6ae490ef69c7f3a51e97", "tree": "c1860179daba52ab0d53707650c1e85194399629", "parents": [ "59770df741b87b201e83ef81cbcfac9df048d19b" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 04 12:28:14 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 09 08:25:22 2019 +0000" }, "message": "ARM64: Change code emitted by ClinitCheck.\n\nChange the code from MVN+CBNZ to CMP+BLO. The latter is\nbetter optimized in ARM64 CPUs. To avoid increasing code\nsize, this requires the preceding load to be changed from\nLDR to LDRB for a single byte of the 32-bit field.\n\nThis shows small but measurable improvement on a few Golem\nbenchmarks, for example MicroLambda, KotlinAutoReversiBench\nand KotlinImgProc-GaussianBlurOpt.\n\nTest: testrunner.py --target --optimizing\nBug: 36692143\nChange-Id: Ia73f791d7026220ef38e73bd5ee19fcc4877564d\n" }, { "commit": "988c3911671598d7c840c65bf1cdfafa1e05c582", "tree": "2ee476b2dbd75fa9c36cfdb28dbcede539eac195", "parents": [ "4bbc62ba98a74885dcc7fd21b468808774db5a8b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Sep 25 19:33:35 2019 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 01 12:20:13 2019 +0000" }, "message": "Fix null checks on volatile reference field loads on ARM64.\n\nART\u0027s compiler adds a null check HIR instruction before each field\nload HIR instruction created in the instruction builder phase. When\nimplicit null checks are allowed, the compiler elides the null check\nif it can be turned into an implicit one (i.e. if the offset is within\na system page range).\n\nOn ARM64, the Baker read barrier thunk built for field reference loads\nneeds to check the lock word of the holder of the field, and thus\nincludes an explicit null check if no null check has been done before.\nHowever, this was not done for volatile loads (implemented with a\nload-acquire instruction on ARM64). This change adds this missing null\ncheck.\n\nTest: art/test/testrunner/testrunner.py --target --64 -t 1004-checker-volatile-ref-load\nBug: 140507091\nBug: 36141117\nChange-Id: Ie94f2e73d2f439ae4460549d7b71848401602a21\n" }, { "commit": "7f8678ec4d2abec1f540fb441be60604bec86b6e", "tree": "e36b4d32dfc47fcebadf0ee5c7e4d1e3d51412a6", "parents": [ "84e5bb990d48263849bab132d80d753495bc7204" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Aug 30 16:22:28 2019 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Sep 06 18:40:59 2019 +0000" }, "message": "Revert^2 \"Prevent overflow for AOT hotness counters\"\n\nFixed bug where sbc usage was incorrect. sbc does -1 + carry.\n\nTest: test/run-test --always-clean --runtime-option -Xcheck:jni --64 674-hotness-compiled\nTest: test/run-test --always-clean --runtime-option -Xcheck:jni 674-hotness-compiled\nBug: 139883463\n\nThis reverts commit 7ab07777b08db86dda2891f3e7ae15df8f25a599.\n\nChange-Id: I6f8ac0320592a94314386b04cdb0c7e0e6da6994\n" }, { "commit": "7ab07777b08db86dda2891f3e7ae15df8f25a599", "tree": "1b0b2fa585e49e4a7913c09d67794763197c6490", "parents": [ "154445799432cb53d23cd011485132be07c39b5a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 30 08:26:59 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 30 08:57:20 2019 +0000" }, "message": "Revert \"Prevent overflow for AOT hotness counters\"\n\nThis reverts commit 79e6eb8b79be6249358b7801bc511290dacf10d0.\n\nBug: 139883463\n\nReason for revert: 674-hotness-compiled fails on target.\n\nChange-Id: I02fce74d70a4ae69dd5b4ae3924aa11728d9e16f\n" }, { "commit": "79e6eb8b79be6249358b7801bc511290dacf10d0", "tree": "1a04d214dd6223423abd442d8d9b0b61a3db2336", "parents": [ "bae88c0759d48acf29b58d960ad2665e3462dfda" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Aug 26 12:33:46 2019 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Aug 29 16:05:52 2019 +0000" }, "message": "Prevent overflow for AOT hotness counters\n\nPrevious, the addition did not have a check for overflow and might wrap\naround since the counter is only 16 bits.\n\nModified the test to exercise this.\n\nThe slowdown from fixing the overflow is 2% average on golem arm32/64.\nOverall this brings the slowdown from the counter to ~15% from ~13%.\n\nThe benchmarks that regress the most are loopy ones that I would\nconsider non-representative. Code size increases by 0.6%.\n\nBug: 139883463\nTest: test/run-test --host --64 --prebuild 674-hotness-compiled\nTest: test/run-test --host --prebuild 674-hotness-compiled\nTest: test/run-test --64 --prebuild 674-hotness-compiled\nTest: test/run-test ---prebuild 674-hotness-compiled\n\nChange-Id: Icf0ab2aedbc40ab10c9d952ce0f9c7b5e5feaf15\n" }, { "commit": "be53085e183be3edafdf03cac58624c87383e7e9", "tree": "7406d4ff01c6d01e82a9a5119e57968bd33fec1a", "parents": [ "5a75277056c8d528b0f68b7dbbb11609d0c91528" ], "author": { "name": "Georgia Kouveli", "email": "georgia.kouveli@linaro.org", "time": "Thu Jan 17 10:46:41 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Aug 14 08:20:56 2019 +0000" }, "message": "ARM64: Improve BoundsCheck for constant inputs.\n\nThis is a port of 2dd053d to ARM64.\n\nOriginal author: Georgia Kouveli \u003cgeorgia.kouveli@linaro.org\u003e\nCommitted by: David Horstmann \u003cdavid.horstmann@linaro.org\u003e\n\nTest: test-art-target, test-art-host\nTest: 1960-checker-bounds-codegen\nTest: 449-checker-bce\n\nChange-Id: I6564e4d147a0f40665b37c604487159a9d9aeae5\n" }, { "commit": "9df37b9f0fc2046ceabeea0d0638ac286bfc0f37", "tree": "7f1bf36d2373c6666c24f8a35509f929c7e16944", "parents": [ "92fc2c0241590e475a2a37c9864633b88f97b280" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Jul 23 16:41:54 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 31 08:16:27 2019 +0000" }, "message": "ART: ARM64: Fix saved fpu stack offsets for SIMD.\n\nFix the bug when a wrong stack offset was recorded for a FP\nsaved in a SlowPathCode: this happened when graph had SIMD\nloops and some regular FP registers live across a slow path.\n\nTest: test-art-target, test-art-host.\n\nChange-Id: I08b32c9877fcd468dafa6027c156e544d730f1f7\n" }, { "commit": "44ca0754b3c6f11303bac876a9175bbfa95609ef", "tree": "6f669466e6b0e750a075108cc6f8fe0a67b66658", "parents": [ "f3677471a58c2738a3d9dd05f07f01c18a5e61be" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 29 10:18:25 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 30 14:49:54 2019 +0000" }, "message": "Compiler changes for boot image extension.\n\nTest: m test-art-host-gtest\nTest: testrunnner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: run-gtest.sh\nTest: testrunner.py --target --optimizing\nChange-Id: I8e999c96ec908f26d8c529edc9d2a3be49a9379a\n" }, { "commit": "bf12191214c0d6215a98dfe846a51230d995dad9", "tree": "085c1059014ce66fdb7eceb6e8502d906f0eacbd", "parents": [ "78342419743cb6d0f17dc2d4c0cd99d18d9c83d6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 04 13:49:05 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 26 11:10:26 2019 +0000" }, "message": "Implement ClassStatus::kVisiblyInitialized.\n\nPreviously all class initialization checks involved a memory\nbarrier to ensure appropriate memory visibility. We change\nthat by introducing the kVisiblyInitialized status which can\nbe checked without a memory barrier. Before we mark a class\nas visibly initialized, we run a checkpoint on all threads\nto ensure memory visibility. This is done in batches for up\nto 32 classes to reduce the overhead.\n\nAvoiding memory barriers in the compiled code reduces code\nsize and improves performance. This is also the first step\ntoward fixing a long-standing synchronization bug 18161648.\n\nPrebuilt sizes for aosp_taimen-userdebug:\n - before:\n arm/boot*.oat: 19150696\n arm64/boot*.oat: 22574336\n oat/arm64/services.odex: 21929800\n - after:\n arm/boot*.oat: 19134508 (-16KiB)\n arm64/boot*.oat: 22553664 (-20KiB)\n oat/arm64/services.odex: 21888760 (-40KiB)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots\nTest: run-gtests.sh -j4\nTest: testrunner.py --target --optimizing\nTest: Manually diff `m dump-oat-boot` output from before\n with output after this CL without codegen changes,\n with `sed` replacements for class status. Check that\n only checksums and the oatdump runtime values of\n DexCache.dexFile differ.\nBug: 18161648\nBug: 36692143\nChange-Id: Ida10439d347e680a0abf4674546923374ffaa957\n" }, { "commit": "1a225a76ee6bc29833aee048b6cfae20242bdc8b", "tree": "069bfc01d827fcbf9aa4415c4d63d354648f396c", "parents": [ "323844002e54243e295497e7f829e46a533da621" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 05 13:37:42 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 18 13:37:15 2019 +0000" }, "message": "ARM/ARM64: Improve frame entry/exit codegen.\n\nOn ARM64, use STP pre-index for the method and the lowest\nspilled core register for method entry if there\u0027s no gap or\nFP spills in between. On exit, use LDP post-index to restore\nin this case, ignoring the method by loading to XZR. Thus,\nwe save one instruction for both entry end exit for such\nmethods and the performance should be the same or better.\n\nOn ARM, use a single PUSH/POP for method entry and core\nspills if the gap between them is 2 words or less and and we\nhave one or no FP spill, spill args as filler if needed. On\nexit, load the FP spill if any and do a single POP for core\nregisters and return in this situation, clobbering as many\nregisters from r2-r4 as needed; these caller-save registers\nare not used to pass return values. If we cannot do this\nbecause of FP spills but the gap between the method and FP\nspills is 2 words or less, we adjust SP and save the method\nin one PUSH after spilling; there is no similar handling\nfor method exit as the method does not need to be restored.\nThis may improve or degrade performance a bit depending on\nthe particular situation; in the worst case we PUSH/POP\nthree additional registers as a cost for smaller code size.\n\naosp_taimen-userdebug prebuils:\n - before:\n arm/boot*.oat: 19147484\n arm64/boot*.oat: 22558344\n oat/arm/services.odex: 21922256\n - after:\n arm/boot*.oat: 19105436 (-41KiB, -0.2%)\n arm64/boot*.oat: 22549624 (-9KiB, -0.04%)\n oat/arm/services.odex: 21914128 (-8KiB, -0.04%)\n\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nBug: 136144107\nChange-Id: Id36c67b4e735418fb18bcd3269b72b25695fbaa2\n" }, { "commit": "2d06e029b1c84916154b5960d2acd1c84706dc04", "tree": "31dca979adebd2ed3a058b23a12a3c91ce2874d1", "parents": [ "7cde45800e21c270945b43a8989334ffc7422c32" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 08 15:45:19 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 16 08:22:46 2019 +0000" }, "message": "Clean up linker patches in codegens.\n\nIn preparation for introducing boot image extension, make\nsure that we can use both kBootImageLinkTimePcRelative and\nkBootImageRelRo load kinds at the same time.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nChange-Id: I340f2d7d19e1c20699b37b0304d2e487d497da98\n" }, { "commit": "d5fd5c3bbb44880e440c6920ce5ed56b5383c788", "tree": "2cf8a6354e5509c5a5e0bc2937c24fe7e03a12b1", "parents": [ "1a6f9fcce199f437a5945dfe0163188b923adb28" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 02 14:46:32 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 04 08:17:30 2019 +0000" }, "message": "Make .bss stores atomic release operations.\n\nAnd rely on architecture-dependent behavior for the .bss\nentry loads.\n\nThis fixes theoretical races when one thread updates the\n.bss entry and another uses it immediately thereafter;\npreviously we did not ensure correct memory visibility.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nChange-Id: Ie7b7969eb355025b9c9205f8c936e702861943f4\n" }, { "commit": "f667508a2103cfafd1582df6aeea144490f1d11d", "tree": "7394cec1f1463a86deb75dcecca9f3eacd8ecb03", "parents": [ "8fa839cfe6f72adabdf79f938c57300e589e0803" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 17 12:05:28 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 23 11:47:28 2019 +0000" }, "message": "ARM/ARM64: Use trampolines for slow-path entrypoint calls.\n\nThis reduces the size of the generated code. We do this only\nfor AOT compilation where we get the most benefit.\n\nSizes of aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 19624804\n arm64/boot*.oat: 23265752\n oat/arm64/services.odex: 22417968\n - after:\n arm/boot*.oat: 19460500 (-160KiB)\n arm64/boot*.oat: 22957928 (-301KiB)\n oat/arm64/services.odex: 21957864 (-449KiB)\n\nTest: m test-art-host-gtest\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nBug: 12607709\nChange-Id: Ie9dbd1ba256173e4e439e8bbb8832a791965cbe6\n" }, { "commit": "8fa839cfe6f72adabdf79f938c57300e589e0803", "tree": "b940832441ef1b0c724c1383228225845e5d72d1", "parents": [ "3cddf4538a8df429a6084f7176c07d55e1e0ec67" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 12:50:47 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 23 11:47:28 2019 +0000" }, "message": "Revert^2 \"Improve ArraySet codegen.\"\n\nThis reverts commit 0dda8c84938d6bb4ce5a1707e5e109ea187fc33d.\n\nThe original change had two issues that have been fixed.\nFirst, for heap poisoning, the null branch skipped over the\nreference poisoning instructions which copy and poison the\nvalue, thus writing whatever was left in the register.\nSecond, the change erroneously assumed that the slow path\nperformed only the assignability check and bound the slow\npath exit label before the actual array store, unnecessarily\nre-doing the store.\n\nChange-Id: I9f380efa12aa807b4f566a932dbc9dae824fb25a\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: testrunner.py --target --optimizing\nTest: Repeat the above with\n ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue\nBug: 32489401\n" }, { "commit": "552a13415573da19eafa46e1ac00fb0eb68f2b23", "tree": "8cae5f3602d8f8e65cd3cbc349af17d785128605", "parents": [ "0dda8c84938d6bb4ce5a1707e5e109ea187fc33d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 31 10:56:47 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 14:44:09 2019 +0000" }, "message": "ART: Optimize StringBuilder append pattern.\n\nRecognize appending with StringBuilder and replace the\nentire expression with a runtime call that perfoms the\nappend in a more efficient manner.\n\nFor now, require the entire pattern to be in a single block\nand be very strict about the StringBuilder environment uses.\nAlso, do not accept StringBuilder/char[]/Object/float/double\narguments as they throw non-OOME exceptions and/or require a\ncall from the entrypoint back to a helper function in Java;\nthese shall be implemented later.\n\nBoot image size for aosp_taimen-userdebug:\n - before:\n arm/boot*.oat: 19653872\n arm64/boot*.oat: 23292784\n oat/arm64/services.odex: 22408664\n - after:\n arm/boot*.oat: 19432184 (-216KiB)\n arm64/boot*.oat: 22992488 (-293KiB)\n oat/arm64/services.odex: 22376776 (-31KiB)\nNote that const-string in compiled boot image methods cannot\nthrow, but for apps it can and therefore its environment can\nprevent the optimization for apps. We could implement either\na simple carve-out for const-string or generic environment\npruning to allow this pattern to be applied more often.\n\nResults for the new StringBuilderAppendBenchmark on taimen:\n timeAppendLongStrings: ~700ns -\u003e ~200ns\n timeAppendStringAndInt: ~220ns -\u003e ~140ns\n timeAppendStrings: ~200ns -\u003e 130ns\n\nBug: 19575890\nTest: 697-checker-string-append\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nTest: vogar --benchmark art/benchmark/stringbuilder-append/src/StringBuilderAppendBenchmark.java\nChange-Id: I51789bf299f5219f68ada4c077b6a1d3fe083964\n" }, { "commit": "0dda8c84938d6bb4ce5a1707e5e109ea187fc33d", "tree": "3d0b4f35ef4d00aa18eba0e417655d43bc44bf5a", "parents": [ "0ece86491008837a9814f7a2e0d7961c74ef4195" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 12:47:40 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 12:47:40 2019 +0000" }, "message": "Revert \"Improve ArraySet codegen.\"\n\nThis reverts commit 0ece86491008837a9814f7a2e0d7961c74ef4195.\n\nReason for revert: Breaks heap poisoning tests.\n\nBug: 32489401\nChange-Id: Ied4150829eea848d0f967866d87c6aa7dafd39a1\n" }, { "commit": "0ece86491008837a9814f7a2e0d7961c74ef4195", "tree": "590aa02d76255d9e9c4c1329b4a7278c4c8ff018", "parents": [ "3a8ab36cdfc9535bf79057cb9efe787ec8a491d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 13 11:49:17 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 08:23:57 2019 +0000" }, "message": "Improve ArraySet codegen.\n\nSimplify the reference case to emit fewer instructions and\ntake at most one branch in the main path.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: testrunner.py --target --optimizing\nBug: 32489401\nChange-Id: I9d76b7795ec01e6245ed3184cd8d384389e5070d\n" }, { "commit": "403aafa9f286e13ee2a64748514d33af39b55ab0", "tree": "fe9e5a5eed0081c2ac03dec0d616ed32d162b99c", "parents": [ "8809c9cd8d7f477e0a74f68537c864e3b7a35db3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 06 18:04:14 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 12 14:11:25 2019 +0000" }, "message": "Fix non-deterministic compilation for const-string...\n\n... in inlined methods that are not in the boot profile.\nIf such string is not in the boot image for other reasons,\ndo not resolve the string and use the kBssEntry load kind.\n\nBoot image sizes for aosp_taimen-userdebug:\n - before:\n arm/boot*.art: 12349440\n arm/boot*.oat: 19862024\n arm64/boot*.art: 16609280\n arm64/boot*.oat: 23568592\n - after:\n arm/boot*.art: 12324864 (-24KiB)\n arm/boot*.oat: 19936612 (+73KiB)\n arm64/boot*.art: 16580608 (-28KiB)\n arm64/boot*.oat: 23642120 (+72KiB)\n\nTest: aosp_taimen-userdebug boots.\nTest: m test-art-host-gtest\nBug: 26687569\nChange-Id: I3e0b72cd5e8c67904517856208f25a6c379ab601\n" }, { "commit": "3db70689e3e1c92344d436a8ea4265046bdef449", "tree": "3db08743e968062ed5bdc143233cdb3c4564696b", "parents": [ "1650dafad62578a1766bd617d78458a4cf1e2a9a" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Dec 26 15:12:03 2018 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Dec 27 12:56:39 2018 -0800" }, "message": "ART: Refactor for bugprone-argument-comment\n\nHandles compiler.\n\nBug: 116054210\nTest: WITH_TIDY\u003d1 mmma art\nChange-Id: I5cdfe73c31ac39144838a2736146b71de037425e\n" }, { "commit": "aa6f48362b3258a5df5e527987ffe7e068eb4a79", "tree": "0fa8cfbebb77d2e7796084721c836b44114bdc97", "parents": [ "8bda21f1d8bbc1060bf693f5d1666d3396d1cb69" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Nov 21 18:57:54 2018 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Dec 03 18:43:48 2018 +0000" }, "message": "ART: ARM64: Pass ISA features to VIXL macroassembler.\n\nVIXL macroassembler should be initialized properly\nto support Armv8.X features in order to emit corresponding\ninstructions.\n\nTest: codegen_test.cc, relative_patcher_arm64_test.\nTest: test-art-host, test-art-target.\nChange-Id: I2f9e155c28b4d2252a3cfb19717f5d25824d5e11\n" }, { "commit": "c1896c9a0e15df3a1b9a3a19bcd2a933b654fe06", "tree": "b68a5f5163f8da0da87d671a225addaa2a13095f", "parents": [ "f2970cd870948a6ee1c8ecd30c9c3147d05aa0be" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Nov 29 11:33:18 2018 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Nov 29 11:33:18 2018 -0800" }, "message": "C++17 compatibility: make WITH_TIDY\u003d1 happy again.\n\nBug: http://b/111067277\nTest: builds\nChange-Id: I8b69ea3815e14bb6eb27f40c0dd01a85b340a355\n" }, { "commit": "57e7dbfbe34188de05f90bb0ec8520ba66383149", "tree": "1dbbfaa1d0afbc44cbb429ba72b65db37efd8ed6", "parents": [ "4fc843c4fc9f33c4ba49c1303d526d0e0e6a3788", "0806f589a8a8e1fca573069b37761c320660aa63" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 06 17:13:01 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Nov 06 17:13:01 2018 +0000" }, "message": "Merge \"ARM64: Support interm. address for object arrays.\"" }, { "commit": "0806f589a8a8e1fca573069b37761c320660aa63", "tree": "51a26fc5e59cca70a3f6875ece57aee39962221f", "parents": [ "02338775e33b553be51d44ff60bb1ef8e527bd94" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 11 20:14:20 2018 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 25 18:33:55 2018 +0100" }, "message": "ARM64: Support interm. address for object arrays.\n\nSupport IntermediateAddress on arm64 for object\narray reads in Baker read barrier configuration.\n\nThe patch brings minor boot.oat size reduction and\nperformance improvement on Puzzle benchmark.\n\nTest: test-art-target, test-art-host, gc_stress.\nTest: 527-checker-array-access-split.\n\nBug: 26601270\nBug: 32578862\n\nChange-Id: I781a911905038b36428964a990771fdf74e99bbd\n" }, { "commit": "fe89f170fd454188902ae0b80e08c0888158c60e", "tree": "3862cd1e16d25696505da841c127f13e0e08fdfd", "parents": [ "5314caec5a2c61fa96a2d6ee134706c085c18b11", "bd8e10c586fca1c99f29eff27f66d483a18b0ccf" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 25 11:51:43 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 25 11:51:43 2018 +0000" }, "message": "Merge \"Block the platform register, x18.\"" }, { "commit": "b546163926889130354ccdbcccb80c0331c13f3c", "tree": "b4a3fb30e11e2abc671fb0b4b8098acd8fc49ce2", "parents": [ "8db807252e1d4d0bab7785be231e20a1e5fd8e74" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 15 14:24:21 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 16 10:47:24 2018 +0100" }, "message": "Fix HNewArray with unresolved primitive array type.\n\nAnd enable test 920-objects that was crashing because\nof this bug.\n\nTest: testrunner.py --host --jit-on-first-use -t 920\nTest: testrunner.py --host --optimizing\nTest: m test-art-host-gtest\nBug: 117638896\nChange-Id: I47dc893b121c82de537b3147c86d37a6eecf2d62\n" }, { "commit": "a2da9b99fa1ea3d25d52da71308a623b2aae216c", "tree": "5533be23eee7c24b68b1b72272cbae3f35a708cb", "parents": [ "dc3b4670b170b39a8bd6498d4de69c1513af1db2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 10 14:21:55 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 10 15:25:26 2018 +0100" }, "message": "ART: Completely remove the --compile-pic option.\n\nAnd the PIC-related fields from image header.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 77856493\nChange-Id: I3787369378f12d8cd9003bebeae62830a67def33\n" }, { "commit": "bdb2ecc8cfd0d6fc2f3f4fa4c65cca84b358cd61", "tree": "a7660c98c22d28bf508fe208845957418e0dee40", "parents": [ "4bd4d2c199c9e0e522526c40303652e29bc7c631" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 18 14:33:55 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 19 14:46:04 2018 +0100" }, "message": "Remove sharpening as an optimization pass.\n\nMake the last sharpening helper (methods) like the other\nhelpers: being invoked by the instruction builder.\n\nTest: test.py\nChange-Id: Ic80a454f9b59b0b4ef7825590b24402500ba851c\n" }, { "commit": "bd8e10c586fca1c99f29eff27f66d483a18b0ccf", "tree": "ac228db5c0a3cbcc82c665bd2c1653d7e351c09e", "parents": [ "4613c8a3a549213240f3ffc46514b600d872938e" ], "author": { "name": "Peter Collingbourne", "email": "pcc@google.com", "time": "Thu Apr 12 16:39:55 2018 -0700" }, "committer": { "name": "Peter Collingbourne", "email": "pcc@google.com", "time": "Thu Sep 06 01:18:33 2018 +0000" }, "message": "Block the platform register, x18.\n\nBug: 77982665\nTest: run-libcore-tests.sh, sailfish boots\nChange-Id: I5bc4c77f76bb6747a002bff2e16d83c679beeb32\n" }, { "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403", "tree": "0fbce767bc383358cf4cd65aafc74140e1850982", "parents": [ "19379b58bd433da91230e4fe6cd96e7416d16adc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 24 16:58:47 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 28 11:06:07 2018 +0100" }, "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n" }, { "commit": "75eec5d14039d4cbc4ec9b96485b743573665627", "tree": "db9e4158d5cbfb84d2f0c0f6157e5b0edad8587a", "parents": [ "d3678dc2531f95ced2d015b800ecd9018ce96c73", "61ba8d2421a98e9b16510be4f9af7ca7bc4c9055" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 24 14:07:24 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 24 14:07:24 2018 +0000" }, "message": "Merge \"Fix longstanding bug around implicit NPEs and GC, version 2.\"" }, { "commit": "61ba8d2421a98e9b16510be4f9af7ca7bc4c9055", "tree": "9a79331dd5ebd46ed46f853b24ab072f43debf28", "parents": [ "eb369ce3669be74dd89b21f8b3ab31ace4a47086" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Aug 07 09:55:57 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Aug 20 17:18:31 2018 +0100" }, "message": "Fix longstanding bug around implicit NPEs and GC, version 2.\n\nThe TODO has been there since M (so forever :)):\nhttps://android-review.googlesource.com/c/platform/art/+/122794/13//COMMIT_MSG#13\n\nWe hardly see the issue in our tests as we need to have:\n1) A GC happening while creating the NPE object.\n2) ParallelMoves between the NullCheck and implicit null check operation\n that moves references.\n\nThe CL piggy backs on the \"IsEmittedAtUseSite\" flag, to set implicit\nnull checks with it. The liveness analysis then special cases implicit\nnull checks to record environment uses at the location of the actual\ninstruction that will do the implicit null check.\n\nTest: test.py --gcstress\nTest: run-libcore-tests --gcstress\nbug: 111545159\nChange-Id: I3ecea4fe0d7e483e93db83281ca10db47da228c5\n" }, { "commit": "14e5a29a8c5dcd971376a4a04b3c3b05100b3f86", "tree": "81c607cde36b6481ed2cd2d8b41293f62a5521f8", "parents": [ "e0943873483cb2169e5360e1f746931a3371aa24" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 28 12:00:56 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 18:01:43 2018 +0100" }, "message": "Rename art::ReadBarrier::WhiteState as art::ReadBarrier::NonGrayState.\n\nThe read barrier state recorded in object\u0027s lockword used to be a\nthree-state value (white/gray/black), which was turned into a\ntwo-state value (white/gray), where the \"black\" state was conceptually\nmerged into the \"white\" state. This change renames the \"white\" state\nas \"non-gray\" and adjusts corresponding comments.\n\nTest: art/test.py\nChange-Id: I2a17ed15651bdbbe99270c1b81b4d78a1c2c132b\n" }, { "commit": "e0943873483cb2169e5360e1f746931a3371aa24", "tree": "c5fdf8d02f8bb23218513c9159090ff783df0ef0", "parents": [ "6e1faf4af246ebfb05505cebd8ca0db48aa3bae6", "c73f05242a6688c8edec46c1ff257a1efbd4b519" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 16:55:40 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 14 16:55:40 2018 +0000" }, "message": "Merge \"Document the use of the biased card table in ART\u0027s code generators.\"" }, { "commit": "94796f8e1b1d920c6107ffddf4efdabcf85e1da4", "tree": "e6c068b622bc60b1570eb1c54d3ddeea4972b1a2", "parents": [ "248141f724cbb9d436f13181b5301172c4385cc2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 08 15:15:33 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 14 16:36:39 2018 +0100" }, "message": "ARM64: Reimplement the UnsafeCASObject intrinsic.\n\nFor the UnsafeCASObject with Baker read barriers, drop the\nold code updating the field. Perform the main path CAS loop\nand redirect the flow for failure to a slow path that marks\nthe old value and compares it with the expected value (if\nnot marking, this is just a few instructions to determine\nthat they differ). If it\u0027s the same, the old value is known\nto be the from-space reference to the expected object and\nthe slow path performs a modified CAS loop checking for both\nexpected object references (from-space and to-space).\n\nTest: Already covered by the 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --64\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing --64\nBug: 36141117\nChange-Id: I175806dbc003640c9bb6759be6788311bcc9310c\n" }, { "commit": "c73f05242a6688c8edec46c1ff257a1efbd4b519", "tree": "68b95952ec9710da3aabf7a686725692a9fd5cf5", "parents": [ "9e113dd00d94526d7e6e546ac9bd4f066db3a019" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 15:16:50 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 15:20:33 2018 +0100" }, "message": "Document the use of the biased card table in ART\u0027s code generators.\n\nTest: n/a\nChange-Id: Ie03a6f6dc87fd0766fc2b685ec39a0a0ebe3fb57\n" }, { "commit": "248141f724cbb9d436f13181b5301172c4385cc2", "tree": "8828a0e319fa692c4a80e8cecadff7b68a845faa", "parents": [ "6e99db490fabbc38d96cc618a7aa82a99b3d07cf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 10 10:40:07 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 10 13:05:12 2018 +0100" }, "message": "ARM/ARM64: Introspection Baker RB for intrinsics.\n\nNamely Unsafe.getObject/-Volatile().\n\nTest: Additional tests in 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing\nBug: 36141117\nChange-Id: I7305d75ab0ae8c9621843f9a382ad3a5e0aefa0b\n" }, { "commit": "0ecac681bd0f55fad16027fe341f55edd632e3db", "tree": "016727b357ef37b9be41451359f5ca1c1edea8dd", "parents": [ "008e09f35541bcce782cd172d0745b802a720033" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 07 10:40:38 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 07 16:27:17 2018 +0100" }, "message": "ARM64: Introspection Baker RB for volatile fields.\n\nTest: Already covered by 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit --64\nBug: 36141117\nChange-Id: I2f9a707587d1ee27c0efb19d77becba7ec7ffec4\n" }, { "commit": "008e09f35541bcce782cd172d0745b802a720033", "tree": "8a75f77ac9f24196763038a53208266d70e3b584", "parents": [ "f5705e3502183e6dfd03facada5f5cbfab116ec7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 06 15:42:43 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 06 18:05:05 2018 +0100" }, "message": "ARM/ARM64: Clean up Baker RB introspection codegen.\n\nRemove the guard flags and remove unused code.\n\nAvoid unnecessary temporaries for JIT. This was missed in\n https://android-review.googlesource.com/725705\n\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit\nBug: 36141117\nChange-Id: Ic1bdc640db3f18d7169b0e62644f190e65a98d38\n" }, { "commit": "a21eca6a7ddc7f986651261359f821771494c61e", "tree": "5afeffa6ea8384ab50e3e4f87c6b76d195b13134", "parents": [ "d925742e6c52237a262b4430f8b6b679ff1cc80e", "966b46fcba43764267069b6e19bcb2a092260418" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 16:41:58 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 03 16:41:58 2018 +0000" }, "message": "Merge \"Revert^2 \"ARM/ARM64: Use introspection marking for JITted code.\"\"" }, { "commit": "9d479254d0dc4043a15ab26205f40439eca15493", "tree": "af8a9c9c6f2c28e723a971c9d39c9d1cebd1f814", "parents": [ "ca20fb6cc4dda392e63bdc8ec9de54d89793373e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 24 11:35:20 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 11:43:30 2018 +0000" }, "message": "Rename type resolution entrypoints.\n\nRename the InitializeType and InitializeTypeAndVerifyAccess\nentrypoints to Resolve* to better match their semantics.\nKeep the InitializeStaticStorage name for now as the most\nappropriate name InitializeType would clash with the old\nname of the ResolveType entrypoint.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: Ide55b58c490d085ab37d8536f90699f7ed571d59\n" }, { "commit": "966b46fcba43764267069b6e19bcb2a092260418", "tree": "fe89667cbb09a981e67ebd1196d324038a6413ff", "parents": [ "98afa11c3cd8517bd28d1cad7aacaf0179c905f0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 10:20:19 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 12:35:34 2018 +0100" }, "message": "Revert^2 \"ARM/ARM64: Use introspection marking for JITted code.\"\n\nThis reverts commit 756e722c323c69a7c9891892602730e9c94b78f9.\n\nFix the introspection code to avoid avoid macro instructions\nfor unpoisoning references inside ExactAssemblyScope.\n\nChange-Id: I6effadb84de74aba0236ab84b52ca85770daf5be\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit\nTest: ART_HEAP_POISONING\u003dtrue m test-art-target-gtest\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing --jit\nBug: 36141117\n" }, { "commit": "3232dbb6df866985089b13a36c56e2b39dd473ab", "tree": "055f3e8888bfb3cfd072a981e4733cfaad7b202c", "parents": [ "b27d874ebc0c067d96994a6ebe3c10eaeb2e4a75" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 25 15:42:46 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 08:59:07 2018 +0000" }, "message": "Do not save/restore regs in ClinitCheck slow path.\n\nThe entrypoint is kSaveEverything, so the only register that\nneeds to be saved is the argument/return value register.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16811692\n arm64/boot*.oat: 19801032\n oat/arm64/services.odex: 20232208\n - after:\n arm/boot*.oat: 16798804 (-12.6KiB, -0.08%)\n arm64/boot*.oat: 19804392 (+3.3KiB, +0.02%)\n oat/arm64/services.odex: 20227784 (-4.3KiB, -0.02%)\nNote that though there is less code, the metadata for the\narm64/boot*.oat outweighs the code size reduction because of\nthe register map encoding as value+shift introduced in\n https://android-review.googlesource.com/695682\nwhich it\u0027s ill-suited for kSaveEverything entrypoints. We\nshould reconsider that encoding.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nChange-Id: I5cd1deb90332a3b88a0a59d87925c557d9bff1ab\n" }, { "commit": "b27d874ebc0c067d96994a6ebe3c10eaeb2e4a75", "tree": "3084a0b326e98115f5d0621362d5b7c368775669", "parents": [ "8f5992d8c81d4d9a0805c649cdcf859328d5c1b6", "a9f303c089aa2b2fc82d97201352945678ef54ae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 08:57:16 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 03 08:57:16 2018 +0000" }, "message": "Merge \"Rewrite Class init entrypoint to take a Class arg.\"" }, { "commit": "756e722c323c69a7c9891892602730e9c94b78f9", "tree": "a2bf360d95f0aef84f3bce43f43871910a0b7ed9", "parents": [ "450f1d0fa0c40198e63c3e016f02e40ac854b0cb" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 02 17:53:46 2018 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 02 17:53:46 2018 +0000" }, "message": "Revert \"ARM/ARM64: Use introspection marking for JITted code.\"\n\nThis reverts commit 450f1d0fa0c40198e63c3e016f02e40ac854b0cb.\n\nReason for revert: breaks poisoning configuration\n\nBug: 36141117\nChange-Id: I198c20ca1db6d7d7602aa5318616e2b149de8772\n" }, { "commit": "a9f303c089aa2b2fc82d97201352945678ef54ae", "tree": "0df0eb5294a3ee72aea8ca670762c02ca9ffa8dd", "parents": [ "1bfd891d06e276d602b4a6ccf1a9f70967195218" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 20 16:43:56 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 02 17:41:21 2018 +0100" }, "message": "Rewrite Class init entrypoint to take a Class arg.\n\nFixes invalid type index being passed to the entrypoint for\nclass init check across dex files when the target type does\nnot have a TypeId in the compilation unit\u0027s DexFile.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16782748\n arm64/boot*.oat: 19764400\n oat/arm64/services.odex: 20162432\n - after:\n arm/boot*.oat: 16811692 (+28.3KiB, +0.17%)\n arm64/boot*.oat: 19801032 (+35.8KiB, +0.19%)\n oat/arm64/services.odex: 20232208 (+68.1KiB, +0.35%)\nThis increase comes from doing two runtime calls instead of\none for HLoadClass/kBssEntry that MustGenerateClinitCheck().\n\nTest: Additional test in 476-clinit-inline-static-invoke\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --jvm\nBug: 111433619\nChange-Id: I2fccd6944480ab4dac514f60d38e72c1014ae7b2\n" }, { "commit": "450f1d0fa0c40198e63c3e016f02e40ac854b0cb", "tree": "0606a5c722be0d706242c015cb1218021c5c1309", "parents": [ "da6220a29fae95f17edd5374dc6bc2d4870a84da" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 25 17:27:45 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 25 18:34:19 2018 +0100" }, "message": "ARM/ARM64: Use introspection marking for JITted code.\n\nImpact on Golem benchmarks is within noise.\n\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nBug: 36141117\nChange-Id: Idf5177ee5cd34e2034d298a7907240b3e3e12d82\n" } ], "next": "bd39d145e4986217bcb8dce1d4a9631d926a2781" }