)]}' { "log": [ { "commit": "a5c529fd866309856a1eaff009f781ffe266b499", "tree": "1a79af82e61b26de98a6d03fbb81e2fc5db12a93", "parents": [ "b50ceebb814f28a6ade94974d3e8614c8585760e" ], "author": { "name": "Ulya Trafimovich", "email": "skvadrik@google.com", "time": "Mon Jul 12 15:34:43 2021 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Mon Jul 12 16:25:08 2021 +0000" }, "message": "x86_64: Allow test to skip register pairs. Fix XCHG and enable tests.\n\nPreviously tests were disabled for `xchgl reg, reg` variant with all\nregister pairs, although the problematic case is only `xchg eax, eax`.\n\nThis commit allows one to pass an exception list to a testing function\nand skip the problematic register pairs instead of disabling the whole\ntest. The patch adds exception lists to all testing functions that run\nover register pairs, although XCHG only needs it for `Repeatrr`.\n\nEnabling the test revealed a few small errors in the XCHG implementation\n(namely, source and destination registers were swapped, which does not\naffect the result). This commit fixes the implementation so that the\ntests pass.\n\nBug: 65872996\nTest: m test-art-host-gtest\nChange-Id: Iaa759861330bcfb30db1a8219b805cc479cc3280\n" }, { "commit": "d6e14e0b6a3447d6e89a93d0a017e92b11dc5f6f", "tree": "4e30db113ef4352874e57022a654b341e71f1a92", "parents": [ "be7fe3b5466e10c4c49f027f10a801e1a4a9216c" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Jul 01 13:19:17 2020 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Jul 09 13:21:59 2020 +0000" }, "message": "Rewrite assembler_test_base.h\n\nSimplify the code in preparation of move to LLVM prebuilt tools.\n\nBug: 147817558\nTest: m test-art-host-gtest\nChange-Id: Iba277235255fd7d7f0965749b0b2d4a9567ced1f\n" }, { "commit": "0a17b6a0e705e45cf47407d0573ef8a7fd67cd99", "tree": "9b864aae8d952fc0ee2829672220774c91494303", "parents": [ "b7f4d0f15f02224ce5048ba566b2dce193ee103a" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Jul 01 11:29:47 2020 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Jul 01 12:41:06 2020 +0000" }, "message": "Revert \"Support running of host gtests in eng-prod\"\n\nThis reverts commit 22872da653053bb4b86fbef67163a9f6b7aee25b.\n\nReason for revert: Checking if this CL is cause of b/160132136\n\nBug: 147817558\nBug: 160132136\nChange-Id: Ifb6f2292292a7f69fbd0f2e9204fd37dbca84277\n" }, { "commit": "22872da653053bb4b86fbef67163a9f6b7aee25b", "tree": "5355ac349eeb15165c6db0c17e93f1286c52a3d4", "parents": [ "11303f2983bf2ef8d55870afcd0d5937f0778753" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Jun 25 15:23:15 2020 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Jun 26 17:14:57 2020 +0000" }, "message": "Support running of host gtests in eng-prod\n\nAdd more libraries and tools to the shared ART directory in testcases.\n\nChange the tests environment setup, so that it can find the tools.\n\nVast majority of tests pass. Some individual tests still need fixing.\n\nBug: 147817558\nTest: run gtests in forrest\nChange-Id: I3214f532436828c2a1a5a543e69d6b9bcf1e42af\n" }, { "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403", "tree": "0fbce767bc383358cf4cd65aafc74140e1850982", "parents": [ "19379b58bd433da91230e4fe6cd96e7416d16adc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 24 16:58:47 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 28 11:06:07 2018 +0100" }, "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n" }, { "commit": "3215fff7ef8fa3c2250b91158560eacc613a4671", "tree": "50d6fe7aff3f8fae31dcf2ca020f5079f49a592f", "parents": [ "6371249ce05032db5d8c4c7ec96bf7fd7264c42f" ], "author": { "name": "David Sehr", "email": "sehr@google.com", "time": "Tue Apr 03 17:10:12 2018 -0700" }, "committer": { "name": "David Sehr", "email": "sehr@google.com", "time": "Wed Apr 04 14:47:57 2018 -0700" }, "message": "Separate Malloc and MemMap ArenaPools\n\nMake ArenaPool an abstract base class and leave MallocArenaPool\nimplementation with it. This enables arena_allocator to be free\nof MemMap, Mutex, etc., in preparation to move the remaining collections\nout of runtime/base to libartbase/base.\n\nBug: 22322814\nTest: make -j 50 test-art-host\n build and boot\n\nChange-Id: Ief84dcbfb749165d9bc82000c6b8f96f93052422\n" }, { "commit": "2ffb703bf431d74326c88266b4ddaf225eb3c6ad", "tree": "0552c3c76a42b18f9e7460d501fb71a6dc2e7f33", "parents": [ "c4b6f3116f15c8e4fdf2e4f604ababdee12d8923" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Wed Nov 08 13:35:21 2017 -0800" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Wed Nov 08 15:15:52 2017 -0800" }, "message": "cpplint: Cleanup errors\n\nCleanup errors from upstream cpplint in preparation\nfor moving art\u0027s cpplint fork to upstream tip-of-tree cpplint.\n\nTest: cd art \u0026\u0026 mm\nBug: 68951293\nChange-Id: I15faed4594cbcb8399850f8bdee39d42c0c5b956\n" }, { "commit": "3309c01e55821f693e3b9cec0ef24969edf2528f", "tree": "cacb4a3775166297b1c9bb9e6236ab901ad725d4", "parents": [ "24276374dcaf95bfc52be2b8193eb4e337de62e4" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Fri Oct 13 14:34:32 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Oct 19 11:24:55 2017 +0200" }, "message": "MIPS: Introduce a few MSA instructions\n\nThese instructions are needed for SIMD reduction.\nAlso added assembler tests for each instruction.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18\n" }, { "commit": "69d310e0317e2fce97bf8c9c133c5c2c0332e61d", "tree": "fba05a1530e6fc4a2e6950303c1f7c6b0ffbb936", "parents": [ "e764d2e50c544c2cb98ee61a15d613161ac6bd17" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 09 14:12:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 11 09:44:26 2017 +0100" }, "message": "Use ScopedArenaAllocator for building HGraph.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n BatteryStats.dumpCheckinLocked() : 21.1MiB -\u003e 20.2MiB\n BatteryStats.dumpLocked(): 42.0MiB -\u003e 40.3MiB\nThis is because all the memory previously used by the graph\nbuilder is reused by later passes.\n\nAnd finish the \"arena\"-\u003e\"allocator\" renaming; make renamed\nallocator pointers that are members of classes const when\nappropriate (and make a few more members around them const).\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 64312607\nChange-Id: Ia50aafc80c05941ae5b96984ba4f31ed4c78255e\n" }, { "commit": "e764d2e50c544c2cb98ee61a15d613161ac6bd17", "tree": "112aa7ca459d2edb4f800897060a2407fcc622c7", "parents": [ "ca6fff898afcb62491458ae8bcd428bfb3043da1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 05 14:35:55 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 09 10:39:22 2017 +0100" }, "message": "Use ScopedArenaAllocator for register allocation.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n BatteryStats.dumpCheckinLocked() : 25.1MiB -\u003e 21.1MiB\n BatteryStats.dumpLocked(): 49.6MiB -\u003e 42.0MiB\nThis is because all the memory previously used by Scheduler\nis reused by the register allocator; the register allocator\nhas a higher peak usage of the ArenaStack.\n\nAnd continue the \"arena\"-\u003e\"allocator\" renaming.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 64312607\nChange-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01\n" }, { "commit": "f7754e861f0dec2d4772d61102fa93252258f672", "tree": "fdd1a2b81468a8310eae93c070b0ad2a6e290767", "parents": [ "b407afe983f8b106a5007d07aa2523ffc6525018" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Sep 20 10:33:06 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Sep 20 10:35:21 2017 -0700" }, "message": "Add more repeat support and register views.\n\nRationale:\nThis enables exhaustive testing of instructions\nthat use various memory addressing modes and\nregister views (full, half, quarter, etc.).\n\nBug: 18380245\nBug: 18380559\nBug: 18380348\n\nTest: assembler_x86[_64]_test\nChange-Id: I598c3e35a4791166ab629479ccb969ef3c6494b8\n" }, { "commit": "caa31e732bc9bb0007c39c504b109a4867ee5dd9", "tree": "1ed4201e4b76f52b2354c0186c58c693093dacdc", "parents": [ "5809417697955005751d60498964f6d4bd4a096f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Sep 14 17:08:50 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Sep 15 11:05:56 2017 -0700" }, "message": "Add repeat support for memory addresses.\n\nRationale:\nThis enables exhaustive testing of instructions\nthat use memory addresses. First use case of\nthe generics is x86.\n\nBug: 18380245\nBug: 18380559\nBug: 18380348\n\nTest: assembler_x86[_64]_test\n\nChange-Id: Ib0ad6fa65477b0c6fc04642ff980a4b9543d16d5\n" }, { "commit": "5dafb3c796b16718ff0599ea46277f291aee190d", "tree": "18f82de4ebfc982db30796607ec4949bbd5a663b", "parents": [ "6b411fc9fd94da3c552d8b96cee14f6414e7b734" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Sep 13 13:10:12 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Sep 13 14:12:18 2017 -0700" }, "message": "Test assembler driver utilities.\n\nRationale:\nQuis custodiet ipsos custodes?\n\nTherefore, it is good to make sure that the drivers\nused to test the assembler are doing what is expected.\nThis also prepares some upcoming improvements wrt.\naddressing modes and different register sizes.\n\nBug: 18380245\nBug: 18380559\nBug: 18380245\n\nTest: assembler_x86[_64]_test\n\nChange-Id: Iadc269c14cb9e15941ec66c362d59d42e9017001\n" }, { "commit": "8cf9cb386cd9286d67e879f1ee501ec00d72a4e1", "tree": "88e86e214b425e444760fe4e0ffeee677e1558a2", "parents": [ "914b7b6a6c9f399b26b41e9160e9871ef749e0db" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 19 09:28:38 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jul 24 16:07:10 2017 -0700" }, "message": "ART: Include cleanup\n\nLet clang-format reorder the header includes.\n\nDerived with:\n\n* .clang-format:\n BasedOnStyle: Google\n IncludeIsMainRegex: \u0027(_test|-inl)?$\u0027\n\n* Steps:\n find . -name \u0027*.cc\u0027 -o -name \u0027*.h\u0027 | xargs sed -i.bak -e \u0027s/^#include/ #include/\u0027 ; git commit -a -m \u0027ART: Include cleanup\u0027\n git-clang-format -style\u003dfile HEAD^\n manual inspection\n git commit -a --amend\n\nTest: mmma art\nChange-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02\n" }, { "commit": "3f44403fb5b6c9c6176339ab5888e97d0b617746", "tree": "765e3d3968b48fa5236177905fa57c5b60e57653", "parents": [ "bb75449355575a4b1ae72147b80cc7b225092149" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:20 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:55 2017 +0200" }, "message": "MIPS64: Add ldi.df MSA instruction\n\nAlso fixes RepeatTemplatedRegisterImmBits template.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Ib23f8a65ba924623f8c3a2d75d4ec4491d18feb0\n" }, { "commit": "5a9e51d39ed3d1015f20b3d12b35747612cca40e", "tree": "17d4d1e616d5a516dc8187f165fc68ee97ada185", "parents": [ "8f2b925473cfdc7650cef407102957befe0c6bb5" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Mar 16 16:11:43 2017 +0000" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 17 11:17:49 2017 +0100" }, "message": "Revert \"Revert \"Introduce a number of MSA instructions for MIPS64\"\"\n\nThis reverts commit 219bf253e5158c4f3438e70864b8bf7235c1e193.\n\nFixed memory leak in assembler_mips64_test.cc.\n\nTest: mma valgrind-test-art-host-gtest-assembler_mips64_test64\n\nChange-Id: I238833fd4555623c2716432fc67eab7696f1e28e\n" }, { "commit": "219bf253e5158c4f3438e70864b8bf7235c1e193", "tree": "0ba845434b3b5679ee62b099c42ad455b4dcc37d", "parents": [ "dcabc8b740bf3066d59348ffdf21c164d2b27cb4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "message": "Revert \"Introduce a number of MSA instructions for MIPS64\"\n\nThis reverts commit dcabc8b740bf3066d59348ffdf21c164d2b27cb4.\n\n\nReason:\nFAILING TESTS\nvalgrind-test-art-host-gtest-assembler_mips64_test32\nninja: build stopped: subcommand failed.\n19:36:36 ninja failed with: exit status 1\nmake: *** [run_soong_ui] Error 1\n\nChange-Id: If658375528d2a0f34bb6b22b6565fab1d863b3f5\n" }, { "commit": "dcabc8b740bf3066d59348ffdf21c164d2b27cb4", "tree": "1b16fe71dc17f5e3fad5e1f6a865141b5d22da6b", "parents": [ "96cc0a004b5685d8a3fea3cee3105fbbff73437f" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 10 11:53:48 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Mar 14 17:21:19 2017 +0100" }, "message": "Introduce a number of MSA instructions for MIPS64\n\nAdded a number of MSA (The MIPS SIMD Architecture) instructions.\nAdded assembler tests for each instruction.\nMade necessary changes in disassembler for these instructions.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I380f02c6ae5424a96ad999037153228acb07a108\n" }, { "commit": "e36605910cb13da1440fb9d7a8293842a9209c97", "tree": "6bb2097042a3ee4f0e0b64c4e22575823ca82c11", "parents": [ "b487af4fc80ffabe0219657a9690be1316dab8e7" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 09 11:13:42 2016 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Dec 02 16:22:56 2016 -0800" }, "message": "MIPS64: java.lang.String.getChars\n\nTest: run-test --64 --optimizing 020-string\nTest: run-test --64 020-string\nTest: run-test --64 --no-prebuild --optimizing 020-string\nTest: run-test --64 --no-prebuild 020-string\nTest: run-test --64 --optimizing 082-inline-execute\nTest: run-test --64 082-inline-execute\nTest: run-test --64 --no-prebuild --optimizing 082-inline-execute\nTest: run-test --64 --no-prebuild 082-inline-execute\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTest: mma test-art-target-gtest -j2\nTest: booted MIPS64R6 emulator.\n\nNote: All tests run against MIPS64 QEMU.\n\nChange-Id: I48b9a87465f2516044a2e4f598cc5dce56b0d1c9\n" }, { "commit": "2e965aca73bacf84123b5c53bb0904b13b48e428", "tree": "edad34a00b358ca613b7e18781b91c4473e916fb", "parents": [ "2b64cccce7e3697e4ccca44fb95a6cc12c6441aa" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Nov 03 17:24:15 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Nov 04 09:11:35 2016 -0700" }, "message": "ART: Use references in assembler tests\n\nMove parameters to const references.\n\nBug: 32619234\nTest: m\nChange-Id: Ib68bdc313b91fee1e9e4e1e794eeca630837b005\n" }, { "commit": "674b9ee50c812d684a27a28cf09098195f068f3d", "tree": "9b109adff71b48aa531628bf07644bccfc580fa3", "parents": [ "c6c5f6ce1c9cc44f859bbbc447478e4934be0fee" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Sep 20 14:54:15 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Oct 20 15:03:43 2016 -0700" }, "message": "MIPS32: Implement HSelect\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R2) on CI20\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: I8a8127d8d29cb5df84ed6f4fd4478f8d889e5cb7\n" }, { "commit": "a8aaf5a18ad42f3aea9afb3c8d383fe331798c9f", "tree": "56c7500a4c362f56d1c8fec471c61baf810b6658", "parents": [ "12e6e9f3f1352ed58ddd41c7f31831011695b9e4" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 27 14:48:20 2016 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 30 13:41:14 2016 +0000" }, "message": "MIPS32: Disassemble and test movf.fmt and movt.fmt (missed earlier)\n\nTest: ART gtest assembler_mips_test\nChange-Id: Iafedfafe6ccd76127461d66dfa7984f196be6bd2\n" }, { "commit": "3add9cb5e94202e65ec3c80f0b70b670d4fa63a1", "tree": "8a6b6def3ead8480bdd401534d0f148b4bbbfa13", "parents": [ "63e0a7d057adbe17ba0d34624d83f1120cb1162f" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Apr 14 14:01:33 2016 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Tue Jun 14 10:31:31 2016 -0700" }, "message": "MIPS32: Assembler tests for MIPS32R6\n\nChange-Id: Iee3f4447a6182a769490b3235abeea9551111193\n" }, { "commit": "93205e395f777c1dd81d3f164cf9a4aec4bde45f", "tree": "1d08efd9b7bca9fe23df9ae9489c5dd575d3c6df", "parents": [ "6990775e323cd9164d6cc10955a047b9d9f15f32" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 13 11:59:46 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 13 17:50:16 2016 +0100" }, "message": "Move Assemblers to the Arena.\n\nAnd clean up some APIs to return std::unique_ptr\u003c\u003e instead\nof raw pointers that don\u0027t communicate ownership.\n\nChange-Id: I3017302307a0253d661240750298802fb0d9585e\n" }, { "commit": "cd7b0ee296b0462961c63e51d99c9c323e2690df", "tree": "57a9071635389e58a8912d98b99d7e114c1efcc6", "parents": [ "0bbc1727c446ee5f4cc3c28e68127164ef379594" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Dec 03 16:46:38 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 15 14:29:48 2015 -0800" }, "message": "MIPS32: Fuse long and FP compare \u0026 condition in Optimizing.\n\nThis also does a minor clean-up in the assembler and\nits test.\n\nBug: 25559148\nChange-Id: I9bad3c500b592a09013b56745f70752eb284a842\n" }, { "commit": "a0e87b0a97fadd54540ec7e8331b61bebd82d378", "tree": "c1027e65fd859cf59f295ff3a5630404e3724db3", "parents": [ "d83b9042d67f2a7d5ca5a1f63819c97940033336" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Sep 24 22:57:20 2015 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Nov 21 22:18:50 2015 -0800" }, "message": "MIPS64: Support short and long branches\n\nChange-Id: I618c960bd211048166d9fde78d4106bd3ca42b3a\n" }, { "commit": "c4daa0a06cf0b7c1e7b0440fb7e9a06b018b52ff", "tree": "99bcea01770e8fed2ec41cd0f7f86a92a81db303", "parents": [ "4b0ef9c9246435da48203e9f273717d81a1ffe2a", "5141763acd9ca2ddb2ee6bcc742d6d2a2aebd7df" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Oct 16 22:17:56 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 16 22:17:56 2015 +0000" }, "message": "Merge \"MIPS64: Additional assember tests:\"" }, { "commit": "5141763acd9ca2ddb2ee6bcc742d6d2a2aebd7df", "tree": "06d19a307944ab61506628514d7bb6f8c95ce14e", "parents": [ "bcb71a2ce5bcb516f76fc9fe838b61b0c48e1210" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Oct 02 13:24:25 2015 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Tue Oct 06 10:39:18 2015 -0700" }, "message": "MIPS64: Additional assember tests:\n\n- MOV.fmt - NEG.fmt - CVT.D.fmt - CVT.S.fmt\n- JALR - SLL - SRL - SRA\n- DSLL - DSRA - DSRL - DSLL32\n- DSRL32 - DSRA32\n\nChange-Id: Ib15ac72128805a9bca707211359191e32d95d5d7\n" }, { "commit": "8c434dcc78d497e18590461700894d1c3e96013d", "tree": "6fc88cc839c0415aa90a1bbff25e93a09705d19b", "parents": [ "35ef974da353b13938fb0f3272c03070ad728431" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Aug 26 14:39:44 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Oct 06 16:34:25 2015 +0200" }, "message": "MIPS: Assemblers changes needed for optimizing compiler\n\nAlso add assembler tests for MIPS32.\n\nChange-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775\n" }, { "commit": "dbce0d738e9d7956d2bd73e932a0fdd28f2229b4", "tree": "336a92e522c4f20386f65f2a34534f982cf28089", "parents": [ "002117f95896ffa5db74bee808ae61e876b6e8b0" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Sep 17 13:34:00 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Oct 05 18:12:30 2015 -0700" }, "message": "MIPS64r6 Assembler Tests\n\nAssembler tests for:\n\n- SQRT.fmt - ABS.fmt - ROUND.L.fmt - ROUND.W.fmt\n- CEIL.L.fmt - CEIL.W.fmt - FLOOR.L.fmt - FLOOR.W.fmt\n- SEL.fmt - RINT.fmt - CLASS.fmt - MIN.fmt\n- MAX.fmt - cvt.d.l - BITSWAP - DBITSWAP\n- DSBH - DSHD - WSBH - ROTR\n- SELEQZ - SELNEZ - CLZ - CLO\n- DCLZ - DCLO - SC - SCD\n- LL - LLD\n\nThese are the assembler instructions which were added to support\nintrinsic functions on MIPS64. Tests for additional assembler\ninstructions will follow.\n\nSupport added to the testing infrastructure for:\n\n- Assembler instructions which use three registers; previously\n instructions were limited to one, or two, registers.\n- Immediate values which have their sizes specified by the number of\n bits required to store them rather than the number of bytes, in both\n signed and unsigned versions.\n\nChange-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b\n" }, { "commit": "cf93a5cd9c978f59113d42f9f642fab5e2cc8877", "tree": "55162627fcbf2cb7913a735c7ed89e8e4b5e84d7", "parents": [ "db40ea768bd914125c3754dacb9b6f534a2e2399" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:33:24 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 17 09:43:51 2015 +0100" }, "message": "Revert \"Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\"\n\nThis reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.\n\nAdjust block label positions. Bad catch block labels were the\nreason for the revert.\n\nChange-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310\n" }, { "commit": "fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98", "tree": "76ab28cf259def4dccec529df217fd760f27d2aa", "parents": [ "f38caa68cce551fb153dff37d01db518e58ed00f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:32:01 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:32:01 2015 +0000" }, "message": "Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\n\nThis reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.\n\nChange-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40\nReason: broke the tests.\n" }, { "commit": "f38caa68cce551fb153dff37d01db518e58ed00f", "tree": "723612f20666f429b7c67321f0353d57425b1c63", "parents": [ "bd8c725e465cc7f44062745a6f2b73248f5159ed" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 29 15:50:18 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 15 15:13:28 2015 +0100" }, "message": "ART: Implement literal pool for arm, fix branch fixup.\n\nChange-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7\n" }, { "commit": "03b9ee44362965efec4a4f3d23e978e390fa842f", "tree": "66dd5afc11663eda01c09612f18912148f1c089b", "parents": [ "1e3ab9ad421d471ca8eadac03084ce19fd06d4eb" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 24 21:41:45 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 24 22:53:40 2015 -0700" }, "message": "ART: Refactor utils/assembler test\n\nSplit out the part that compares a buffer with the product of a\nhost assembler. That will allow to reuse this for the Quick\nassemblers.\n\nChange-Id: Ie15777cb0a22f7532d8a8ea35403db0f229cd26f\n" }, { "commit": "d23840d3ed900c6072d71e6599b3568b68de6b7c", "tree": "c21634a4f0150913ab7b18017a1848ad7ca0224c", "parents": [ "fa09d442dc74ade81806fce5f1c256f4ddc13004" ], "author": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Tue Apr 07 16:03:04 2015 -0700" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Wed Apr 08 18:10:26 2015 -0700" }, "message": "x86_64: Fix the rex prefix for movzxb, movsxb, movb\n\nThis patch sets the rex prefix for the source byte register of\nmovzxb, movsxb, and movb that has the destination memory operand,\nwhen the register is SPL, BPL, SIL, DIL.\n\nThis patch adds tests for movzxb and movsxb via Repeatrb(),\nand adds the tertiary and quaternary register views for word and\nbyte registers on x86_64.\nTODO: Support tests with memory operands.\n\nChange-Id: I0c5c727f3dd4a75af039b87f7e57d0741e689038\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c", "tree": "01b21964ce0516bda835faa15b260ac290714fe0", "parents": [ "dcff612c3a6e1427749771c4559f198fa480f709" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 22:16:59 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 08:45:38 2015 -0400" }, "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures. Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "65bec691dfa22d66d5a694c40ec9874581eee333", "tree": "f46c766f56f897cb3c2a9a3909275725be4af6c2", "parents": [ "4945bfef00ac446d9c5458e55500229d463ab4c3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 14 12:03:36 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 14 12:03:36 2015 -0800" }, "message": "ART: Clean assembler_test disassemblies\n\nAdd a flag. Enable commented-out code.\n\nChange-Id: Ife17b72f2b93c128992d757e58b0e51431a3edf8\n" }, { "commit": "91e9f256b045a30fd55e96a95c77caf2eeadb2f0", "tree": "d01d662d108e9b4209ad50ae2de0d8848799c395", "parents": [ "d7a6f48736d9ed27d8bab42237ee700a2737db8e", "9aec02fc5df5518c16f1e5a9b6cb198a192db973" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 24 16:19:42 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 24 16:19:43 2014 +0000" }, "message": "Merge \"[optimizing compiler] Add shifts\"" }, { "commit": "9aec02fc5df5518c16f1e5a9b6cb198a192db973", "tree": "fe924b37f395af1bb50f55ee6c87c66b727f00af", "parents": [ "20032e512c003a8f42735c4e1eca19c1472bb95e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 18 23:06:35 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 24 16:06:55 2014 +0000" }, "message": "[optimizing compiler] Add shifts\n\nAdded SHL, SHR, USHR for arm, x86, x86_64.\n\nChange-Id: I971f594e270179457e6958acf1401ff7630df07e\n" }, { "commit": "849cc5e54cbd05f4efbd6082e03547ed9284639f", "tree": "a7f156569bc680583cc0c4d722284cfd15008bc6", "parents": [ "e5f88fe4f832d8e50452aa137a7b0c03beb57185" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Nov 18 13:46:46 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Nov 20 14:32:46 2014 -0800" }, "message": "ART: Assembler_arm_test\n\nAdd some generic test infrastructure, and update the arm32 test.\nSupports many of the GPR instructions.\n\nChange-Id: I8a270ec377f3266d6ab486e636abb50c56b87823\n" }, { "commit": "851df20225593b10e698a760ac3cd5243620700b", "tree": "e4414bc2fbad4e73785e3ef336ab2278d85aa496", "parents": [ "3225b83903329ba7745f6785127e09ff040492cf" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Nov 12 14:05:46 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Nov 13 16:31:59 2014 -0800" }, "message": "ART: Multiview assembler_test, fix x86-64 assembler\n\nExpose \"secondary\" names for registers so it is possible to test\n32b views for 64b architectures.\n\nAdd floating-point register testing.\n\nRefactor assembler_test for better code reuse (and simpler adding\nof combination drivers).\n\nFix movss, movsd (MR instead of RM encoding), xchgl, xchgq,\nboth versions of EmitGenericShift.\n\nTighten imull(Reg,Imm), imulq(Reg,Imm), xchgl and xchgq encoding.\n\nClarify cv*** variants with a comment.\n\nAdd tests for movl, addl, imull, imuli, mull, subl, cmpqi, cmpl,\nxorq (regs), xorl, movss, movsd, addss, addsd, subss, subsd, mulss,\nmulsd, divss, divsd, cvtsi2ss, cvtsi2sd, cvtss2si, cvtss2sd, cvtsd2si,\ncvttss2si, cvttsd2si, cvtsd2ss, cvtdq2pd, comiss, comisd, sqrtss,\nsqrtsd, xorps, xorpd, fincstp, fsin, fcos, fptan, xchgl (disabled,\nsee code comment), xchgq, testl, andl, andq, orl, orq, shll, shrl,\nsarl, negq, negl, notq, notl, enter and leave, call, ret, and jmp,\nand make some older ones more exhaustive.\n\nFollow-up TODOs:\n1) Support memory (Address).\n2) Support tertiary and quaternary register views.\n\nBug: 18117217\nChange-Id: I1d583a3bec552e3cc7c315925e1e006f393ab687\n" }, { "commit": "1a28fc43ea7daa624ada9af40e30de64d4e946a8", "tree": "aeb6c0aea89df5dd824e5366ad727e0557e6ebee", "parents": [ "51d3fc40637fc73d4156ad617cd451b844cbb75e" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 13 18:03:06 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 13 18:03:06 2014 +0000" }, "message": "Exercise the generation of SBFX on ARM32 \u0026 Thumb-2.\n\nExercise the generation of the ARM SBFX intruction in\ncompiler/utils/arm/assembler_arm32_test.cc (ARM\ninstruction set encoding) and in\ncompiler/utils/arm/assembler_thumb2_test.cc (Thumb\ninstruction set encoding).\n\nChange-Id: Ic72683aac6dd6628e227523e352c395e1a63b52e\n" }, { "commit": "cf7f19135f0e273f7b0136315633c2abfc715343", "tree": "ffa4d9efd9c45f4b6789acc1f534bb9327052b7e", "parents": [ "aea6888b056be21adf762e066c7f33b8939b8a06" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:06:39 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:21:57 2014 -0700" }, "message": "C++11 related clean-up of DISALLOW_..\n\nMove DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations\nwith no definitions this prompts better warning messages so deal with these\nby correcting the code.\nAdd a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object.\nMake X86 assembly operand types ValueObjects to fix compilation errors.\nTidy the use of iostream and ostream.\nAvoid making cutils a dependency via mutex-inl.h for tests that link against\nlibart. Push tracing dependencies into appropriate files and mutex.cc.\nx86 32-bit host symbols size is increased for libarttest, avoid copying this\nin run-test 115 by using symlinks and remove this test\u0027s higher than normal\nulimit.\nFix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it\nreturns NULL when the heap is under construction by Runtime.\n\nChange-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b\n" }, { "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f", "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a", "parents": [ "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 15 18:31:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 16:03:51 2014 +0100" }, "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n" }, { "commit": "54e15de4a3ea869488d50694fa01138901e70c4e", "tree": "9bb3bc73aaac2fb544e1fdbe5b6eb53cc7f5aaf7", "parents": [ "147594f8815ed0982d7e5676dc8b6fed5a0ba9e6" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Aug 06 15:31:06 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 08 10:48:44 2014 -0700" }, "message": "ART: Make assembler_test less chatty\n\nDo not save temporaries in case we use a different encoding than\nthe host assembler.\n\nBug: 16505797\nChange-Id: Iaa9edfe8bc84d7f809f5b403de902b92b0998431\n" }, { "commit": "7747c8de402f64e3009ca3bcccebddbb70f617ee", "tree": "491fb0e346d6e0821d209b9617f0abfac78aedb1", "parents": [ "57cd9d3bda952ee2c2cf977fb1e26a0a954e1bab" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Aug 06 14:53:03 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Aug 06 16:06:28 2014 -0700" }, "message": "ART: Remove test files after test\n\nThe unix_file tests should remove files and directories when they\nare done testing.\n\nBug: 16505797\nChange-Id: Iff6856f64ee42ee9818b4ac23a6de3fe7eec6eae\n" }, { "commit": "700a402244a1a423da4f3ba8032459f4b65fa18f", "tree": "4c22fcda04d271bd55a37aff30650214af17a90c", "parents": [ "047c11adcbcbc0bcf210defdfcbada763961ffee" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 16:49:03 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 22:27:39 2014 -0700" }, "message": "Now we have a proper C++ library, use std::unique_ptr.\n\nAlso remove the Android.libcxx.mk and other bits of stlport compatibility\nmechanics.\n\nChange-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61\n" }, { "commit": "b40c6a768aa8df4774d2a8c3ac7045237cc748cd", "tree": "cbfd1265e0e1b43345d97727d21d0e7e5a9859d8", "parents": [ "1dbbbf6090274ebae6809fdb340c166bb34e09c2" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri May 02 14:25:12 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri May 02 14:25:12 2014 -0700" }, "message": "ART: Fix assembler_test to use ScratchFile\n\nThis removes a warning about tmpnam usage.\n\nAlso add an assertion to ScratchFile about ANDROID_DATA being set,\nwhich it relies on for the temp directory.\n\nChange-Id: I1202f92e48e61492f0ed3ac36ff44fde34dbb0e1\n" }, { "commit": "5a4fa82ab42af6e728a60e3261963aa243c3e2cd", "tree": "69da9eb204c294be63f30d49cf0233e1dc9b6e93", "parents": [ "0a3b13fc401bcf21225e30654012fe98806b0873" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 31 16:50:12 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Apr 30 19:25:51 2014 -0700" }, "message": "x86_64 Assembler Test Infrastructure, fix x86_64 assembler\n\nSome infrastructure to do real assembler testing. Need to extend to\nother assemblers, and a lot more tests.\n\nFix some of the cases of the x86_64 assembler.\n\nChange-Id: I15b5f3a094af469130db68a95a66602cf30d8fc4\n" } ] }