)]}' { "log": [ { "commit": "b15e8797d2ca6fb480a940887c66dd2aae7c9065", "tree": "23bd6e44c31b45fde7d92bbe7620329a61c1fcf5", "parents": [ "79bf0b8e9c704e63029bb3badf9c4872484a827b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 28 12:20:59 2020 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Nov 10 09:46:01 2020 +0000" }, "message": "Verify ART run-tests\u0027 standard output and standard error separately.\n\nIntroduce expected standard error files for ART run-tests. Collect\ntests\u0027 standard output and standard error separately and check them\nagainst the corresponding expectation file.\n\nTest: Run ART run-tests on host and device using `testrunner.py`.\nTest: atest --test-mapping art:all\nTest: atest --test-mapping cts/hostsidetests/jvmti:all\nBug: 171865375\nBug: 147812905\nChange-Id: Ie95bec4a4684ff6791d464124ce8976339432d1f\n" }, { "commit": "a073f46104fbce0482fb759d5ccfb32ee39cc973", "tree": "985538ce69fa4d9253725cddaca936ddc3eaea86", "parents": [ "5a19854c682a994729f704806d6c0de1de349631" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Oct 28 12:48:24 2020 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 05 18:15:49 2020 +0000" }, "message": "Rename ART run-tests `expected.txt` files as `expected-stdout.txt`.\n\nThis is in preparation for the addition of `expected-stderr.txt` files\nin all ART run-test directories, which will record the expected\nstandard error for each of these tests, and which will be verified\nalong with `expected-stdout.txt`.\n\nTest: Run ART run-tests on host and device using `testrunner.py`.\nTest: atest --test-mapping art:all\nBug: 171865375\nBug: 147812905\nChange-Id: I37e3c4b8409475790e2fc63514cdf57156d47ff4\n" }, { "commit": "45217376b527cd17d758152c54960e6786288e31", "tree": "cc2ae731f7ebfe61af74fa8150025064a0245a8a", "parents": [ "8b236fac816beb18e4919e2c4260da843257a4e3" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Apr 03 10:46:13 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Oct 29 15:40:27 2019 +0000" }, "message": "Fix intersecting live ranges created by instruction scheduler\n\nWhen scheduling code like the following:\nLOOP:\n v2\u003dphi(v0, v1)\n use(v2)\n v1\u003d...\n goto LOOP\n\nthe instruction scheduler can move \u0027v1\u003d...\u0027 before \u0027use(v2)\u0027. This\ncauses live ranges of v1 and v2 to intersect and results to a MOV\ninstruction to be created.\n\nThe CL fixes this.\n\nImprovements, Pixel3:\n Little CPU, arm64\n micro/GCCLoops\n Example12 14.1%\n Example10b 11.0%\n Example23 8.1%\n Example24 6.6%\n Example10a 5.0%\n FFT workload 4.7%\n Compress workload 1.2%\n\n Little CPU, arm32\n micro/GCCLoops\n Example23 7.5%\n Example24 4.3%\n MonteCarlo workload 1.35%\n\n Big CPU, arm32 and arm64\n No significant improvements\n\nNo significant regressions (\u003e 5%) are found.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I1e4282af18f2d51fde5325a0c00a57e8bbc4fbed\n" }, { "commit": "d1aa7d0eec33e5f297d1eadedda714d4d0a3ef91", "tree": "e8a3876705be966611a06659e9f4b848205f3957", "parents": [ "11529ab4cdf06e579182fa4252170aa4541f4ce9" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Jun 22 11:35:46 2018 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Aug 31 12:34:32 2018 +0100" }, "message": "ART: Remove unneeded SideEffects for fatal instructions.\n\nRemove \"CanTriggerGC\" side effect for NullCheck, BoundsCheck and\nDivZeroCheck - instructions which have fatal slow paths. Even though\nGC might happen after going through those instructions\u0027 slow path\nexecution doesn\u0027t return to the next instruction after the\nexceptional one so side effects can be relaxed.\n\nPerformance improvement (angler, arm64, little core):\n - Geomean: 2.8%\n - Particular benchmarks\n - algorithm/Sort.SystemSort: 13.0%\n - stanford/IntMM: 12.7%\n - stanford/Puzzle: 9.5%\n - benchmarksgame/revcomp: 8.9%\n - reversigame/Reversi: 3.5%\n\nTest: 510-checker-try-catch.\nTest: 706-checker-scheduler.\nTest: 527-checker-array-access-split.\nTest: test-art-host, test-art-target.\n\nChange-Id: I55ac011822e5dbac82c828a700213dbea87329c8\n" }, { "commit": "2ab1bdd1ed06ff2cbcfbed946fb58778be23ad4f", "tree": "ce63864f7f62b433ca863866406bee2e7af73065", "parents": [ "fca0b491a34144acf6769ab9c5fb528ac81bd325" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 12 09:59:56 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 23 18:39:09 2018 +0100" }, "message": "Elide ClinitCheck for superclasses with trivial init.\n\nWe cannot generally elide ClinitCheck for superclasses\nbecause of escaping instances of erroneous classes and\nbecause a subclass can be successfully initialized while\nthe superclass is initializing and the subclass remains\ninitialized even when the superclass initializer throws.\n\nHowever, for those superclasses that have trivial init,\ni.e. that class and its superclasses (and superinterfaces\nwith default methods) initialize only their own static\nfields using constant values, there is no chance to end\nup in one of these weird situations and we can safely\neliminate the ClinitCheck.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16856928\n arm64/boot*.oat: 19846592\n oat/arm64/services.odex: 24662880\n - after:\n arm/boot*.oat: 16848696 (-8.0KiB, -0.05%)\n arm64/boot*.oat: 19842320 (-4.2KiB, -0.02%)\n oat/arm64/services.odex: 24629952 (-32.2KiB, -0.13%)\nwith minor changes to other app prebuilts.\n\nTest: Improved 478-checker-clinit-check-pruning.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 62478025\nChange-Id: I865f567443f1b7f172e5e6559d8eb3232adb7833\n" }, { "commit": "51b8aafd3beb8855a258383a9eb876a783375629", "tree": "002f77eb0308dbb11b6e5e5a88ce4bc19c6ff836", "parents": [ "e824cfdcfd41d400237a806ff93caca7f2e51878" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 09 15:17:05 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 12 09:23:17 2018 +0100" }, "message": "Fix HClinitCheck elimination in instruction builder.\n\nTo handle escaping instances of erroneous classes correctly,\nwe can omit the HClinitCheck only when using a class in the\nstatic method of the very same class. Even for superclasses\nwe need to do the check. The new test exposes the cases\nwhere we were previously diverging from the RI.\n\nAlso clean up the CompilerDriver by inlining one function\ndirectly to the HInstructionBuild::IsInitialized(.) and\nremoving some related functions that are no longer used.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16891788\n arm64/boot*.oat: 19815520\n oat/arm64/services.odex: 20071624\n - after:\n arm/boot*.oat: 16949532 (+56.4KiB, +0.34%)\n arm64/boot*.oat: 19889752 (+72.5KiB, +0.37%)\n oat/arm64/services.odex: 20224328 (+149.1KiB, +0.76%)\nwith minor changes to other app prebuilts.\n\nNote: Some of that could be reclaimed by reinstating the old\noptimization for classes where no bytecode can be executed\nduring initialization (no \u003cclinit\u003e to execute in that class\nor superclasses).\n\nTest: 174-escaping-instance-of-bad-class\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --jvm -t 174\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 62478025\nChange-Id: I41f026ea7fecc615c06e87f3b6cb847de0ede8a6\n" }, { "commit": "a6f5c8cd15316ff1ceeb4ce7c3de0644e3b81cb8", "tree": "0621bf0b8c544f7c0d4dc300a7cbaea699561e88", "parents": [ "1e739fa94947147953c53e92964e0e9e1eac0526" ], "author": { "name": "Tamas Kenez", "email": "tamaskenez@google.com", "time": "Wed Jun 20 13:57:04 2018 +0200" }, "committer": { "name": "Tamas Kenez", "email": "tamaskenez@google.com", "time": "Wed Jun 20 13:57:04 2018 +0200" }, "message": "ART-tests: remove DX dependency from 706-checker-scheduler.\n\nWith the D8 generated code 2 PHI instruction are swapped in the ARM64\ncode. This CL updates the corresponding CHECK conditions and enables\nD8.\n\nTest: art/test.py -b -r --target -t 706-checker-scheduler\nBug: 65168732\nChange-Id: If17bfdd0732b850279a10736c15ef296e15f0c90\n" }, { "commit": "88f1054e8272dfc1a47bf172b14c423b66417554", "tree": "f03988967c101630bca8af03208320477ca2fa97", "parents": [ "d9c8f55d18af0cdf379715eef83d6c9f737ef947" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu Apr 05 09:54:52 2018 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu Apr 05 10:04:22 2018 +0100" }, "message": "ART: Temporarily move 3 checker tests away from D8\n\nPostpones switching to D8 for tests failing on the ART buildbots.\n\nAll of the tests modified were failing on 64-bit ARM. Only\n551-checker-shifter-operand was failing on 32-bit ARM.\n\nBug: 65168732\nTest: art/test.py --target -j4 -r --64 -t 551-checker-shifter-operand\nTest: art/test.py --target -j4 -r --64 -t 626-checker-arm64-scratch-register\nTest: art/test.py --target -j4 -r --64 -t 706-checker-scheduler\n\nChange-Id: Ie02d8dc46a36ebe5ddb9a6e24e96bc2bdc4f97c7\n" }, { "commit": "89ff8b23f7c4189ba82407d95c3100c2f397cf19", "tree": "95a49416c9231eea98c927e8777b7721b24974a3", "parents": [ "03376f4c4de8e419402bf40fdff4135728ffb21e" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Nov 20 11:51:05 2017 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Dec 13 15:33:29 2017 +0000" }, "message": "ARM64: Workaround for the callee saved FP registers and SIMD.\n\nTreat as scheduling barriers those vector instructions whose live\nranges exceed the vectorized loop boundaries. This is a workaround\nfor the lack of notion of SIMD register in the compiler; around a\ncall we have to save/restore all live SIMD\u0026FP registers (only\nlower 64 bits of SIMD\u0026FP registers are callee saved) so don\u0027t\nreorder such vector instructions.\n\nTest: 706-checker-scheduler, test-art-host, test-art-target\nBug: 69667779\n\nChange-Id: I31e57518339d41545a0c519f7299afe381a8286c\n" }, { "commit": "e0eb48353ddf0c1b79bfec2ba15c899a413c2c70", "tree": "71dfe896afa05c39d64373518d1e1e36cb8d8d43", "parents": [ "3e6c13997373efac343a65740da0c4f6e77338b9" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon Oct 30 13:43:14 2017 +0000" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Thu Nov 02 16:17:17 2017 +0000" }, "message": "Fix LSA hunt for original reference bug.\n\nFix a bug in LSA where it doesn\u0027t take IntermediateAddress\ninto account during hunting for original reference.\n\nIn following example, original reference i0 can be transformed\nby NullCheck, BoundType, IntermediateAddress, etc.\n i0 NewArray\n i1 HInstruction(i0)\n i2 ArrayGet(i1, index)\n\nTest: test-art-host\nTest: test-art-target\nTest: load_store_analysis_test\nTest: 706-checker-scheduler\n\nChange-Id: I162dd8a86fcd31daee3517357c6af638c950b31b\n" }, { "commit": "1545ccc4852255870b5c4676203fc7c2f2fa393f", "tree": "5e983b1ece6e6d7af3cd2d476bdbcac6ebb49631", "parents": [ "3b21019edb5586a73516833482fc203e75309dbe" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Aug 08 15:24:26 2017 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Thu Aug 10 14:10:06 2017 -0700" }, "message": "scheduler should not schedule volatile field accesses.\n\nUnresolved field accesses are not scheduled either since it\u0027s not know\nwhether they are volatile or not, and they are already expensive anyway.\n\nTest: 706-checker-scheduler\nChange-Id: Ie736542590a2459ee9b597e090fbedd4b527782a\n" }, { "commit": "2a3471fc83383bfe3e060799482e372420ba6150", "tree": "7b7764521a0b67392e023f1efacc0dbae64fe675", "parents": [ "89ae0f42e38a2f985ac404830f2a05fecf9547e2" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon May 08 18:36:40 2017 +0100" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Fri Jun 30 16:32:54 2017 +0100" }, "message": "Disambiguate memory accesses in instruction scheduling\n\nBased on aliasing information from heap location collector,\ninstruction scheduling can further eliminate side-effect\ndependencies between memory accesses to different locations,\nand perform better scheduling on memory loads and stores.\n\nPerformance improvements of this CL, measured on Cortex-A53:\n| benchmarks | ARM64 backend | ARM backend |\n|----------------+---------------|-------------|\n| algorithm | 0.1 % | 0.1 % |\n| benchmarksgame | 0.5 % | 1.3 % |\n| caffeinemark | 0.0 % | 0.0 % |\n| math | 5.1 % | 5.0 % |\n| stanford | 1.1 % | 0.6 % |\n| testsimd | 0.4 % | 0.1 % |\n\nCompilation time impact is negligible, because this\nheap location load store analysis is only performed\non loop basic blocks that get instruction scheduled.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: 706-checker-scheduler\n\nChange-Id: I43d7003c09bfab9d3a1814715df666aea9a7360b\n" }, { "commit": "22aa54bf8469689c7c6c33f15ff4df2ffba8fa15", "tree": "14204d55784dce3ffdd2641382a763afee85ced0", "parents": [ "8116003cc9dd1e74fac1682eec547b8bb0afb061" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Oct 18 09:32:29 2016 +0100" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Wed Jan 25 14:25:20 2017 +0000" }, "message": "AArch64: Add HInstruction scheduling support.\n\nThis commit adds a new `HInstructionScheduling` pass that performs\nbasic scheduling on the `HGraph`.\n\nCurrently, scheduling is performed at the block level, so no\n`HInstruction` ever leaves its block in this pass.\n\nThe scheduling process iterates through blocks in the graph. For\nblocks that we can and want to schedule:\n1) Build a dependency graph for instructions. It includes data\n dependencies (inputs/uses), but also environment dependencies and\n side-effect dependencies.\n2) Schedule the dependency graph. This is a topological sort of the\n dependency graph, using heuristics to decide what node to schedule\n first when there are multiple candidates. Currently the heuristics\n only consider instruction latencies and schedule first the\n instructions that are on the critical path.\n\nTest: m test-art-host\nTest: m test-art-target\n\nChange-Id: Iec103177d4f059666d7c9626e5770531fbc5ccdc\n" } ] }