)]}'
{
  "log": [
    {
      "commit": "3d661949dba4a2f3311e6f74a3c42b5addf1f534",
      "tree": "d8fd2c903fe425bb65a92a7ee9f72a1e57cf5045",
      "parents": [
        "fb84494fc1888b92e938ece850990668073a276b"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Mar 14 17:37:27 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Mar 14 17:53:18 2012 -0700"
      },
      "message": "Real fix for 064\n\nThe recent ssa cleanup CL surfaced a somewhat subtle bug in\nlive register tracking.  The code generation register utilities\nattempt to remember and reuse live Dalvik register values for future\nuse.  This remembering takes place in the storeValueXX() code.\nFor this to work, though, storeValue may only be called once during\nthe compilation of any single Dalvik instruction.\n\nHowever, the code generation routine for CONST_CLASS included a\nsomewhat complicated slow path with iternal branches and two\ngenerated \"storeValue\" locations.  This resulted in downstream\ncode expecting to find a live value in the wrong place.\n\nThis fix is to note this special case and do a \"clobber\" on the ssa name.\n\nThis CL also includes some sanity checking code that can detect\nmultiple calls to storeValue during one intruction compilation to\ntry to catch this situation in the future.\n\nChange-Id: I66a279140accd80cda83f66efe570c9702fb351b\n"
    },
    {
      "commit": "e196567b50a084b163937ea9605b51ee1e48adeb",
      "tree": "709964fc09a36132490d9a3a4805983ec80c57e3",
      "parents": [
        "13b835a45f3dccff1c6d024ad82a2044831c7c41"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 11 18:39:19 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Mar 13 20:59:18 2012 -0700"
      },
      "message": "SSA rework and support compiler temps in the frame\n\nAdd ability for the compiler to allocate new frame temporaries\nthat play nicely with the register allocation mechanism.  To do this\nwe assign negative virtual register numbers and give them SSA names.\nAs part of this change, I did a general cleanup of the ssa naming.\nAn ssa name (or SReg) is in index into an array of (virtual reg, subscript)\npairs.  Previously, 16 bits were allocated for the reg and the subscript.\nThis CL expands the virtual reg and subscript to 32 bits each.\n\nMethod* is now treated as a RegLocation, and will be subject to\ntemp register tracking and reuse.  This CL does not yet include\nsupport for promotion of Method* - that will show up in the next one.\n\nAlso included is the beginning of a basic block optimization pass (not\nyet in a runable state, so conditionally compiled out).\n\n(cherry picked from commit f689ffec8827f1dd6b31084f8a6bb240338c7acf)\n\nChange-Id: Ibbdeb97fe05d0e33c1f4a9a6ccbdef1cac7646fc\n"
    },
    {
      "commit": "efccc565091b3409ed1372615b4ea4e2f6c39323",
      "tree": "c0987fb6051a0c4abe2129dc3564c51274fab7e1",
      "parents": [
        "904667a58fa38437d1be6907beb3fb76d1982e0b"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 11 11:19:28 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 11 11:19:28 2012 -0700"
      },
      "message": "Frame layout change\n\nThis CL slightly changes the frame layout to remove an old unnecessary\nslot, allow for the inclusion of compiler-generated temps and\nunifies all variable offset calculation into a single function shared\nby the compilers and the runtime system.\n\n   o Update the GetVRegOffset function in stack.cc to understand the\n     new layout.\n\n   o Remove compiler-private offset calculation code and route\n     everything through the shared GetVRegOffset in thread.cc.\n\n   o Remove \"filler word\" that existed immediately after the last\n     Dalvik local.  This was there to address an initial concern that\n     I had about a single argument register being reused later as a\n     long.  Now convinced that it won\u0027t happen.\n\n   o Extend the old \"padding\" region to include compiler-created temps\n     that can appear to the rest of the rest of the system as\n     Dalvik registers.  The new temps will have Dalvik register numbers\n     of -2 and lower.\n\n   o Treat Method* for the current method as a special Dalvik register\n     denoted by reg number -1.\n\nChange-Id: I5b5f3aef9c6a01d3a647ced6ec06981ed228c785\n"
    },
    {
      "commit": "b3bd5f07884f5a1f2b84224363b1372d7c28d447",
      "tree": "6e2997ab64b4a4f32d7ef539a4649adc736ea553",
      "parents": [
        "ddbd01ac1660d57416879d5a576482f1048dde64"
      ],
      "author": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Thu Mar 08 21:05:27 2012 -0800"
      },
      "committer": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Fri Mar 09 15:37:46 2012 -0800"
      },
      "message": "Refactor the compilers out of libart.\n\nThis builds three separate compilers and dynamically links with the right one\nat runtime.\n\nChange-Id: I59d22b9884f41de733c09f97e29ee290236d5f4b\n"
    },
    {
      "commit": "86a4bce32e2aaf3d377c0acf865f0630a7c30495",
      "tree": "98517211fdb1309f461e3fe3c41a34739ad121c1",
      "parents": [
        "6150d9889b56e95f1267d9200c5702b16e0d32d5"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Mar 06 18:15:00 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Mar 07 12:10:21 2012 -0800"
      },
      "message": "Fix branch bug (showed up in codegen for debug)\n\nThere are a few \"safe\" optimizations in the compiler - removing\nregister copies where source and target are the same, deleting\nbranches to the next instruction, etc.  One of the redundant\nbranch optimizations, however, was incorrect and resulted in\na good branch being deleted.  This one showed up in the debug\nbuild, and resulted in a failure to do a suspend check (because\nthe branch to the suspend check was deleted).\n\nI had hoped that this but might also be the case of some\nother unexpected failures, but unfortunately I was only able\nto trigger it when doing a \"codegen for debug\" build.\n\nThe source of the bug was a confusion around 16 v/ 32-bit\nunconditional branch encodings.  For a 32-bit unconditional\nbranch, going to the next instruction means an displacement\nof zero.  However, for 16-bit branches, the next instruction\nis represented by a displacement of -1.\n\nTo help track down this sort of thing in the future, this CL\nalso adds a new optimization disable flag: kSafeOptimizations.\nThis will allow us to really turn off all optimizations for A/B\ntesting.\n\nAlso in this CL we are re-enabling the ability to promote argument\nregisters and improving somewhat the code sequence for suspend\ncheck when debug is enabled.\n\nChange-Id: Ib6b202746eac751cab3b4609805a389c18cb67b2\n"
    },
    {
      "commit": "31a4a6f5717f645da6b97ccc1e420ae1e1c71ce0",
      "tree": "de07c7175bcda6c2e3f11329d72d142319354f3f",
      "parents": [
        "32c9a2decebe7b736e1f05b53b5822affea5e81d"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Feb 28 15:36:15 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Feb 29 18:52:47 2012 -0800"
      },
      "message": "More target-independence\n\nContinuing to move target-specific code from the Arm\ncode generator into the independent realm.  This will be\ndone in multiple small steps.\n\nIn this CL, the focus is on unifying the LIR data structure and\nvarious enums that don\u0027t really need to be target specific. Also\ncreates two new shared source files: GenCommon.cc (to hold\ntop-level code generation functions) and GenInvoke.cc (which\nis likely to be shared only by the Arm and Mips targets).\n\nAlso added is a makefile hack to build for Mips (which we\u0027ll\neventually remove when the compiler support multiple targets\nvia the command line) and various minor cleanups.\n\nOverall, this CL moves more than 3,000 lines of code from\ntarget dependent to target independent.\n\nChange-Id: I431ca4ae728100ed7d0e9d83a966a3f789f731b1\n"
    },
    {
      "commit": "e3acd07f28d5625062b599c2817cb5f7a53f54a9",
      "tree": "d38696b0235dab5d8ef791cdb9fb311a6705e03b",
      "parents": [
        "55b796c6f1fdc36494463a3deeb1e248800695e9"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Feb 25 17:03:10 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Feb 26 20:44:46 2012 -0800"
      },
      "message": "Multi-target support\n\nThis CL represents a step towards splitting out the target dependent\nand target independent portions of the compiler, and also adds in the\nbeginning of a MIPS compiler based on the MIPS AOSP Jit submission.\n\nMore polish is clearly needed, but the split is here probably pretty\nclose.  The MIPS code will not compile at this point (and there is no\nmakefile target at present), but it\u0027s pretty close.\n\nThere should be no changes in functionality of the Arm compiler in this\nCL - just moved stuff around.\n\nChange-Id: Ia66b2847e22644a1ec63e66bf5f2fee722f963d4\n"
    },
    {
      "commit": "5abfa3ea35781464df8fae60aaf03f48a295e965",
      "tree": "3db19d0ecfc1031f86d77964de636ec45d4ba690",
      "parents": [
        "6c7d244058b74cdd61533968dd6cddd7003d2671"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Jan 31 17:01:43 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Feb 02 15:56:41 2012 -0800"
      },
      "message": "Compiler tuning\n\nSignificant reduction in memory usage by the compiler.\n    o Estimated sizes of growable lists to avoid waste\n    o Changed basic block predecessor structure from a growable bitmap\n      to a growable list.\n    o Conditionalized code which produced disassembly strings.\n    o Avoided generating some dataflow-related structures when compiling\n      in dataflow-disabled mode.\n    o Added memory usage statistics\n    o Eliminated floating point usage as a barrier to disabling expensive\n      dataflow analysis for very large init routines.\n    o Because iterating through sparse bit maps is much less of a concern now,\n      removed earlier hack that remembered runs of leading and trailing\n      zeroes.\n\nAlso, some general tuning.\n    o Minor tweaks to register utilties\n    o Speed up the assembly loop\n    o Rewrite of the bit vector iterator\n\nOur previous worst-case method originally consumed 360 megabytes, but through\nearlier changes was whittled down to 113 megabytes.  Now it consumes 12 (which\nso far appears to close to the highest compiler heap usage of anything\nI\u0027ve seen).\n\nPost-wipe cold boot time is now less than 7 minutes.\n\nInstallation time for our application test cases also shows a large\ngain - typically 25% to 40% speedup.\n\nSingle-threaded host compilation of core.jar down to \u003c3.0s, boot.oat builds\nin 17.2s.  Next up: multi-threaded compilation.\n\nChange-Id: I493d0d584c4145a6deccdd9bff344473023deb46\n"
    },
    {
      "commit": "11d1b0c31ddd710d26068da8e0e4621002205b4b",
      "tree": "8d9c9c0dd5741214466775b86069032d609fd91c",
      "parents": [
        "bbdb1437f55948e5395b4dcb306e25605539a444"
      ],
      "author": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Mon Jan 23 16:57:47 2012 -0800"
      },
      "committer": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Mon Jan 23 17:26:10 2012 -0800"
      },
      "message": "Reduce namespace pollution.\n\nThis leaves us with just the mspace stuff and three libdex functions to clean\nup. We deliberately expose the JII API, and I don\u0027t think there\u0027s anything we\ncan really do about the art_..._from_code stuff (and at least that starts with\n\"art_\").\n\nChange-Id: I77e58e8330cd2afeb496642302dfe3311e68091a\n"
    },
    {
      "commit": "a50638ba8b983616da3cf1aa941038bea56159e5",
      "tree": "db7d9f0080d264ab3735bc7495da9dd9df929f9e",
      "parents": [
        "5d76c435082332ef79a22962386fa92a0870e378"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Nov 02 15:15:06 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Nov 02 15:15:06 2011 -0700"
      },
      "message": "Register allocation fixes.\n\nThis fixes the calculator button problem, but let\u0027s leave optimization\noff until we\u0027ve passed more tests.\n\nChange-Id: I79b71687a1651e83f16037dead768c43f55d65da\n"
    },
    {
      "commit": "67bc236a207852d652f6ddeab0a90efc1bd111bb",
      "tree": "eea13fcb90ad8ce5b2b3819fb8caf0281583cd61",
      "parents": [
        "95caa791e560da97363c0c0d22bfda4a7e7377c3"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Oct 11 18:08:40 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Oct 14 10:54:03 2011 -0700"
      },
      "message": "Register promotion fix\n\nRestructured the type inference mechanism, added lots of DCHECKS,\nbumped the default memory allocation size to reflect AOT\ncompilation and tweaked the bit vector manipulation routines\nto be better at handling large sparse vectors (something the old\ntrace JIT didn\u0027t encounter enough to care).\n\nWith this CL, optimization is back on by default.  Should also see\na significant boost in compilation speed (~2x better for boot.oat).\n\nChange-Id: Ifd134ef337be173a1be756bb9198b24c5b4936b3\n"
    },
    {
      "commit": "6825326abfef92d4e1bf6afddef1a319aa18d08c",
      "tree": "1706bf3e0bbdb9f7a704140f70011c1b362fa294",
      "parents": [
        "a43cb5e8fb29989dbb986b9b91a68cda150aa3c8"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Oct 07 14:02:25 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Oct 07 14:16:01 2011 -0700"
      },
      "message": "Reg utility fix\n\nLong ago in a galaxy far away, there was a trace compiler that\nhandled short code fragments with a small, sparse and variable\nset of temp registers.  In that situation, doing linear reg\nlookups wasn\u0027t terrible.  In the new world that has a fixed and\npacked set of registers, a linear search is unnecessary, foolish\nand wasteful.  [P.S. perf showed that roughly 25% of all\ncompilation time was spent doing register manipulation!]\n\nChange-Id: I6f23d9f70367fb4139cc28a27fd9fdf8beffa270\n"
    },
    {
      "commit": "3ddc0d1108a00e14b60c60edcdeff3b81f9e35f9",
      "tree": "daae3f0f439fc95e29a611d366f82309316943f4",
      "parents": [
        "ce30293d222c864fa281da98bc896dd1c98a9a16"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Oct 05 10:36:21 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Oct 05 10:36:21 2011 -0700"
      },
      "message": "Fix Vmap table size\n\nConsistently use 16 bits to store Dalvik vreg number.\n\nChange-Id: I6d21c0ed7011e5defaa45571951ff7608d0ce80e\n"
    },
    {
      "commit": "bbaf894dded77603bd457758ba2b4636122fb8b7",
      "tree": "ac8d0450f23dd6cde9647febef8de514c5a4b8ae",
      "parents": [
        "fc22c89072e310767f8e39776195a219df851ea0"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Oct 02 13:08:29 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Oct 02 13:21:01 2011 -0700"
      },
      "message": "Optimization fixes\n\nTwo primary fixes.  First, the save/restore mechanism for FP callee saves\nwas broken if there were any holes in the save mask (the Arm ld/store\nmultiple instructions for floating point use a start + count mechanism,\nrather than the bit-mask mechanism used for core registers).\n\nThe second fix corrects a problem introduced by the recent enhancements\nto loading floating point literals.  The load-\u003ecopy optimization mechanism\nfor literal loads used the value of the loaded literal to identify\nredundant loads.  However, it used only the first 32 bits of the\nliteral - which worked fine previously because 64-bit literal loads\nwere treated as a pair of 32-bit loads.  The fix was to use the\nlabel of the literal rather than the value in the aliasInfo - which\nworks for all sizes.\n\nChange-Id: Ic4779adf73b2c7d80059a988b0ecdef39921a81f\n"
    },
    {
      "commit": "58f9274efe66535255a70327022b8f586d334843",
      "tree": "6899c83fbf029ca90b2beaef1f92ed7b8b9d72ea",
      "parents": [
        "e4390576de48a47a7f2dd99534169d83aaaa71ae"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Oct 01 11:22:17 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Oct 01 11:26:37 2011 -0700"
      },
      "message": "Various bugfixes\n\ndivide by zero check for longs, off-by-one error on fill-array-data,\nregister management hygene, mvn encoding, iget/iput \u003c\u003d 32bits are\ndone as 32-bit (code was using type size for ld/st).\n\nChange-Id: Ia09323e7d92f4ad21890af4c10f2f8c8f05f3b0e\n"
    },
    {
      "commit": "6181f79576e4269937b45e4fce8d0d004107e5b9",
      "tree": "1e5970dd4074c9852b10ecfc6bc4f18b89d40dd7",
      "parents": [
        "557e027f86d86f801e1b48055f8116f2d83d3d5c"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Sep 29 11:14:04 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Sep 29 13:38:10 2011 -0700"
      },
      "message": "Register usage cleanup\n\nI plan to enable some of the old-world basic block optimizations.\nThose care about temp register status, so we needed a bit of\ncleanup on the temp tracking.\n\nChange-Id: I317bce1b91a73ec9589c20ed5bfe00d53994991a\n"
    },
    {
      "commit": "b29e4d1423028fab47db3be6e41e4b2a067bf100",
      "tree": "c965f68c3c57750a837baf4f70fd9dc876adb082",
      "parents": [
        "395520eaa47eca25b92e86188accf3095d60af49"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Sep 26 15:05:48 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Sep 26 15:05:48 2011 -0700"
      },
      "message": "Misc codegen fixes related to register promotion\n\nThe post-promotion world no longer guarantees that wide result\npairs don\u0027t overlap with source operands.  Also had to narrow\na load-elimination optimization to apply only when using\ntemp registers for Dalvik virtual registers.\n\nChange-Id: I2afbbec865d5a14d46e539cce4d8b3d0e4e8880b\n"
    },
    {
      "commit": "ed3e930109e3f01804ca32cee4afe4f2d4b3f4d8",
      "tree": "41c3ffd3fdade2244b4cd3824c98419edecbca86",
      "parents": [
        "8060925c45cc2607ab92390d7366c6c0cfdfe4bb"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Sep 23 17:34:19 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Sep 23 18:34:31 2011 -0700"
      },
      "message": "assert to DCHECK conversion\n\nAlso replaced static function defs with a STATIC macro to make normally\nhidden functions visible to DCHECK\u0027s traceback listing).  Additionally,\nadded some portions of the new type \u0026 size inference mechanism (but not\ntaking advantage of them yet).\n\nChange-Id: Ib42a08777f28ab879d0df37617e1b77e3f09ba52\n"
    },
    {
      "commit": "042946dda087c5f3d3aed48349baa33127cf2faf",
      "tree": "bb025ac206db674667c50dea7e084e52140ff8f7",
      "parents": [
        "c41e5b5ae1befe2c602d55de1dbc04d1914f4a6c"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Sep 23 15:49:27 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Sep 23 15:49:27 2011 -0700"
      },
      "message": "Fix dalvik vm reg to callee save mappings\n\nNeglected to include fp regs promoted as a double.\n\nChange-Id: I7ca6ad5e755c5d2e20c1c903cf41491d605f258e\n"
    },
    {
      "commit": "c41e5b5ae1befe2c602d55de1dbc04d1914f4a6c",
      "tree": "fa122d75b64193d7c2dee7a1be871a5ae8511493",
      "parents": [
        "f4afb7aec4e51c2e682cf3af4d6511add74d2f38"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Sep 23 12:46:19 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Sep 23 13:53:25 2011 -0700"
      },
      "message": "Add tables to map between callee saves and vregs\n\nAlso added function to return sp-relative offset for Dalvik\nvirtual registers using Method*\n\n[Note: must be matched with corresponding libcore change to\nreflect new field in Method]\n\nChange-Id: Id739908c6232ce60763d8199bc05111e960da46e\n"
    },
    {
      "commit": "43a364291dcdfe08e530e9568748359735dd7442",
      "tree": "1141a3f0f91c527dfe28796e88f166d2bc0ed7fd",
      "parents": [
        "303b01ed0d36017371e29b1f1e209dd19896ac9e"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Sep 14 14:00:13 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Sep 14 15:40:34 2011 -0700"
      },
      "message": "Fix null check elimination\n\nThe existing null check elimination mechanism suffered from the same\nlimitation as the SSA renaming: it took shortcuts that were valid in\na trace compilation world, but not in a method compilation world.\n\nThis CL replaces the old mechanism, and additionally takes advantage\nof some the fact that \"this\" is always non-null, as are objects returned\nfrom OP_NEW_* (thanks Ian!).\n\nTwo test cases added.  The one for ensuring that unnecessary null checks\nare elminated requires manual inspection.  The other - that we don\u0027t\neliminate a necessary null check - is disabled until exceptions are working.\n\nChange-Id: I2a9b72741f56617bf609e4d7c20244796c988f28\n"
    },
    {
      "commit": "f0cde549bed96e16401a347a4511b59130c61e84",
      "tree": "a5c91481513ea75897d0f64ae9bb660923f42a94",
      "parents": [
        "5ea047b386c5dac78eda62305d14dedf7b5611a8"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Sep 13 14:55:02 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Sep 13 15:13:44 2011 -0700"
      },
      "message": "SSA renaming fix \u0026 invalid opcode fix\n\nThe old SSA renaming mechanism was able to take some shortcuts because\nof the limited CFG shapes it encountered.  Shortcut replaced and previous\nworkaround code removed.\n\nAlso fixes a regression introduced by the stack bounds checking change\nwhich sometimes resulted in an (opcode \u003c 0x200) assert failure, and\nremoves an optimization flag and associated code that no longer applicable.\n\nChange-Id: I617e9e5347dfd3a7e8f44a9772647bf4530631d6\n"
    },
    {
      "commit": "ec5adf351879cb6235faf2c6c068c2553d85a7d2",
      "tree": "f3f8e9ab69690e729a523188468d7150ede27bf7",
      "parents": [
        "005ab2eb9e9ab4762c00e73c7028de2850bd5108"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Sep 11 15:25:43 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Sep 11 18:14:46 2011 -0700"
      },
      "message": "Mark top of managed stack on helper transitions\n\nTo assist with unwind from a helper function, store current SP prior\nto helper call in Thread.  NOTE: we may wish to push this into a\ntrampoline to reduce code expansion.  NOTE #2:  Because any helper\nfunction which can throw will be non-leaf, it will spill lr at the saved\naddress - 4 (the word immediately below caller\u0027s Method*).  To identify\nthe callsite, load the spilled lr, clear the low bit, subtract 2, and use\nthat address in the native \u003c-\u003e dalvik mapping to identify the callsite.\n\nAlso in this CL are a ralloc fix and some extra SSA logging.\n\nChange-Id: Idd442f0c55413a5146c24709b1db1150604f4554\n"
    },
    {
      "commit": "0d966cff87464544a264efdbfba6c379474d5928",
      "tree": "74ce88ebfdb902c90700b20b6b4e82290b77e70b",
      "parents": [
        "34cd9e58431504c36d0cb2a8fd0f3fac16dcb406"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Sep 08 17:34:58 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Sep 08 17:54:29 2011 -0700"
      },
      "message": "Add suspend check \u0026 stub\n\nChange-Id: I017653026ca95166cbc4b6b94b5da1fef2597804\n"
    },
    {
      "commit": "0c7f26d54ddb70dbc60aaaa6a6e9f011e402018f",
      "tree": "ebe5eb3c9f97386ff93b5b79f434d0de687f0c65",
      "parents": [
        "109bd6a38d0cd7c4b7797a9f2db8324c797d1368"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Sep 07 12:28:51 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Sep 07 12:28:51 2011 -0700"
      },
      "message": "Fixes for register promotion; enable fast path\n\nHad an off-by-one error in the range argument loading (only mattered when\nregister promotion is enabled - for range args we do a memory copy and\nmust ensure that all promoted values are flushed to memory before the\ncopy.  Also reworked and removed some asserts for sitations that are\nlegal now that we\u0027re promoting.  Enabled fast path code to exercise it\na bit.\n\nChange-Id: Id1acb3dad01d5d1077661150e98e51fd4243b6f1\n"
    },
    {
      "commit": "e9a72f6a1a84f4d9af0b07dd289b89e45ffb32d5",
      "tree": "0a709a3694d0a3fd11878d39b6422e5e997c8c94",
      "parents": [
        "7715c68b5f137ff5ffa4f2e1fee0a96fa6cfffb4"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Sep 04 17:59:07 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Sep 05 13:38:41 2011 -0700"
      },
      "message": "Try/Catch analysis; various workarounds\n\nFixed a couple of codegen bugs.  Added a temporary workaround until\nSSA renaming problem is fixed.  By enabling the \"CompileDexLibCore\"\ntest in compiler_test.cc and disabling the jni_compiler, we appear to\nbe successfully compiling 17,641 methods of libcore (note: of those,\n4 exhibit the SSA problem).\n\nAlso turned off most of the compiler logging, and disabled the fast\npath for invoke virtual (which seems to be broken).\n\nChange-Id: I0ecf460cba209f885209efbee62e9f80bffbf666\n"
    },
    {
      "commit": "2e748f364dba4505ca3a90f095d09c70bcd88eab",
      "tree": "16aae1898827bb16a0a1f826797139371ef5b456",
      "parents": [
        "ff0f9bea6355fe0c420815f9b894e6bb634fe764"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Aug 29 21:02:19 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Aug 29 21:18:53 2011 -0700"
      },
      "message": "Register temp handling fix\n\nIn general, compiler routines that generate code don\u0027t need to worry\nabout register management - the underlying utilites will take care of\nit.  However, when generating an invoke sequence specific registers must\nbe used to conform to the calling convention.  To prevent the normal\nutilities from allocating these fixed registers, oatLockAllTemps() is\ncalled to mark the registers as in use.  However, oatLockAllTemps() did\njust that - it locked all of the temps, not just those used for arguments.\n\nThis change renames oatLockAllTemps() to oatLockCallTemps() and restricts\nthe locking to the argument registers.\n\nChange-Id: Id4183ce89e2672bcf2873d31aa60bd80c91c5a72\n"
    },
    {
      "commit": "c5ef046ba4a484b08d0286393574396669a57c03",
      "tree": "331ef8c3b48daf7214457ff621932c0574269f1b",
      "parents": [
        "bafc342a37e423a19ac05f14800006ea9d67a941"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Aug 25 18:44:49 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Aug 25 18:44:49 2011 -0700"
      },
      "message": "Add slow-path code gen for static/direct invokes\n\nAlso added recursive fibonacci test, but conditionally compiled it out.\n\nChange-Id: Ic36e38dc7c428f1f9f299e2732e7f156ee492ed0\n"
    },
    {
      "commit": "9e0f9b0d3e2cd78092e5c4b66ce1edcd79c951ea",
      "tree": "ecdf662160bd3113de7b09c02a7c8156e3f768d1",
      "parents": [
        "69f5bc6759f256a146eefd8a7141d39fcc3b0421"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Aug 24 15:32:46 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Aug 24 15:47:44 2011 -0700"
      },
      "message": "Add switch and comparison tests. Fix ralloc bug\n\nWe normally have 5 registers in our temp pool, but up to 6 may be\nneeded for long 3-operand operations.  Added a workaround to temporarily\nadd lr to the temp pool in that specific case.\n\nMoved the bulk of the compiler_test code out of common_test.h into\ncompiler_test.h.  Added switch and compare unit tests.\n\nChange-Id: Ib449c49861acb5aaef716e8538e5818ba74522cb\n"
    },
    {
      "commit": "67bf885d62b1473c833bece1c9e0bb624e6ba391",
      "tree": "a6069d30bb0e25d4ed1f19d7a3c2b55c4aef7127",
      "parents": [
        "f4c21c9f6440c3980c47a297519f758796dbc039"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Aug 17 17:51:35 2011 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Aug 19 20:14:15 2011 -0700"
      },
      "message": "Oat compiler integration snapshot.\n\nCleanly compiles, but not integrated.  Old-world dependencies captured\nin hacked-up temporary files \"Dalvik.h\" and \"HackStubs.cc\".\n\nDalvik.h is a placeholder that captures all of the constants, struct\ndefinitions and inline functions the compiler needs.  It largely consists\nof declaration fragments of libdex, Object.h, DvmDex.h and Thread.h.\n\nHackStubs.cc contains empty shells for some required libdex routines.\n\nChange-Id: Ia479dda41da4e3162ff6df383252fdc7dbf38d71\n"
    }
  ]
}