)]}' { "log": [ { "commit": "70e97462116a47ef2e582ea29a037847debcc029", "tree": "ee587e35b9b9483c35875ccc8ddea139978ca823", "parents": [ "521691ae4dfad47cf6b46858347fa5fa32fd7bcc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 09 11:04:26 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 05 17:27:41 2016 +0100" }, "message": "Avoid excessive spill slots for slow paths.\n\nReducing the frame size makes stack maps smaller as we need\nfewer bits for stack masks and some dex register locations\nmay use short location kind rather than long. On Nexus 9,\nAOSP ToT, the boot.oat size reduction is\n prebuilt multi-part boot image:\n - 32-bit boot.oat: -416KiB (-0.6%)\n - 64-bit boot.oat: -635KiB (-0.9%)\n prebuilt multi-part boot image with read barrier:\n - 32-bit boot.oat: -483KiB (-0.7%)\n - 64-bit boot.oat: -703KiB (-0.9%)\n on-device built single boot image:\n - 32-bit boot.oat: -380KiB (-0.6%)\n - 64-bit boot.oat: -632KiB (-0.9%)\n on-device built single boot image with read barrier:\n - 32-bit boot.oat: -448KiB (-0.6%)\n - 64-bit boot.oat: -692KiB (-0.9%)\n\nThe other benefit is that at runtime, threads may need fewer\npages for their stacks, reducing overall memory usage.\n\nWe defer the calculation of the maximum spill size from\nthe main register allocator (linear scan or graph coloring)\nto the RegisterAllocationResolver and do it based on the\nlive registers at slow path safepoints. The old notion of\nan artificial slow path safepoint interval is removed as\nit is no longer needed.\n\nTest: Run ART test suite on host and Nexus 9.\nBug: 30212852\nChange-Id: I40b3d114e278e2c5807982904fa49bf6642c6275\n" }, { "commit": "521691ae4dfad47cf6b46858347fa5fa32fd7bcc", "tree": "bb9fdefaad92ac05e20c50e1a56a35454dad6576", "parents": [ "cb83389879f0c391996aad0f7435caffa4d6b30f", "8d49fd7b1087fba274a844cbf180349c528cf912" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 25 19:52:01 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 25 19:52:02 2016 +0000" }, "message": "Merge \"ArraySet without type check does not need read barrier.\"" }, { "commit": "ca11dc008457e1596554eb9b1b77c823ae9dcf54", "tree": "d88faea88303d905484d46ffeea9c36bc2fe7bf6", "parents": [ "8812e8fa4bd558b2797a9ad138c3910234097fad", "22f81d3b620581c98548dec3b0d6d575e012fed8" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 25 16:54:43 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 25 16:54:43 2016 +0000" }, "message": "Merge \"ARM64: Make runtime invokes use InvokeRuntime().\"" }, { "commit": "8812e8fa4bd558b2797a9ad138c3910234097fad", "tree": "46f7ee842f5601dcdb55c2ff5e0c4cccee3f619a", "parents": [ "24cbdc42f87d3329463cdd0af294265c3d0b650e", "be919d90adf8a5c68e6d4d5eea004a9d5be473d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 25 15:42:26 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 25 15:42:26 2016 +0000" }, "message": "Merge \"ARM64: Use the zero register for field and array set operations.\"" }, { "commit": "22f81d3b620581c98548dec3b0d6d575e012fed8", "tree": "7986c0bd60c9ee6a95fcfff489b20ffa62cf3ed8", "parents": [ "ce999e7c8af5f76a05ab0b2267ef7b74d25c75b5" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Feb 18 16:06:31 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 25 15:38:23 2016 +0000" }, "message": "ARM64: Make runtime invokes use InvokeRuntime().\n\nThis patch refactors all of the ARM64 Optimizing compiler runtime\ninvokes to use InvokeRuntime(). It also fixes some misuses of\nRecordPcInfo().\n\nTest: m test-art-target + Nexus 6 boot test\nChange-Id: Ia3e477c42fb14c62b81e50daa5811185071bafa6\n" }, { "commit": "8d49fd7b1087fba274a844cbf180349c528cf912", "tree": "128be6aa83734b09ecf189a70525570555a4d8cb", "parents": [ "082bfec57684bd93dcca0800d030c12fd448127f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 25 15:20:47 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 25 15:24:05 2016 +0100" }, "message": "ArraySet without type check does not need read barrier.\n\nTest: Run ART test suite with ART_USE_READ_BARRIER\u003dtrue on host and Nexus 9.\nBug: 12687968\nChange-Id: Ie04a34b2149f4fc6fe995f3e43e76986a3f6330f\n" }, { "commit": "be919d90adf8a5c68e6d4d5eea004a9d5be473d2", "tree": "f6fb545811b724bfc78f34089b866f606c5b9d8a", "parents": [ "7c95b4e22897a6f14ef79ec6e547e2eed686814a" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 23 18:33:36 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 25 13:53:51 2016 +0000" }, "message": "ARM64: Use the zero register for field and array set operations.\n\nTest: Run ART test suite on host and Nexus 9.\nChange-Id: I4e2a81570ecc57530249672df704eb0bb780acce\n" }, { "commit": "a518c150add36b71aaaf9b904d9f5b4ad61b8c8c", "tree": "7daa4cc425a5e29179e310646f9c99ce2ebf84b1", "parents": [ "c8cbbf518d8a23fecaedb22c71e44ef3736b08e2", "ba6b679bd34449ec56508966706ca1b8d5e7cb17" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 25 12:19:36 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 25 12:19:36 2016 +0000" }, "message": "Merge \"ARM: Purge Arm32Assembler.\"" }, { "commit": "2923db7314da613d50c9e6e44f38bb8d3e1c49f0", "tree": "063590a45f9f384872b8fa14f9f0bd2f014f0d66", "parents": [ "897b8f5da90b38b030826273f4c9bd8fbc32759e" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Aug 20 01:55:47 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Aug 24 17:27:35 2016 -0700" }, "message": "MIPS32: Refactor implicit null checks in array/field get/set.\n\nRationale: on MIPS32 64-bit loads and stores may be performed\nas pairs of 32-bit loads/stores. Implicit null checks must be\nassociated with the first 32-bit load/store in a pair and not\nthe last. This change ensures proper association of said checks\n(a few were done after the last 32-bit load/store in a pair)\nand lays ground for further improvements in array/field get/set.\n\nTest: booted MIPS32 in QEMU\nTest: test-art-host-gtest\nTest: test-art-target-run-test-optimizing in QEMU\n\nChange-Id: I3674947c00bb17930790a7a47c9b7aadc0c030b8\n" }, { "commit": "953437bd51059801d92079295f728d0260efca31", "tree": "b52816b5092a143361ea3878ef0e06d311c4a56f", "parents": [ "c67d22ac6db73aaa9540294c86344bf8021495b3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 08:30:46 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 24 13:20:32 2016 +0100" }, "message": "Revert \"Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\"\n\nFixed the fault handler recognizing the TEST instruction and\nfault address within the lock word. Added tests to 439-npe.\n\nBug: 29966877\nBug: 12687968\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\n\nThis reverts commit ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15.\n\nChange-Id: I8990def5f719c9205bf6e5fdba32027fa82bec50\n" }, { "commit": "ccf15bca330f9a23337b1a4b5850f7fcc6c1bf15", "tree": "8e271269eb0f3e40388311478fe441bfeb47ab47", "parents": [ "ccf06d8f19a37432de4a3b768747090adfbd18ec" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 17:48:38 2016 +0000" }, "message": "Revert \"x86/x86-64: Avoid temporary for read barrier field load.\"\n\nFault handler does not recognize the instruction\n F6 /0 ib TEST r/m8, imm8\nso we get crashes instead of NPEs.\n\nBug: 29966877\nBug: 12687968\n\nThis reverts commit ccf06d8f19a37432de4a3b768747090adfbd18ec.\n\nChange-Id: Ib7db3b59f44c0d3ed5e24a20b6c6ee596a89d709\n" }, { "commit": "ccf06d8f19a37432de4a3b768747090adfbd18ec", "tree": "fcb3ba46184db6882e695cecf1cfe495417593ae", "parents": [ "cf834d00de838272cf28f2382ffc26fe716aae5c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 12 13:37:55 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 23 11:41:44 2016 +0100" }, "message": "x86/x86-64: Avoid temporary for read barrier field load.\n\nAdd TEST instructions for memory and immediate. Use the byte\nversion to avoid a temporary in read barrier field load.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue ART_HEAP_POISONING\u003dtrue on host.\nBug: 29966877\nBug: 12687968\nChange-Id: Ia415d3c2e1ae1ff6dff11d72bbb7d96d5deed6ee\n" }, { "commit": "cf834d00de838272cf28f2382ffc26fe716aae5c", "tree": "8e271269eb0f3e40388311478fe441bfeb47ab47", "parents": [ "5f81cd04135b2153dcafa636f0bd0802469dac9f", "b6a12832943fcf838d89134158208c8a2e47f49f" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Aug 23 02:57:21 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 23 02:57:21 2016 +0000" }, "message": "Merge \"Use full pass name when building optimizations\"" }, { "commit": "5f81cd04135b2153dcafa636f0bd0802469dac9f", "tree": "0c249178440c60f3e65650beeff1aa3b321236bb", "parents": [ "38d4d5490397c71bcd5a9ce32ce497b825f870b7", "07f712f6d083ec0589e7a0c5e4712809eea19a30" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Aug 23 02:49:26 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 23 02:49:26 2016 +0000" }, "message": "Merge \"MIPS32: Optimize R6 round(float) intrinsic.\"" }, { "commit": "b6a12832943fcf838d89134158208c8a2e47f49f", "tree": "c85a7b7f0469447f3ed41ca6c4a4a6b975a4fbbc", "parents": [ "82a4c22ef4277faa08bf588c560c3dddcca559d2" ], "author": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Tue Aug 16 16:33:00 2016 -0700" }, "committer": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Tue Aug 23 00:45:36 2016 +0000" }, "message": "Use full pass name when building optimizations\n\nIf possible, use full pass name provided in --run-passes rather\nthan its base version.\n\nTest: m test-art-host -j32\n\n1. Prepare a run-passes file with content:\ndead_code_elimination$initial\ninstruction_simplifier\nx86_memory_operand_generation\n2. Run art for a dex file like:\nart -Xcompiler-option --run-passes\u003drun-passes -Xcompiler-option\n--dump-passes -classpath classes.dex Test\n3. Verify that dead_code_elimination$initial string is present in\ndump-passes output.\n\nChange-Id: I92d9ed0c8b919ea03f625f549123f546dffe546b\n" }, { "commit": "792c98bb773c8c2390f9cbf774f85be9d9a75332", "tree": "118711491155a6cac349b895268d79e808ebcd33", "parents": [ "449fe8790c7e9addfc1416da1e07e6a3865acf7e", "372f3a374681ef11f003460e14249adb7bc8313d" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Aug 22 15:01:24 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 22 15:01:24 2016 +0000" }, "message": "Merge \"ART: Add thread offset printing hook to disassembler\"" }, { "commit": "372f3a374681ef11f003460e14249adb7bc8313d", "tree": "b6d2bd95975a0ce1096dc2aa761f8e6b30e42b18", "parents": [ "9c07ab332b8ebbcb1586c311bfcb75e19b8a35b4" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 10:49:06 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 16:46:56 2016 -0700" }, "message": "ART: Add thread offset printing hook to disassembler\n\nTo prepare separation of disassembler from libart, add a function\nhook to the disassembler options for thread offset name printing.\n\nBug: 15436106\nChange-Id: I9e9b7e565ae923952c64026f675ac527b560f51b\n" }, { "commit": "7a687680e2127d351bbdb3b301ec5d27b68c7d14", "tree": "74f69c91aa18af6cb475f3a15019b27d124e6f81", "parents": [ "679e38bad57c70a47ededd4dfcde178c7b3969ff", "5a5d0faab643eb07ba33d91d47484878c1450b44" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Aug 19 21:53:57 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 19 21:53:58 2016 +0000" }, "message": "Merge \"ART: Fixing build breakage (sharpening DCHECK).\"" }, { "commit": "5a5d0faab643eb07ba33d91d47484878c1450b44", "tree": "f006ca8a9a374751a4f17fb1227bb40b58cc704e", "parents": [ "9210ce973ea180f6c5109f262068d433b1da5bc0" ], "author": { "name": "Christina Wadsworth", "email": "cwadsworth@google.com", "time": "Fri Aug 19 14:38:01 2016 -0700" }, "committer": { "name": "Christina Wadsworth", "email": "cwadsworth@google.com", "time": "Fri Aug 19 14:38:01 2016 -0700" }, "message": "ART: Fixing build breakage (sharpening DCHECK).\n\nChange-Id: I7ba19808dde0712739a278075da57f724166a233\n" }, { "commit": "75214833572bcdebd498f566212b9240cdd66fcf", "tree": "ca6f684191fc713b4c019fd01f35ba06b158f931", "parents": [ "ca1d99f530429307bb9d13d7ca138a318bcb2670", "a75b01a549f0c86669dd24e53c9e3e74f0bf5b40" ], "author": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Fri Aug 19 20:16:29 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 19 20:16:29 2016 +0000" }, "message": "Merge \"Fix building tests with partial arch codegen support\"" }, { "commit": "a75b01a549f0c86669dd24e53c9e3e74f0bf5b40", "tree": "fbca55a54871421db00709e6bbb51e48c851069f", "parents": [ "3049b2a54b5b55d094fea603236f492c31b842e1" ], "author": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Thu Aug 18 13:45:24 2016 -0700" }, "committer": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Fri Aug 19 10:47:35 2016 -0700" }, "message": "Fix building tests with partial arch codegen support\n\nAdd conditionals around more code that is only used for codegen for\nspecific architectures, and move a few more files into the\narchitecture-specific codegen lists.\n\nTests: ART_HOST_CODEGEN_ARCHS\u003d\"x86_64 mips\" m -j ART_TARGET_CODEGEN_ARCHS\u003dsvelte test-art-host\nBug: 30928847\nChange-Id: I0444d15e1cafe4c9b13ff78718c3b13b544270e7\n" }, { "commit": "9c07ab332b8ebbcb1586c311bfcb75e19b8a35b4", "tree": "26a300b803f77e64c17e3d239a1880a4c5960666", "parents": [ "6670bd2098264d4c4e19750ab4741121da7ee54b", "bf44e0e5281de91f2e38a9378b94ef8c50ad9b23" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Aug 19 17:33:03 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 19 17:33:03 2016 +0000" }, "message": "Merge \"ART: Implement a fixed size string dex cache\"" }, { "commit": "6670bd2098264d4c4e19750ab4741121da7ee54b", "tree": "96d0e872b50daad88dbb77357c8e0102b1a4b69d", "parents": [ "f606c3a687e3eae94296ba74d2d820b6e37692ff", "0b671c0408e98824e1f92b1ee951b210c090fe7a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 15:07:31 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 19 15:07:31 2016 +0000" }, "message": "Merge \"Add support for Baker read barriers in SystemArrayCopy intrinsics.\"" }, { "commit": "0b671c0408e98824e1f92b1ee951b210c090fe7a", "tree": "0bc58c031cd899aa856677fe8c9ffa376228806f", "parents": [ "36bf3a2d281892e7906d3eaf9d7455b0656c9a25" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 12:02:34 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 19 16:00:09 2016 +0100" }, "message": "Add support for Baker read barriers in SystemArrayCopy intrinsics.\n\nBenchmarks (ARM64) score variations on Nexus 5X with CPU\ncores clamped at 960000 Hz (aosp_bullhead-userdebug build):\n- Ritzperf - average (lower is better): -3.03% (slightly better)\n- CaffeineMark - average (higher is better): +1.26% (slightly better)\n- DeltaBlue (lower is better): -10.50% (better)\n- Richards - average (lower is better): -3.36% (slightly better)\n- SciMark2 - average (higher is better): +0.26% (virtually unchanged)\n\nDetails about Ritzperf benchmarks with meaningful variations\n(lower is better):\n- FormulaEvaluationActions.EvaluateAndApplyChanges: -13.26% (better)\n- FormulaEvaluationActions.EvaluateCascadingSums: -10.94% (better)\n- FormulaEvaluationActions.EvaluateComplexFormulas: -15.50% (better)\n- FormulaEvaluationActions.EvaluateFibonacci: -10.41% (better)\n- FormulaEvaluationActions.EvaluateLargeSums: +6.02% (worse)\n\nBoot image code size variation on Nexus 5X\n(aosp_bullhead-userdebug build):\n- total ARM64 framework Oat files size change:\n 107047632 bytes -\u003e 107154128 bytes (+0.10%)\n- total ARM framework Oat files size change:\n 90932028 bytes -\u003e 91009852 bytes (+0.09%)\n\nTest: ART host and target (ARM, ARM64) tests + Nexus 5X boot.\nBug: 29516905\nBug: 29506760\nBug: 12687968\nChange-Id: I85431368d09965687a0301ae2eb3c991f276ce5d\n" }, { "commit": "ba6b679bd34449ec56508966706ca1b8d5e7cb17", "tree": "ec5985cc0f9e8a75c717513954d25d69e526065e", "parents": [ "f606c3a687e3eae94296ba74d2d820b6e37692ff" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Aug 15 14:22:07 2016 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Aug 19 10:39:23 2016 +0100" }, "message": "ARM: Purge Arm32Assembler.\n\nUse Thumb2Assembler always. This originated from finding out that\nthe JNI tests are run using the Arm32Assembler however in real\nworld Thumb2Assembler is used for JNI. Therefore Arm32Assembler\ncode is dead except its own tests and the illegitimate use in\nJNI tests.\n\nChange-Id: I9ca6b83582bf97149a46690518ccb9312b1a3b68\n" }, { "commit": "96954301ee5b6603a4423854d02d87b28b6f4721", "tree": "21733867ebc30f03663106b340aa8aaa33f6bb03", "parents": [ "35938f90ef69fb030b18f2f7fb21f9b78620914b", "b6722fff3bedb867062b7ad369182f431dd98191" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 19 00:30:44 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 19 00:30:45 2016 +0000" }, "message": "Merge \"Color spill slots in gc regalloc\"" }, { "commit": "35938f90ef69fb030b18f2f7fb21f9b78620914b", "tree": "79619376bb6920c4a1b84e8f974a2abb54916eb7", "parents": [ "3049b2a54b5b55d094fea603236f492c31b842e1", "e706070b271945d60229736a15bb712f3061fd15" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 18 23:35:09 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 18 23:35:09 2016 +0000" }, "message": "Merge \"Log optimization passes in verbose mode\"" }, { "commit": "bf44e0e5281de91f2e38a9378b94ef8c50ad9b23", "tree": "bb6e65a3434806dc58f286ee75ad3b78ba9d6c36", "parents": [ "d99565069c64fefc069005286de04599dc2619b8" ], "author": { "name": "Christina Wadsworth", "email": "cwadsworth@google.com", "time": "Thu Aug 18 10:37:42 2016 -0700" }, "committer": { "name": "Christina Wadsworth", "email": "cwadsworth@google.com", "time": "Thu Aug 18 16:18:36 2016 -0700" }, "message": "ART: Implement a fixed size string dex cache\n\nPreviously, the string dex cache was dex_file-\u003eNumStringIds() size, and\n@ruhler found that only ~1% of that cache was ever getting filled. Since\nmany of these string dex caches were previously 100,000+ indices in\nlength, we\u0027re wasting a few hundred KB per app by storing null pointers.\nThe intent of this project was to reduce the space the string dex cache\nis using, while not regressing on time that much. This is the first of a\nfew CLs, which implements the new fixed size array and disables the\ncompiled code so it always goes slow path. In four other CLs, I\nimplemented a \"medium path\" that regresses from the previous \"fast path\"\nonly a bit in assembly in the entrypoints. @vmarko will introduce new\ncompiled code in the future so that we ultimately won\u0027t be regressing on\ntime at all. Overall, space savings have been confirmed as on the order\nof 100 KB per application.\n\nA 4-5% slow down in art-opt on Golem, and no noticeable slow down in the\ninterpreter. The opt slow down should be diminished once the new\ncompiled code is introduced.\n\nTest: m test-art-host\n\nBug: 20323084\n\nChange-Id: Ic654a1fb9c1ae127dde59290bf36a23edb55ca8e\n" }, { "commit": "e28c7d022b73cff58d0a9bcbaa5cfdc0950fe003", "tree": "479dbf47819e5b0ae5a6aabcceafe4e08e90d90c", "parents": [ "c6efcaa17319e9f81def246c277fec523f5b85e0" ], "author": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Wed Aug 17 19:15:51 2016 -0700" }, "committer": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Thu Aug 18 02:50:05 2016 +0000" }, "message": "Fix optimizing compiler not building for svelte\n\nFixes compiler not building when some of the codegen paths\nare disabled.\n\nTest: mmma -j art ART_TARGET_CODEGEN_ARCHS\u003dsvelte\nm -j32 test-art-host\n\nBUG\u003d30928847\n\nChange-Id: I52c78e8a4e507f74b1f2a39352970079721b737e\n" }, { "commit": "e706070b271945d60229736a15bb712f3061fd15", "tree": "b8951b25bf06733b5aa022aeff444033831f1654", "parents": [ "3cc35c324b748c41be92a51eae68b77846b4c243" ], "author": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Tue Aug 16 17:31:19 2016 -0700" }, "committer": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Thu Aug 18 01:36:04 2016 +0000" }, "message": "Log optimization passes in verbose mode\n\nIntroduce verbose logging of optimization passes run during\ncompilation.\n\nTest: m test-art-host -j32\nart -Xcompiler-option --runtime-arg -Xcompiler-option -verbose:compiler\n-classpath classes.dex Test\nChange-Id: Iae98ce9dcafc252f2d0eec138aa05b34e424bd2a\n" }, { "commit": "b6722fff3bedb867062b7ad369182f431dd98191", "tree": "7cbfdf3658404dc25a92e2ea66b7accb8e5ba6c3", "parents": [ "e70b9243ba8b11bc37dc2eb10dd95e4238ea240e" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Aug 12 19:07:11 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Wed Aug 17 14:42:14 2016 -0700" }, "message": "Color spill slots in gc regalloc\n\nColoring spill slots avoids pathologically large stack\nsizes by reusing spill slots when possible.\n\nTest: ART_TEST_OPTIMIZING_GRAPH_COLOR\u003dtrue m test-art-host\n\nChange-Id: I4b4aea859c78b0515758f8b057ee870dbbfc2300\n" }, { "commit": "3cc35c324b748c41be92a51eae68b77846b4c243", "tree": "615179a7897249b7e859a1875467bc9c9300f866", "parents": [ "3f410202b177416c785e6172138a265a91c81b0a", "9d4b6da934934c322536ee3309b63ce402740f49" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Aug 16 21:51:02 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 16 21:51:03 2016 +0000" }, "message": "Merge \"jni: Fast path for @FastNative annotated java methods\"" }, { "commit": "9d4b6da934934c322536ee3309b63ce402740f49", "tree": "9e7ee5023d6036b98e0560411bb0527efdedca01", "parents": [ "2af1aa066e3d20edd8fea5d5b6dbbbad73102d52" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Fri Jul 29 09:51:58 2016 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue Aug 16 20:19:36 2016 +0000" }, "message": "jni: Fast path for @FastNative annotated java methods\n\nAdds a faster path for java methods annotated with\ndalvik.annotation.optimization.FastNative .\n\nIntended to replace usage of fast JNI (registering with \"!(FOO)BAR\" descriptors).\n\nPerformance Microbenchmark Results (Angler):\n* Regular JNI cost in nanoseconds: 115\n* Fast JNI cost in nanoseconds: 60\n* @FastNative cost in nanoseconds: 36\n\nSummary: Up to 67% faster (vs fast jni) JNI transition cost\n\nChange-Id: Ic23823ae0f232270c068ec999fd89aa993894b0e\n" }, { "commit": "554b6fb8759d186eba1046c220c9cff9a8610525", "tree": "0b28f10d2235c82ba13f75829a018457d2ce9a66", "parents": [ "fe74ba9ea6c2c47a02d2ba7436b3a603b459468c", "4a3aa578eff94eb10450fae1772deb7cb8ddc6a6" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Aug 15 14:35:48 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 15 14:35:48 2016 +0000" }, "message": "Merge \"Revert \"Enable IntermediateAddress for primitive arrays with read barriers.\"\"" }, { "commit": "4a3aa578eff94eb10450fae1772deb7cb8ddc6a6", "tree": "abb3aa17279c6a9edc9dd1c0691738a7f7c69a10", "parents": [ "12ecf0800d465acdaa3deccd383ff8ed3428a183" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 15 13:17:06 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 15 13:17:06 2016 +0000" }, "message": "Revert \"Enable IntermediateAddress for primitive arrays with read barriers.\"\n\nThis CL breaks the angler-userdebug build with\n`ART_USE_READ_BARRIER\u003dtrue`.\n\nTest: Build angler-userdebug with `ART_USE_READ_BARRIER\u003dtrue`.\nBug: 30762467\nBug: 26601270\nBug: 12687968\n\nThis reverts commit 12ecf0800d465acdaa3deccd383ff8ed3428a183.\n\nChange-Id: Ia2069ac9436d2336311dd8d0f183c02e587586ae\n" }, { "commit": "fe74ba9ea6c2c47a02d2ba7436b3a603b459468c", "tree": "a3bba08767d44b60a38af6a0ad67dacb260d4daa", "parents": [ "85b1811f0de0cb8fb2a9ae37f53c6056a2de6867", "af4e42a0d210aa3aa5d52926536b2ca5c2952934" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 15 10:03:32 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 15 10:03:32 2016 +0000" }, "message": "Merge \"ARM64: VIXL: Support a newer version of VIXL.\"" }, { "commit": "912cc4aad303d4de0cae8d26d8094a916d93752b", "tree": "890fb8ef5d30a9fd5c00af7f96f6e38adc1b6487", "parents": [ "ef1a3209ab59008d402045a17379fb1f13a21e7b", "2ccae4a5fe6efbebd22cc2ad3a845829b695f670" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 12 22:07:41 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 12 22:07:41 2016 +0000" }, "message": "Merge \"Revert \"Revert \"Iterative move coalescing for gc regalloc\"\"\"" }, { "commit": "ba1642dec60c053895c259deac429463669ddc9b", "tree": "57f8a1d11b4774b9a1ea38bec459ee1127ce3595", "parents": [ "82d33b295fecf472a98435b7fc8e4652d4c78542", "1aa559d49b55b72de2da77734dc69704733af269" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 12 20:54:05 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 12 20:54:06 2016 +0000" }, "message": "Merge \"Use TestCodeGeneratorX86 in codegen unit tests\"" }, { "commit": "2ccae4a5fe6efbebd22cc2ad3a845829b695f670", "tree": "43b269041f0ed7144ca223da20623727e5d59722", "parents": [ "82d33b295fecf472a98435b7fc8e4652d4c78542" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Aug 12 16:10:45 2016 +0000" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Aug 12 13:30:38 2016 -0700" }, "message": "Revert \"Revert \"Iterative move coalescing for gc regalloc\"\"\n\nThis reverts commit 6f61ee5623a676ce983ccfa1aba9b2ae1237e163,\nand fixes the arena allocator issues in the original CL.\nFunctionality from the original CL has not changed.\n\nTest: m valgrind-test-art-host-gtest-register_allocator_test\nTest: ART_TEST_OPTIMIZING_GRAPH_COLOR\u003dtrue m test-art-host-run-test\n\nChange-Id: Idd979f4e03f0c2800e0c07a0a7d392c8a4230aab\n" }, { "commit": "af4e42a0d210aa3aa5d52926536b2ca5c2952934", "tree": "b64d683ba6ac11c0b7730df9a579aead2905dfff", "parents": [ "dce74be0c49e8a540affc0b5649a9cf8756b809b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Aug 08 15:11:24 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Aug 12 13:22:34 2016 +0100" }, "message": "ARM64: VIXL: Support a newer version of VIXL.\n\nPlease note that compiling VIXL with -Wshadow is a known VIXL issue.\n\nThis will be resolved in a later version of VIXL, when we can drop\nthe deprecated API for getters and setters.\n\nFor more info take a look at VIXL_DEPRECATED in the VIXL source code.\n\nChange-Id: Iea30b1a7b065f9b16a92c6cc7ebdc50ef068b348\n" }, { "commit": "7cbd27fe778f2c348136540d52b5473e28f5769d", "tree": "80c0fa4ff2a223c061245c6799d992cd4d863fa0", "parents": [ "3d1d18d74dfac5039b6093ddf04f74eee4f157a3" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 11 23:53:33 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 12 13:19:51 2016 +0100" }, "message": "Adjust spacing before NOLINT comments in ART.\n\nNote that neither clang-tidy nor cpplint.py complain about\nthese style \"issues\", precisely because of the NOLINT\ncomments.\n\nTest: WITH_TIDY\u003d1 WITH_TIDY_CHECKS\u003d\u0027-*,misc-macro-parentheses\u0027 mmma art\nChange-Id: Id692fd394ffbd4fe208cbbe4407b4d5e208462bb\n" }, { "commit": "0c283627c0280d271c602baba9ffcffecb067c03", "tree": "10b8b274e0f6771a89bc522559940978a8134ce5", "parents": [ "eef560e257368c62bcefe6a9023f78b830fefd25", "6f61ee5623a676ce983ccfa1aba9b2ae1237e163" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 12 08:01:43 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 12 08:01:43 2016 +0000" }, "message": "Merge \"Revert \"Iterative move coalescing for gc regalloc\"\"" }, { "commit": "6f61ee5623a676ce983ccfa1aba9b2ae1237e163", "tree": "d4367d5707b5c5fa918387da6ea1844e063073d2", "parents": [ "465ed699e810868fe5bb39730e6d149a4734372d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 12 06:33:15 2016 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 12 06:33:15 2016 +0000" }, "message": "Revert \"Iterative move coalescing for gc regalloc\"\n\nThere are lifetime issues with allocators and coloring\niterations that got flagged by valgrind.\n\nThis reverts commit 465ed699e810868fe5bb39730e6d149a4734372d.\n\nChange-Id: I9e08172321af61d109c116a4f0742fa809e8094b\nTest: m test-art-host\n" }, { "commit": "592c9bd2ad30480ba058e689be976e7a2107595a", "tree": "352a8baef419a813fd914e88dd80ac1ab2b49938", "parents": [ "9d32586b52893a82c5094821d32c4f2d4d201795", "465ed699e810868fe5bb39730e6d149a4734372d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 12 01:43:26 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 12 01:43:26 2016 +0000" }, "message": "Merge \"Iterative move coalescing for gc regalloc\"" }, { "commit": "1aa559d49b55b72de2da77734dc69704733af269", "tree": "f7093a05da05ed4455e64ef2c87b543e4280fb6b", "parents": [ "9d32586b52893a82c5094821d32c4f2d4d201795" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Thu Aug 11 17:20:05 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Thu Aug 11 17:32:19 2016 -0700" }, "message": "Use TestCodeGeneratorX86 in codegen unit tests\n\nThe codegen unit tests are supposed to use special \"test\" code\ngenerators when targeting ARM and x86 (due to differing calling\nconventions between the C++ source code and the generated code),\nyet TestCodeGeneratorX86 was not being used. This fixes that.\n\n(The tests were only succeeding because the register allocator happened\nto not assign the EBX register.)\n\nTest: m test-art-host-gtest-codegen_test\n\nChange-Id: Ia3dd6998c38e9ff27b8c2734457f86b3fed44ab4\n" }, { "commit": "465ed699e810868fe5bb39730e6d149a4734372d", "tree": "a53b71b2bebb31e5e75b0c649cf7e48058728dee", "parents": [ "71572de11618275ac7a093a3bf3815c3dbdc2510" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Jul 22 08:52:13 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Thu Aug 11 13:17:02 2016 -0700" }, "message": "Iterative move coalescing for gc regalloc\n\nImplement iterative move coalescing for graph coloring\nregister allocation. Based on Andrew Appel\u0027s implementation\nin \"Modern Compiler Implementation in Java\", modified to\nsupport constraints such as pair intervals.\n\nTest: ART_TEST_OPTIMIZING_GRAPH_COLOR\u003dtrue m test-art-host\n\nChange-Id: I8642297d3bd798a4fc4de4b356ac3304098471a5\n" }, { "commit": "9d32586b52893a82c5094821d32c4f2d4d201795", "tree": "357164c78a92269cdf3f7b196f8b544fbbd1fadd", "parents": [ "0c7972c6c29a8f6595a8f656b16d8ace42db990b", "961ea1286f670a9ac9fc673308a9cf56137acb95" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 11 18:41:55 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 11 18:41:55 2016 +0000" }, "message": "Merge \"x86/x86-64: Shorter fast-path for read barrier field load.\"" }, { "commit": "0c7972c6c29a8f6595a8f656b16d8ace42db990b", "tree": "776c319956588842a54a797d6cd7a5b4b1f196ba", "parents": [ "c531c217942b2304e40c54083b471baf5d994236", "2ea915326b0ff9e07f0b3ecb68b78f7d3200d200" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 11 18:37:50 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 11 18:37:51 2016 +0000" }, "message": "Merge \"ARM64: Use libvixld when compiling for debug mode.\"" }, { "commit": "c531c217942b2304e40c54083b471baf5d994236", "tree": "fd9ce951b4556e09c13eb070cebb00f07fed9732", "parents": [ "33699c9529add1c1ec4bb5dcb0807942709de224", "0cf8d9c08bb77b0f527121b83e6a9dbb36d602f3" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 11 18:24:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 11 18:24:10 2016 +0000" }, "message": "Merge \"Full enable new round implementation on x86/x86_64\"" }, { "commit": "2ea915326b0ff9e07f0b3ecb68b78f7d3200d200", "tree": "c7ac53f09bb71eb6da19b0a71435774637765942", "parents": [ "33699c9529add1c1ec4bb5dcb0807942709de224" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Thu Aug 11 17:04:14 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Thu Aug 11 17:04:14 2016 +0100" }, "message": "ARM64: Use libvixld when compiling for debug mode.\n\nVIXL debug mode checks are valuable to catch dangerous code that can\nlead to bugs.\n\nThis patch includes a couple of fixes for issues spotted by VIXL in debug mode.\n\nChange-Id: I388ae1ffd9256ad74d0b6ce06f79cc7927a5f28a\n" }, { "commit": "961ea1286f670a9ac9fc673308a9cf56137acb95", "tree": "e4158b237c7527d18be3e9fbf5bac322df935aee", "parents": [ "33699c9529add1c1ec4bb5dcb0807942709de224" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 11 14:16:57 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 11 14:17:21 2016 +0100" }, "message": "x86/x86-64: Shorter fast-path for read barrier field load.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on host.\nBug: 29966877\nBug: 12687968\nChange-Id: I73359495910dacb2cc28f1a21ef9e610bab5a476\n" }, { "commit": "0cf8d9c08bb77b0f527121b83e6a9dbb36d602f3", "tree": "dcdc448217614142e5327ca7a823e59030ae15ed", "parents": [ "3f3201a89ec19257b3bc93c25b20abdcfe61f3e4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Aug 10 14:05:54 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Aug 10 14:05:54 2016 -0700" }, "message": "Full enable new round implementation on x86/x86_64\n\nRationale:\nRunning JIT on Fugu does not always provide a constant area.\nIn such cases, we need to construct FP constants through stack.\nThis only applies to x86.\n\nTest: 580-checker-round\n\nBUG\u003d26327751\n\nChange-Id: I7e2c80dafbafbe647cfe9ecb039920bb534c666a\n" }, { "commit": "4997d14c8d0404269993986deff5ae1ae45ab712", "tree": "b125ba1053f987e13eb2890e342e37b872c524cf", "parents": [ "c218427ab96e521e0c4e9a3ffeb87e6c57eea0a5", "59751a7375196c530fbd048e72750aa94ab90431" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 10 13:29:15 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Aug 10 13:29:15 2016 +0000" }, "message": "Merge \"ARM: Embed constants in add/sub-long.\"" }, { "commit": "5319d3cca5a9b8e9e3f59421818272b966575172", "tree": "a90bd83b7e69bbff0be601088bb1c764125d8cf6", "parents": [ "9cff32df754c428ef69ddb61e7600abfd4c75266" ], "author": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Mon Aug 01 17:48:59 2016 -0700" }, "committer": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Mon Aug 08 11:24:26 2016 -0700" }, "message": "Implement running user defined list of passes\n\nThis change introduces new dex2oat switch --run-passes\u003d. This switch\naccepts path to a text file with names of passes to run.\nCompiler will run optimization passes specified in the file rather\nthen the default ones.\n\nThere is no verification implemented on the compiler side. It is user\u0027s\nresponsibility to provide a list of passes that leads to successful\ngeneration of correct code. Care should be taken to prepare a list\nthat satisfies all dependencies between optimizations.\n\nWe only take control of the optional optimizations. Codegen (builder),\nand all passes required for register allocation will run unaffected\nby this mechanism.\n\nChange-Id: Ic3694e53515fefcc5ce6f28d9371776b5afcbb4f\n" }, { "commit": "51616fb233df2760fd6002a02dce692f24b93fb6", "tree": "61766bfa4bb53bf8f57a6c2645e81d375aa902bf", "parents": [ "c10ad423024432df36f6360eafca8332d07b946a", "12ecf0800d465acdaa3deccd383ff8ed3428a183" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 08 10:16:43 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Aug 08 10:16:43 2016 +0000" }, "message": "Merge \"Enable IntermediateAddress for primitive arrays with read barriers.\"" }, { "commit": "12ecf0800d465acdaa3deccd383ff8ed3428a183", "tree": "229f7438b82c945f4b3221f6c1033eaf96a9a1c6", "parents": [ "d16ae7fe70d74091778e5952b7920df14866287f" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 08 10:18:37 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Aug 08 10:18:37 2016 +0100" }, "message": "Enable IntermediateAddress for primitive arrays with read barriers.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 26601270\nBug: 12687968\nChange-Id: I6736ba7b1809bece1bf3cd82c69e4f42a0d3c4a7\n" }, { "commit": "1568ed9bd7e8fda112bc3afcf6d139637f2c65ce", "tree": "84f69ce45c614a0c015109cfa655f298a6463e3b", "parents": [ "95a976a3d1842384ed71bcc6e6449de95ec69961", "2cd05b7d9976c0c7fa74d58cb1608c809e5c37d3" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Sat Aug 06 02:41:24 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Sat Aug 06 02:41:24 2016 +0000" }, "message": "Merge \"Add a register allocation strategy compiler option\"" }, { "commit": "2cd05b7d9976c0c7fa74d58cb1608c809e5c37d3", "tree": "5cb7751e491aeae7357ed357f2a52702bf16854a", "parents": [ "11a59a48474caa818ddf344575aa6afc51f45590" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Wed Aug 03 16:57:37 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Sat Aug 06 01:21:14 2016 +0000" }, "message": "Add a register allocation strategy compiler option\n\nTest: manually, on device.\n\nChange-Id: If007a1657dd5769ddef03691e0a19dbbe6ba1a29\n" }, { "commit": "2ac06bc507d3e8bc0cf2a6274780f9b5d336cb4b", "tree": "116eeceb2a2d8273accc9c83432dec4db18a0c0a", "parents": [ "d9ffd0dd7266f6a5e76f29d98dbe1a04f64cbb9b" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Aug 05 09:34:52 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Aug 05 14:10:27 2016 -0700" }, "message": "Test all register allocators in regalloc gtest\n\nPreviously, the gtest only exercised the default register allocator.\nNote that the line count is high due mostly to whitespace changes.\n\nTest: m test-art-host-gtest-register_allocator_test\n\nChange-Id: I783edf98ae11d605d4f69834866c387abb71d34f\n" }, { "commit": "d9ffd0dd7266f6a5e76f29d98dbe1a04f64cbb9b", "tree": "7589320b18206648538734493fe5590023fecf5c", "parents": [ "fe5c430e6ef71e8f8932ece9631a4e9bfc8b7916" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Wed Jun 22 10:27:55 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Aug 05 13:24:41 2016 -0700" }, "message": "Implement a graph coloring register allocator\n\nTest: m test-art-host\n\nChange-Id: I8c0d77f339ab02b33588a54b96ecce5c8322cfce\n" }, { "commit": "59751a7375196c530fbd048e72750aa94ab90431", "tree": "98c1649266004d0b9c26a5f5e53613a9d1608a8b", "parents": [ "9526d13c791b3c95ae3f22e0be4d695e8be5708c" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 05 14:37:27 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 05 19:17:53 2016 +0100" }, "message": "ARM: Embed constants in add/sub-long.\n\nTest: 538-checker-embed-constants\nTest: Run ART test suite on Nexus 5.\nChange-Id: Ib9639748c74d5c56dc354a6830987b613b922654\n" }, { "commit": "9526d13c791b3c95ae3f22e0be4d695e8be5708c", "tree": "072f25eace49bb34285c9b4a8de384582f134fbf", "parents": [ "ac152079c6ec514a4c0c03d2d0246fd4dec82d11", "7ad310dabb9c9b60f35f72c7b0736da602e7541a" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 04 22:20:33 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 04 22:20:34 2016 +0000" }, "message": "Merge \"Temporary disable new round implementation on x86/x86_64\"" }, { "commit": "ac152079c6ec514a4c0c03d2d0246fd4dec82d11", "tree": "bda2a4f773b0c96f11eff9e97d74865bb33522eb", "parents": [ "20b975cc5c5a1f4e6f0a8e525b5d2e63abc413df", "806f0122e923581f559043e82cf958bab5defc87" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 04 22:05:54 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 04 22:05:54 2016 +0000" }, "message": "Merge \"Add support for CallKind::kCallOnMainAndSlowPath\"" }, { "commit": "7ad310dabb9c9b60f35f72c7b0736da602e7541a", "tree": "3241de5f450b17fcae1a7dd074cd9ece1c73e454", "parents": [ "20b975cc5c5a1f4e6f0a8e525b5d2e63abc413df" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 04 14:28:21 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 04 14:28:21 2016 -0700" }, "message": "Temporary disable new round implementation on x86/x86_64\n\nRationale:\nFUGU is not happy\n\nTest: 580-checker-round\n\nBUG\u003d26327751\n\nChange-Id: If0ddea47a88e14b86d37080b8a18a6f8defcc8e6\n" }, { "commit": "349f388b8c75c674f3337e6474affb2bff91d507", "tree": "0f8f37d538b83c78cecbbbbf439cdfcfeed8dc33", "parents": [ "25dd953085f0c35a395bde468251c2b13e944282" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Aug 02 15:40:56 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 04 12:39:15 2016 -0700" }, "message": "Implement single-/double-precision round intrinsic in x86_64\n\nRationale:\nX86_64 does not provide a direct instruction for the\nrequired rounding and NaN and large positive numbers\nmust be dealt with too. This CL generates code that\ncorrectly implements SP and DP round.\n\nTest: 580-checker-round\n\nBUG\u003d26327751\n\nChange-Id: Ia7518e2c30afafba4e037e2d0c21e0ce926f0425\n" }, { "commit": "25dd953085f0c35a395bde468251c2b13e944282", "tree": "ca3c937de9a3a96238542eab64518015186f1dd3", "parents": [ "1a2e5e67bc6fd9df4154f0add1d1163af6aa9bf2", "2c9f495e8f8c1b367662a5a7a32d216b70d3bb18" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 04 17:53:49 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 04 17:53:50 2016 +0000" }, "message": "Merge \"Implement single-precision round intrinsic in x86\"" }, { "commit": "2c9f495e8f8c1b367662a5a7a32d216b70d3bb18", "tree": "69da2e9c6d337fe22273ae8bb2c417fb7177ce75", "parents": [ "89bd8358c0a69e8cd6456d81d88ef366e261f732" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Aug 01 16:52:27 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Aug 04 09:53:03 2016 -0700" }, "message": "Implement single-precision round intrinsic in x86\n\nRationale:\nX86 does not provide a direct instruction for the\nrequired rounding and NaN and large positive numbers\nmust be dealt with too. This CL generates code that\ncorrectly implements SP round in a reasonably\nefficient manner (I hope....)\n\nTest: 580-checker-round\n\nBUG\u003d26327751\n\nChange-Id: Ic5f4d9cff9c27c855a8ad577c51ed3ed37fb60cd\n" }, { "commit": "965c0b9f98a4acbec7be148291196e30784bba2d", "tree": "c9b53c36226535f2941d47a1ea222da114266680", "parents": [ "2e98023165349ab91855555f63fed8dad3c471fe", "952dbb19cd094b8bfb01dbb33e0878db429e499a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 04 14:44:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 04 14:44:10 2016 +0000" }, "message": "Merge \"Change suspend entrypoint to save all registers.\"" }, { "commit": "952dbb19cd094b8bfb01dbb33e0878db429e499a", "tree": "82932c2b00245042e2c129f3d4133f6431657da3", "parents": [ "df638c66d1f385d4e217b2ab22c5e48a7eefdef4" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 28 12:01:51 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 04 14:51:52 2016 +0100" }, "message": "Change suspend entrypoint to save all registers.\n\nWe avoid the need to save/restore registers in slow paths\nand get significant code size savings. On Nexus 9, AOSP:\n - 32-bit boot.oat: -1.4MiB (-1.9%)\n - 64-bit boot.oat: -2.0MiB (-2.3%)\n - other 32-bit oat files in dalvik-cache: -200KiB (-1.7%)\n - other 64-bit oat files in dalvik-cache: -2.3MiB (-2.1%)\n\nTest: Run ART test suite on host and Nexus 9 with gc stress.\nBug: 30212852\nChange-Id: I7015afc1e7d30341618c9200a3dc9ae277afd134\n" }, { "commit": "36a270ae4f288e49493432b7128f899ad579849e", "tree": "99f134bbfe111b1c42b1b0c19d8b65175a3e6fc8", "parents": [ "89bd8358c0a69e8cd6456d81d88ef366e261f732" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jul 28 18:08:51 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Aug 03 15:46:18 2016 -0700" }, "message": "Change one read barrier bit to mark bit\n\nOptimization to help slow path performance. When the GC marks an\nobject through the read barrier slow path. The GC sets the mark bit\nin the lock word of that reference. This bit is checked from the\nassembly entrypoint the common case is that it is set. If the bit is\nset, the read barrier knows the object is already marked and there is\nno work to do.\n\nTo prevent dirty pages in zygote and image, the bit is set by the\nimage writer and zygote space creation.\n\nEAAC score (lower is better):\nN9: 777 -\u003e 700 (average 31 of runs)\nN6P (960000 mhz): 1737.48 -\u003e 1442.31 (average of 25 runs)\n\nBug: 30162165\nBug: 12687968\n\nTest: N9, N6P booting, test-art-host, test-art-target all with CC\n\nChange-Id: Iae0cacfae221e33151d3c0ab65338d1c822ab63d\n" }, { "commit": "89bd8358c0a69e8cd6456d81d88ef366e261f732", "tree": "e024d9507acadbc0ea1c142a83e9a3221baf7718", "parents": [ "01b7982a45fe53218d432ed1e8172d9d032d93ab", "b2b753c85433d81bcf44ad35b7b053d8fc753148" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 03 17:56:02 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Aug 03 17:56:03 2016 +0000" }, "message": "Merge \"ARM64: Use the zero register in the parallel-move resolver.\"" }, { "commit": "a7426c6a9ceeec193f6d886df7d0dcb3018f919d", "tree": "51e3513626ec0faf4ed648032e498bbd5e9c40d9", "parents": [ "d16ae7fe70d74091778e5952b7920df14866287f" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 03 15:02:10 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 03 15:05:43 2016 +0100" }, "message": "Fix an assertion in the non-Baker read barrier ARM64 slow path.\n\nTest: m ART_USE_READ_BARRIER\u003dtrue ART_READ_BARRIER_TYPE\u003dTABLELOOKUP test-art-target (ARM64).\nBug: 30563701\nChange-Id: Ib7969bd78e9c14cc2be9d5527d80385486b4f409\n" }, { "commit": "b2b753c85433d81bcf44ad35b7b053d8fc753148", "tree": "a10d2fd40109c5ca4a31e78a1de9cc3b83d2ca18", "parents": [ "d16ae7fe70d74091778e5952b7920df14866287f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 02 13:45:28 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Aug 03 09:24:31 2016 +0100" }, "message": "ARM64: Use the zero register in the parallel-move resolver.\n\nWhen moving zero to a stack slot, this will change\n\n mov temp, #0\n str temp, [...]\n\ninto\n\n str zr, [...]\n\nChange-Id: I2211b00d70f3fa0a02e781c90198757290b2bf89\n" }, { "commit": "b7e921c90540e87f73a14a232435b752ab12e906", "tree": "646c456b9952580c35e5bd0c5a32e24031c2afe7", "parents": [ "524a76c93347d7c23ad75b58eec997219b352ead", "c2c52a18a210b3c3c2a2a4345019b9d961a29f49" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Aug 02 20:18:27 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 02 20:18:28 2016 +0000" }, "message": "Merge \"Improve the graph visualizer\u0027s output for constant locations.\"" }, { "commit": "524a76c93347d7c23ad75b58eec997219b352ead", "tree": "e429889eb682be16f382c1534a6b0d298eba9155", "parents": [ "8055598c8dd4f3cd4d8490b5fc576161467f8bcb", "087930f2be5a628c65db280a73fecf468899d983" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Aug 02 20:06:39 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 02 20:06:39 2016 +0000" }, "message": "Merge \"ARM64: Make the VIXL macro assembler part of ART ARM64\u0027s assembler.\"" }, { "commit": "087930f2be5a628c65db280a73fecf468899d983", "tree": "d7fbf94ce260ddbb722a3731fe393bc9ef6e1bbc", "parents": [ "3d6094531e3790b25c43e59fd6cd0b6b99d3447c" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 02 13:45:28 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 02 15:47:28 2016 +0000" }, "message": "ARM64: Make the VIXL macro assembler part of ART ARM64\u0027s assembler.\n\nThis avoids a dynamic allocation of the VIXL macro assembler.\n\nChange-Id: I4cd62678d0978f1ad6f32ea0ce7279e09152be38\n" }, { "commit": "c2c52a18a210b3c3c2a2a4345019b9d961a29f49", "tree": "47b4e7923ba4fcf83367a699f90a53d5abb61ee7", "parents": [ "3d6094531e3790b25c43e59fd6cd0b6b99d3447c" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 02 13:45:28 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Aug 02 13:45:58 2016 +0100" }, "message": "Improve the graph visualizer\u0027s output for constant locations.\n\nChange-Id: I423fb378ee61fb53c3b328fc74f4e95cdef0992a\n" }, { "commit": "3719016185859778fa562d02140d04004c21d9a7", "tree": "30a2401e0576370bff32375fc87856739559379e", "parents": [ "3d6094531e3790b25c43e59fd6cd0b6b99d3447c", "37dd80d701fc5f55ed5a88ce2a495bf6eeb4a321" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 02 12:31:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 02 12:31:10 2016 +0000" }, "message": "Merge \"ARM: Embed 0.0 in VCMP.\"" }, { "commit": "37dd80d701fc5f55ed5a88ce2a495bf6eeb4a321", "tree": "2129c5f6fb822e0ca5c5671494c35aaadd78ef9c", "parents": [ "6e5e3b2e914cf4bdc5f17a6011fc2b1937eb9641" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 01 17:41:45 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 02 11:21:49 2016 +0100" }, "message": "ARM: Embed 0.0 in VCMP.\n\nTest: Run ART test suite on Nexus 5.\nChange-Id: I5cbbd98c4d64a4d9213e27adcae929ead5099a39\n" }, { "commit": "ba65cc4a71273904294245cb37ce70e5bce797e3", "tree": "d53a7a816ec4c8e5bdbf80729ac945787b27bf2c", "parents": [ "1a827a05afbffd5bee241f245f9aa3c40b4dbae4", "542451cc546779f5c67840e105c51205a1b0a8fd" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Aug 02 03:47:35 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 02 03:47:35 2016 +0000" }, "message": "Merge \"ART: Convert pointer size to enum\"" }, { "commit": "542451cc546779f5c67840e105c51205a1b0a8fd", "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a", "parents": [ "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 26 09:02:02 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 18:54:48 2016 -0700" }, "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n" }, { "commit": "4c4d6f42cff3d9a43db3e44716726c2cd39c23bb", "tree": "3323fc2751203f078ae9ecab9287c6d10b0e3664", "parents": [ "533d684038a72fc5bd3ed352384fc2200bc79c76", "f1aedb126ad1cb56dc7a38c8e07113295b123f58" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 29 14:28:44 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 29 14:28:44 2016 +0000" }, "message": "Merge \"Pass the right class loader when inlining.\"" }, { "commit": "d22b69a12777014a92a3551eba65a4c69f2800b2", "tree": "9610ef0db5bdd3b21bfcfa4de2f1f3328b928f5b", "parents": [ "e3051bf60783fa18e6f8c7ac6f73091f05af5665", "d549c28cfbddba945cb88857bcca3dce1414fb29" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 28 16:20:19 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 28 16:20:19 2016 +0000" }, "message": "Merge \"Remove two ReadBarrierMarkRegX entrypoints.\"" }, { "commit": "f1aedb126ad1cb56dc7a38c8e07113295b123f58", "tree": "1ed73536af4ce231ffeb884bb9a464bb9b57ea00", "parents": [ "e3051bf60783fa18e6f8c7ac6f73091f05af5665" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 28 03:49:14 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 28 17:16:39 2016 +0100" }, "message": "Pass the right class loader when inlining.\n\nOtherwise, method and type resolution can resolve to the wrong\nthings and as a side effect update the dex cache with wrong data.\n\nbug:30403437\ntest:./art/test/run-test --host --jit --dev --no-prebuild 613\n\n(cherry picked from commit 0a210d9b108c87c0e7c1d430a92ce6fc89790c95)\n\nChange-Id: I8fdca96fccae079c8e99b8e86e7b6935acfce89d\n" }, { "commit": "f9136b631a42531353544791fb79cc9e4c0b321b", "tree": "c60d6ae2746d218b3c22e1cfc61fbf5e978dfd7c", "parents": [ "f59f59769046932e121864386676205a9ca631e1", "06a46c44bf1a5cba6c78c3faffc4e7ec1442b210" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 28 12:43:29 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 28 12:43:29 2016 +0000" }, "message": "Merge \"MIPS32: Improve string and class loads\"" }, { "commit": "75d2df275abedf90be8c8e31202389788c3b079b", "tree": "01d63985ad762f8fe22ffc82e8532d920bb3af36", "parents": [ "6369394e75b84ff3aefbd6523bb1f955bcc2323f" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 21:25:41 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 21:26:18 2016 -0700" }, "message": "ART: Use old operator\u003c\u003c for MemBarrierKind\n\nTo fix assumptions in the tests.\n\nTest: m test-art-host\nChange-Id: Ie2e738524ee8f75a3c41730f6a1449dab490e535\n" }, { "commit": "06a46c44bf1a5cba6c78c3faffc4e7ec1442b210", "tree": "fa82ec7a787200e475e567a51c2839349a513021", "parents": [ "9755c262df1be7f5d5b98d038c8fd3734e974f9d" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jul 19 15:00:40 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Jul 27 20:02:48 2016 -0700" }, "message": "MIPS32: Improve string and class loads\n\nTested:\n- MIPS32 Android boots in QEMU\n- test-art-host-gtest\n- test-art-target-run-test-optimizing in QEMU, on CI20\n- test-art-target-gtest on CI20\n\nChange-Id: I70fd5d5267f8594c3b29d5a4ccf66b8ca8b09df3\n" }, { "commit": "6369394e75b84ff3aefbd6523bb1f955bcc2323f", "tree": "005e7085340c02b4efd77dc0536f6d9616ecf778", "parents": [ "74d19f13d22653edfd966a89464fc02a95ea8522", "26de38bb7f2122417388809f4ff88a7cb5c4af5e" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 28 01:54:06 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 28 01:54:06 2016 +0000" }, "message": "Merge \"ART: Delete old compiler_enums.h\"" }, { "commit": "26de38bb7f2122417388809f4ff88a7cb5c4af5e", "tree": "878f432e2476f90201dd4695cfc8c3498c2c207f", "parents": [ "9755c262df1be7f5d5b98d038c8fd3734e974f9d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 17:53:11 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 27 17:56:08 2016 -0700" }, "message": "ART: Delete old compiler_enums.h\n\nHoldover from the Quick days. Move the two enums that are still\nused closer to the actual users (and prune no longer used cases).\n\nTest: m test-art-host\nChange-Id: I88aa49961a54635788cafac570ddc3125aa38262\n" }, { "commit": "cdd822f4dc8414ac78374d06fa1a0c6be2507bc4", "tree": "60ec68f992a1a7c3382f0d4e611faa76cada5665", "parents": [ "e92730cbc5e05b8057cf103af876927c9c361b73" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jul 22 09:46:43 2016 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Jul 26 12:58:40 2016 +0200" }, "message": "MIPS32: Block callee save fp registers in debuggable\n\nThis fixes tests 454-get-vreg and 457-regs in debuggable.\nAdditional changes in LocationsBuilderMIPS::HandleFieldGet/Set\nto prevent situations when running out of available fp registers.\n\nTest: mma -j2 ART_TEST_RUN_TEST_DEBUGGABLE\u003dtrue test-art-target-run-test\nChange-Id: Iaad6a6e414ff747b39209780c21aeddc225a04c1\n" }, { "commit": "a69e790ad9751807d4a660bb4432b7ea79f0ad3b", "tree": "ce885e1cc3379d7f32c286b987d7d741ab571663", "parents": [ "edbecee66ff9c550cb82d4a5310b81c9def1e80e", "f5fb09035da52a07e9df81cdcb4b025edb0db113" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Jul 25 17:53:51 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 25 17:53:51 2016 +0000" }, "message": "Merge \"Make static helper methods member functions of OptimizingCompiler class\"" }, { "commit": "de4cf16f467b531373560ca6eb785f0f36606aae", "tree": "ae663c4bc03e6805189bd0dc849de1cb2d1f74e0", "parents": [ "c4aa8961819c78a0fb2ed342ed374d4aaeb4255c", "dec8f63fdf50815f24efe1c03af64208da15f339" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 25 14:49:51 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 25 14:49:51 2016 +0000" }, "message": "Merge \"Do not emit stack maps for runtime calls to ReadBarrierMarkRegX.\"" }, { "commit": "806f0122e923581f559043e82cf958bab5defc87", "tree": "c297dd93b213ce174558f7b63ead3f174ff1a90c", "parents": [ "c4aa8961819c78a0fb2ed342ed374d4aaeb4255c" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Mar 09 11:10:16 2016 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Mon Jul 25 14:10:37 2016 +0100" }, "message": "Add support for CallKind::kCallOnMainAndSlowPath\n\nSome of the intrinsics call on both the main and slowpath. This patch\nadds support for such a CallKind and marks the intrinsics accordingly.\n\nThis will be exercised by a later patch that refactors all the runtime\ncalls to use InvokeRuntime().\n\nPlease note that without this patch, the calls to ValidateInvokeRuntime()\nexercised by the following patches would fail.\n\nChange-Id: I450571b8b47280a004b714996189ba6db13fb57d\n" }, { "commit": "d549c28cfbddba945cb88857bcca3dce1414fb29", "tree": "584d765beea2cd6ceb4d56789ccc5c8f64db967e", "parents": [ "9e27d02040ff87eb8e2d56d21347a77cb800eddf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 25 12:49:15 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 25 12:49:15 2016 +0100" }, "message": "Remove two ReadBarrierMarkRegX entrypoints.\n\nAs entry points ReadBarrierMarkReg30 and\nReadBarrierMarkReg31 are undefined on all architectures\nsupporting the read barrier configuration (ARM, ARM64, x86\nand x86-64), remove them from the entry point list.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I500626e54f00aebfc095b4ef5f81b49fa43f7768\n" }, { "commit": "f5fb09035da52a07e9df81cdcb4b025edb0db113", "tree": "469a91dd42323b63b72895d844de0e11455939c0", "parents": [ "633c22de95fe6f80c0dd3176e15de4de3ee4bc79" ], "author": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Fri Jul 22 13:33:11 2016 -0700" }, "committer": { "name": "Wojciech Staszkiewicz", "email": "staszkiewicz@google.com", "time": "Fri Jul 22 15:42:56 2016 -0700" }, "message": "Make static helper methods member functions of OptimizingCompiler class\n\nMake RunOptimizations, MaybeRunInliner and RunArchOptimizations member\nfunctions of OptimizingCompiler class.\n\nBoth versions of RunOptimizations are protected in preparation for\nbisection bug search CL.\n\nChange-Id: I596efa9ed3fccd1ed3798c6427cc166e2a5d28bd\n" }, { "commit": "dec8f63fdf50815f24efe1c03af64208da15f339", "tree": "36c8dec8c2c93312d17c6d9d1452d4b133212dbd", "parents": [ "41c7e2e6ac0a59da2f3e066e20630b295fbe4661" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 22 17:10:06 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 22 18:54:35 2016 +0100" }, "message": "Do not emit stack maps for runtime calls to ReadBarrierMarkRegX.\n\n* Boot image code size variation on Nexus 5X\n (aosp_bullhead-userdebug build):\n - total ARM64 framework Oat files size change:\n 115584120 bytes -\u003e 109124728 bytes (-5.59%)\n - total ARM framework Oat files size change:\n 97387728 bytes -\u003e 92517584 (-5.00%)\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I979d9fb2b4e09f4c0c7bf33af2cd91750a67f989\n" }, { "commit": "67def597e84d2bb42a5f66433bd29ce94068b6b0", "tree": "fae6bfe90f3fe2042ea28afa6a992f5f0afcc068", "parents": [ "41c7e2e6ac0a59da2f3e066e20630b295fbe4661" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jul 14 17:19:43 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jul 22 10:52:53 2016 -0700" }, "message": "Combine offsets in loop-based dynamic BCE.\n\nRationale:\nSimilar to what I did recently for dom-based dynamic BCE, this\nCL combines offsets for the tests generated for loop-based\ndynamic BCE. For a set of n references, this reduces the\nnumber of generated tests from 2*n+1 down to at most 4\n(in some cases even less).\n\nTEST: 530-checker-loops3\n\nBUG\u003d27430379\n\nChange-Id: Ic80c2563eaae23f514c1fd52965dd83bccb9d190\n" }, { "commit": "057361ca33625ed14b33ffd8e641e27916fb2fea", "tree": "cf13a0b5c0e5504fdcf320ab9a9936d0d489bdf5", "parents": [ "65ad9b3516c4f4bc4e7abf5c6e065a675cf024d8", "4359e61927866c254bc2d701e3ea4c48de10b79c" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 12:11:15 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 12:11:15 2016 +0000" }, "message": "Merge \"Move caller-saves saving/restoring to ReadBarrierMarkRegX.\"" }, { "commit": "4359e61927866c254bc2d701e3ea4c48de10b79c", "tree": "05d274ecd6b5ff6eb890f64cd3bb670c7170bf15", "parents": [ "2be946bbf995496fe56364d9b7c4957fcb6aeec5" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 20 11:32:19 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 11:21:20 2016 +0100" }, "message": "Move caller-saves saving/restoring to ReadBarrierMarkRegX.\n\nInstead of saving/restoring live caller-save registers\nbefore/after the call to read barrier mark entry points\nReadBarrierMarkRegX, have these entry points save/restore\nall the caller-save registers themselves (except register\nrX, which contains the return value).\n\nAlso refactor the assembly code of these entry points\nusing macros.\n\n* Boot image code size variation on Nexus 5X\n (aosp_bullhead-userdebug build):\n - total ARM64 framework Oat files size change:\n 119196792 bytes -\u003e 115575920 bytes (-3.04%)\n - total ARM framework Oat files size change:\n 100435212 bytes -\u003e 97621188 bytes (-2.80%)\n\n* Benchmarks (ARM64) score variations on Nexus 5X\n (aosp_bullhead-userdebug build):\n - RitzPerf (lower is better)\n - average score difference: -2.71%\n - CaffeineMark (higher is better)\n - no real difference for most tests\n (absolute variation lower than 1%)\n - better score on the \"Method\" benchmark:\n score variation 41253 -\u003e 44891 (+8.82%)\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I881bf73139a3f1c2bee9ffc6fc8c00f9a392afa6\n" }, { "commit": "a92938a17b75eed3213030faaff9cfb321d47f37", "tree": "c6db649f7c1f6b6a86eb568212a721aac4ee6d96", "parents": [ "89b03e0cfb03e3194e39f07fa8c1bd46e3b28a34", "328429ff48d06e2cad4ebdd3568ab06de916a10a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 21 09:17:15 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 09:17:16 2016 +0000" }, "message": "Merge \"ARM: Port instr simplification of array accesses.\"" } ], "next": "328429ff48d06e2cad4ebdd3568ab06de916a10a" }