)]}' { "log": [ { "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd", "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 13 09:20:58 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 15 11:21:37 2015 -0500" }, "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine. This fails for X86,\nwhere a double in an XMM register takes up 8 bytes. Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce", "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518", "parents": [ "893e8881e31180721512c1b9e5ffacb03aad2e45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 07 16:01:24 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 13:57:51 2015 +0000" }, "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n" }, { "commit": "02d81cc8d162a31f0664249535456775e397b608", "tree": "8bce70d3d44dcc9384d72e4edc1505e4d1a6ea07", "parents": [ "8558375377946aabbbda6ab584e13f754590bd89" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Mon Jan 05 16:08:49 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 05 18:23:33 2015 +0000" }, "message": "Opt Compiler: ARM64: Add support for rem-float, rem-double and volatile.\n\nAdd support for rem-float, rem-double and volatile memory accesses\nusing acquire-release and memory barriers.\n\nChange-Id: I96a24dff66002c3b772c3d8e6ed792e3cb59048a\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8", "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519", "parents": [ "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n" }, { "commit": "6004796d6c630696127df2494dcd4f30d1367a34", "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97", "parents": [ "407d77f344cfbdbbfb50531c5f0766bc0892e2fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 00:01:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 14:59:50 2014 +0000" }, "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n" }, { "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c", "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955", "parents": [ "776b880f66edb21cb3b4225877e494ec7a9ec1a2" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 10:36:50 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 14:36:14 2014 +0000" }, "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7" }, { "commit": "02164b352a1474c616771582ca9a73a2cc514c1f", "tree": "6c124ec6e19f18343b69df8cddcb74e17447f294", "parents": [ "32f5b4d2c8c9b52e9522941c159577b21752d0fa" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Nov 13 14:05:07 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 13:10:25 2014 +0000" }, "message": "Opt Compiler: Arm64: Add support for more IRs plus various fixes.\n\nAdd support for more IRs and update others.\n\nChange-Id: Iae1bef01dc3c0d238a46fbd2800e71c38288b1d2\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa", "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Nov 25 20:05:46 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 12:02:58 2014 +0000" }, "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6", "tree": "3db61320369973e463f67927a8983d7eb0d9f860", "parents": [ "255a5bde2f0014dc86a564555106a4291c0867b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n" }, { "commit": "67555f7e9a05a9d436e034f67ae683bbf02d072d", "tree": "9a01b7c69032b08b3c55c18076f68c1e397d8a35", "parents": [ "bf75c5cf32a47eecadcc5e4a324237c1f1d09cde" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Nov 18 10:55:16 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 18 15:36:36 2014 +0000" }, "message": "Opt compiler: Add support for more IRs on arm64.\n\nChange-Id: I4b6425135d1af74912a206411288081d2516f8bf\n" }, { "commit": "f0e3937b87453234d0d7970b8712082062709b8d", "tree": "e552c1173ee90fea1d2ba11cc08878efe65ba0be", "parents": [ "59321e0e10ea09694efecf6154704e2743b9bffd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:50:07 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:55:24 2014 +0000" }, "message": "Do a parallel move in BoundsCheckSlowPath.\n\nThe two locations of the index and length could overlap,\nso we need a parallel move. Also factorize the code for\ndoing a parallel move based on two locations.\n\nChange-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4\n" }, { "commit": "fc19de8b201475231751b9df08fce01a093e5c2b", "tree": "7c0e9c923a37d059f1707156d69f4908aca308ac", "parents": [ "a89086e3be94fb262c4c4feb15241b30616c3b8f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 17:13:31 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Nov 10 17:31:38 2014 +0000" }, "message": "Opt compiler: Add arm64 support for a few more IRs.\n\nChange-Id: I781ddcbc61eb2b04ae80b1c7697e1ed5694bd5b9" }, { "commit": "a89086e3be94fb262c4c4feb15241b30616c3b8f", "tree": "82878d8a6c5418c43ff45857b81db7c88af7d455", "parents": [ "974bc2747b345667e07692109d63675ec50955a3" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 17:13:25 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Nov 10 17:31:17 2014 +0000" }, "message": "Opt compiler: Add arm64 support for floating-point.\n\nChange-Id: I0d97ab0f5ab770fee62c819505743febbce8835e" }, { "commit": "de58ab2c03ff8112b07ab827c8fa38f670dfc656", "tree": "c872bfbcad1e90845008140bbddcc43e56dc19d2", "parents": [ "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 05 12:46:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 06 16:49:52 2014 +0000" }, "message": "Implement try/catch/throw in optimizing.\n\n- We currently don\u0027t run optimizations in the presence of a try/catch.\n- We therefore implement Quick\u0027s mapping table.\n- Also fix a missing null check on array-length.\n\nChange-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f\n" }, { "commit": "6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f", "tree": "9df58b57af13240a93a6da4eefcf03f70cce9ad9", "parents": [ "c6e0955737e15f7c0c3575d4e13789b3411f4993" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 31 00:33:20 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Nov 03 20:01:04 2014 -0800" }, "message": "Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.\n\nFix associated errors about unused paramenters and implict sign conversions.\nFor sign conversion this was largely in the area of enums, so add ostream\noperators for the effected enums and fix tools/generate-operator-out.py.\nTidy arena allocation code and arena allocated data types, rather than fixing\nnew and delete operators.\nRemove dead code.\n\nChange-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b\n" }, { "commit": "5319defdf502fc4569316473846b83180ec08035", "tree": "909c6b29f065c79c8368a283946947cbb582d1c7", "parents": [ "37a7188810e865a1ee0a7bdc2d01d62c1f1ea49e" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Oct 23 10:03:10 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 23 13:44:42 2014 +0100" }, "message": "ART: optimizing compiler: initial support for ARM64.\n\nThe ARM64 port uses VIXL for code generation, to which it defers work\nlike label binding and branch resolving, register type coherency\nchecking, and immediate values handling.\n\nChange-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\nSigned-off-by: Alexandre Rames \u003calexandre.rames@arm.com\u003e\n" } ] }