)]}'
{
  "log": [
    {
      "commit": "71fb52fee246b7d511f520febbd73dc7a9bbca79",
      "tree": "444d91e910433aaf887bbdada28dfaa3160bebc2",
      "parents": [
        "420457e6040184a6e1639a4c84fcc8e237bd8a3d"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Dec 29 17:43:08 2014 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Jan 15 10:21:11 2015 -0800"
      },
      "message": "ART: Optimizing compiler intrinsics\n\nAdd intrinsics infrastructure to the optimizing compiler.\n\nAdd almost all intrinsics supported by Quick to the x86-64 backend.\nFurther intrinsics require more assembler support.\n\nChange-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807\n"
    },
    {
      "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd",
      "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4",
      "parents": [
        "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 13 09:20:58 2015 -0500"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Jan 15 11:21:37 2015 -0500"
      },
      "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine.  This fails for X86,\nwhere a double in an XMM register takes up 8 bytes.  Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce",
      "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518",
      "parents": [
        "893e8881e31180721512c1b9e5ffacb03aad2e45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 07 16:01:24 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 08 13:57:51 2015 +0000"
      },
      "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n  (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n  registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n"
    },
    {
      "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c",
      "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955",
      "parents": [
        "776b880f66edb21cb3b4225877e494ec7a9ec1a2"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 10:36:50 2014 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 14:36:14 2014 +0000"
      },
      "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7"
    },
    {
      "commit": "5976857e65d3d0e7be0c4e3183e9483c85a76bb8",
      "tree": "33dd2712eaf12ce49db7bfe2d0737122c21e4ed4",
      "parents": [
        "7933e185ebd4efab7f7e0749bfa193f08152c614"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Dec 01 09:50:04 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Dec 01 11:25:41 2014 +0000"
      },
      "message": "Fix insertion of parallel move when connecting siblings.\n\nAlso add a check that ensures parallel moves have been inserted\ncorrectly.\n\nThis fixes tests:\norg.apache.harmony.tests.java.util.BitSetTest#test_nextSetBitI\norg.apache.harmony.tests.java.util.BitSetTest#test_31036_set\n\nOn host/x64.\n\nChange-Id: I59d29aca393b5344bac933e2813ab409fea9d9b5"
    },
    {
      "commit": "eea79dd779ba199658ada7264f8f96d776e53f19",
      "tree": "f7317c36141deb11bf7cdcc7afd7b230491e82d5",
      "parents": [
        "9ce56af31bef386944b7e76ab46897b3573a80d1",
        "46fbaab1bf2981f2768b046abf43e368663daacd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Nov 28 11:26:24 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Nov 28 11:26:25 2014 +0000"
      },
      "message": "Merge \"Fix a bug in the linear scan register allocator.\""
    },
    {
      "commit": "9ce56af31bef386944b7e76ab46897b3573a80d1",
      "tree": "69024d8c6b23e6c60b25ee6511c67f5e5332b5a4",
      "parents": [
        "db5453bbda97e94c00af714a7ec8e59d3a4ea843",
        "acd033994aced8246c2fd8e931340dbf82d06d1a"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Nov 28 11:07:27 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Nov 28 11:07:28 2014 +0000"
      },
      "message": "Merge \"Fix bogus assumption for live registers at safe point.\""
    },
    {
      "commit": "199f336af1fc8212646fda67675df0361ece33d6",
      "tree": "e8709a668b285246ab7d7f4c3f8f2553fd5f39e2",
      "parents": [
        "924632d2626b17b903bf7b851099f6d575ac534b"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Nov 27 17:15:16 2014 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Nov 27 17:15:16 2014 +0000"
      },
      "message": "Wrap long lines in the optimizing compiler.\n\nChange-Id: I5dee0c65e6652de574ae952b1f1dfc7355859e45\n"
    },
    {
      "commit": "5368c219a462defc90c4b896b34eb7506ba5c142",
      "tree": "6374d21b8ac88f3a0f001a7fbda4a1769572c879",
      "parents": [
        "d7fa3a7d26105dd112acf955a0c7a880a6027180"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Nov 27 15:03:41 2014 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Nov 27 15:03:41 2014 +0000"
      },
      "message": "Fix neg-float \u0026 neg-double for null values in opt. compiler.\n\n- Implement float and double negation as an exclusive or\n  with a bit sign mask in x86 and x86-64 code generators.\n- Enable requests of temporary FPU (double) registers during\n  register allocation.\n- Update test cases in test/415-optimizing-arith-neg.\n\nChange-Id: I9572c24b27c645ba698825e60cd5b3956b4895fa\n"
    },
    {
      "commit": "46fbaab1bf2981f2768b046abf43e368663daacd",
      "tree": "36b8ea48ce8f2a1dafb121b4cf18176f174b8835",
      "parents": [
        "f2611341d2e45144edd25c90f66834687a043dcc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 26 18:30:23 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 26 19:07:14 2014 +0000"
      },
      "message": "Fix a bug in the linear scan register allocator.\n\nTriggered by:\norg.apache.harmony.tests.java.util.jar.JarFileTest#testGetJarEntry.\n\nBy miscompling:\nokhttp.CacheControl#parse.\n\nA move occuring just before the first instruction of a block\nshould not be handled by ConnectSplitSiblings, but by ConnectSiblings\ninstead.\n\nChange-Id: I8ad409734809e6787bb7321563e1331e7a6906c0\n"
    },
    {
      "commit": "acd033994aced8246c2fd8e931340dbf82d06d1a",
      "tree": "750cca769708c80b2f38f550b3df86188ec78752",
      "parents": [
        "220526b05d4365a1820a694c98527eda2d3dc980"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 26 15:46:52 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 26 15:46:52 2014 +0000"
      },
      "message": "Fix bogus assumption for live registers at safe point.\n\nWe did not take into account inactive intervals going\ninto active when computing live registers at a slow path\nsafe point. So we must ensure the safepoint interval is always\nhandled after all intervals starting at the same position have\nbeen handled.\n\nChange-Id: I05ea2161016a90b0ee3ba0b18cd54a8e46860f1e\n"
    },
    {
      "commit": "87d03761f35ad6cbe0bffbf1ec739875a471da6d",
      "tree": "139fd83737c4f88747214a662e205cd064f1709d",
      "parents": [
        "d79ac38df2a5e56b8929501803183f70053494bf"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 15:17:56 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 18:11:05 2014 +0000"
      },
      "message": "Fix safepoint bug when computing live registers.\n\nChange-Id: I8f28dd287c0e04223c49dea6a323058c1b210913\n"
    },
    {
      "commit": "9806199033fc2fb61bfd2260f0156d1b38d56beb",
      "tree": "14a5cd067fb01ace19fb5e0f7d494bd9e8744845",
      "parents": [
        "255507d9c695aa9c774b882308faa8278382006b",
        "52839d17c06175e19ca4a093fb878450d1c4310d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Nov 10 10:36:59 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Nov 10 10:37:00 2014 +0000"
      },
      "message": "Merge \"Support invoke-interface in optimizing.\""
    },
    {
      "commit": "52839d17c06175e19ca4a093fb878450d1c4310d",
      "tree": "552ea632ad4d1f688bdfd04b66102e25312bd237",
      "parents": [
        "a453307957afdc3ef0a7988025539ab8919464bc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Nov 07 17:47:25 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Nov 10 10:33:37 2014 +0000"
      },
      "message": "Support invoke-interface in optimizing.\n\nChange-Id: Ic18d7c3d2810557231caf0571956e0c431f5d384\n"
    },
    {
      "commit": "f43083d560565aea46c602adb86423daeefe589d",
      "tree": "6c812e88723c40ee77ab5c9ba38625a10cc9b364",
      "parents": [
        "de87f405a5f8a4ffd57f01d0d667188e8f0ca8cd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Nov 07 10:48:10 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Nov 07 14:43:19 2014 +0000"
      },
      "message": "Do not update Out after it has a valid location.\n\nSlow paths use LocationSummary to know where to move\nthings around, and they are executed at the end of the\ncode generation.\n\nThis fix is needed for https://android-review.googlesource.com/#/c/113345/.\n\nChange-Id: Id336c6409479b1de6dc839b736a7234d08a7774a\n"
    },
    {
      "commit": "d0d4852847432368b090c184d6639e573538dccf",
      "tree": "47e31fe860ff1c3ace2f3f5945aa69689d42d998",
      "parents": [
        "a88b7b93e28ea86969dd3ec6a6bf6929d697fc31"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Tue Nov 04 16:40:20 2014 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Thu Nov 06 14:42:58 2014 +0000"
      },
      "message": "[optimizing compiler] Add div-int and exception handling.\n\n- for backends: arm, x86, x86_64\n- fixed a register allocator bug: the request for a fixed register for\nthe first input was ignored if the output was kSameAsFirstInput\n- added divide by zero exception\n- more tests\n- shuffle around some code in the builder to reduce the number of lines\nof code for a single function.\n\nChange-Id: Id3a515e02bfbc66cd9d16cb9746f7551bdab3d42\n"
    },
    {
      "commit": "277ccbd200ea43590dfc06a93ae184a765327ad0",
      "tree": "d89712e93da5fb2748989353c9ee071102cf3f33",
      "parents": [
        "ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Nov 03 21:36:10 2014 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Nov 04 18:40:08 2014 -0800"
      },
      "message": "ART: More warnings\n\nEnable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,\nand -Wunused-but-set-parameter for GCC builds.\n\nChange-Id: I81bbdd762213444673c65d85edae594a523836e5\n"
    },
    {
      "commit": "c6e0955737e15f7c0c3575d4e13789b3411f4993",
      "tree": "84a0b42a5d722e4e485834a218bd32d607a4eedc",
      "parents": [
        "9aee6fc7f23ca4c23d11b8b269da02a383d8debb",
        "296bd60423e0630d8152b99fb7afb20fbff5a18a"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Tue Nov 04 00:21:46 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Nov 04 00:21:46 2014 +0000"
      },
      "message": "Merge \"Some improvement to reg alloc.\""
    },
    {
      "commit": "296bd60423e0630d8152b99fb7afb20fbff5a18a",
      "tree": "384aa7659763bb77a038a67c27f7cf6059632570",
      "parents": [
        "57b4d1c44e246dfd4aaef2d23b20a696a0c5e57e"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Oct 06 16:47:28 2014 -0700"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Nov 03 16:16:50 2014 -0800"
      },
      "message": "Some improvement to reg alloc.\n\nChange-Id: If579a37791278500a7e5bc763f144c241f261920\n"
    },
    {
      "commit": "2810f92d099ac7442f661abbfa73734835a58e25",
      "tree": "197012940ef5af52c9c802396f1c2d3b5a5742bd",
      "parents": [
        "a9014f977ae90373f5bad4cf812c2bda810b10f8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Oct 31 14:27:37 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Oct 31 14:56:00 2014 +0000"
      },
      "message": "Disable kNoOutputOverlap optimization.\n\nFound a case where it does not work. Need to think more about it\nas well as write a regression test.\n\nChange-Id: I2abe05c84f2c608d622fbe6d373b6dcdb68f4162\n"
    },
    {
      "commit": "b5f62b3dc5ac2731ba8ad53cdf3d9bdb14fbf86b",
      "tree": "fb2d33e43de1476af33112f263fd3c3a775917d0",
      "parents": [
        "29ce77f654412dbb5fb3d5949da4053952917101"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 30 10:58:41 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Oct 31 12:21:53 2014 +0000"
      },
      "message": "Support for CONST_STRING in optimizing compiler.\n\nChange-Id: Iab8517bdadd1d15ffbe570010f093660be7c51aa\n"
    },
    {
      "commit": "c7dd295a4e0cc1d15c0c96088e55a85389bade74",
      "tree": "0c08a2236bc9ba5d9a4dc75d4dd0ed2d76f8f1c6",
      "parents": [
        "94e5af8602150efa95bde35cc9be9891ddf30135"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Oct 21 23:31:19 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Oct 22 12:06:23 2014 -0700"
      },
      "message": "Tidy up logging.\n\nMove gVerboseMethods to CompilerOptions. Now \"--verbose-methods\u003d\" option to\ndex2oat rather than runtime argument \"-verbose-methods:\".\nMove ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc\nexcept for a forward declaration.\nRemove ConstDumpable as Dump methods are all const (and make this so if not\ncurrently true).\nMake LogSeverity an enum and improve compile time assertions and type checking.\nRemove log_severity.h that\u0027s only used in logging.h.\nWith system headers gone from logging.h, go add to .cc files missing system\nheader includes.\nAlso, make operator new in ValueObject private for compile time instantiation\nchecking.\n\nChange-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641\n"
    },
    {
      "commit": "c8147a76ed2f440f38329dc08ff889d393b5c535",
      "tree": "bc5b83636edd6c7c6fb170dd8bddc776deefe43f",
      "parents": [
        "8d2c23e0a2d1b449448675e0ba822953cee52b18"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 16:06:20 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 16:51:50 2014 +0100"
      },
      "message": "Fix off by one errors in linear scan register allocator.\n\nChange-Id: I65eea3cc125e12106a7160d30cb91c5d173bd405\n"
    },
    {
      "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f",
      "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a",
      "parents": [
        "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 15 18:31:05 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 16:03:51 2014 +0100"
      },
      "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n"
    },
    {
      "commit": "8e3964b766652a0478e8e0e303e8556c997675f1",
      "tree": "ebae22017d3d3c872642cbc56610f67ff32a861d",
      "parents": [
        "5830247c351a1c40f37666584d6c390f32c31957"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Oct 17 11:06:38 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 11:47:54 2014 +0100"
      },
      "message": "Remove the notion of dies at entry.\n\n- Instead, explicitly say that the output does not overlap.\n- Inputs that must be in a fixed register do die at entry,\n  as we know they have a location that others can not take.\n- There is also no need to differentiate between an input move\n  and a connecting sibling move - those can be put in the\n  same parallel move instruction.\n\nChange-Id: I1b2b2827906601f822b59fb9d6a21d48e43bae27\n"
    },
    {
      "commit": "f8e28f575b1382e984edb2e8c9846a27a1bdea10",
      "tree": "12506af9dc858d842061843570a939e74822b517",
      "parents": [
        "f659bec20db45c809a891ff528fb6aecf2c76149",
        "476df557fed5f0b3f32f8d11a654674bb403a8f8"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Oct 13 11:36:10 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Oct 13 11:36:11 2014 +0000"
      },
      "message": "Merge \"Use Is*() helpers to shorten code in the optimizing compiler.\""
    },
    {
      "commit": "71175b7f19a4f6cf9cc264feafd820dbafa371fb",
      "tree": "5370e7c7c9f7d1edf148a00548cb1334d5118f8d",
      "parents": [
        "b76c5495c4879fcfa0866b1490031a3123baf9ee"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 22:13:55 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Oct 10 11:36:03 2014 +0000"
      },
      "message": "Cleanup baseline register allocator.\n\n- Use three arrays for blocking regsters instead of\n  one and computing offsets in that array.]\n- Don\u0027t pass blocked_registers_ to methods, just use the field.\n\nChange-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6\n"
    },
    {
      "commit": "476df557fed5f0b3f32f8d11a654674bb403a8f8",
      "tree": "0ca72785e60b3b1152bca0908e6d134c0a30f631",
      "parents": [
        "9e878d50567f624094f3c4940ac3aedbc5eff3b9"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Oct 09 17:51:36 2014 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Oct 09 17:59:50 2014 +0100"
      },
      "message": "Use Is*() helpers to shorten code in the optimizing compiler.\n\nChange-Id: I79f31833bc9a0aa2918381aa3fb0b05d45f75689\n"
    },
    {
      "commit": "360231a056e796c36ffe62348507e904dc9efb9b",
      "tree": "a62ff73c11eaa6694649c98e4c2d872e89149b0c",
      "parents": [
        "2072c465cfff077da257bdf14f1f1b2690c946c8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 08 21:07:48 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 15:21:57 2014 +0100"
      },
      "message": "Fix code generation of materialized conditions.\n\nMove the logic for knowing if a condition needs to be materialized\nin an optimization pass (so that the information does not change\nas a side effect of another optimization).\n\nAlso clean-up arm and x86_64 codegen:\n- arm: ldr and str are for power-users when a constant is\n  in play. We should use LoadFromOffset and StoreToOffset.\n- x86_64: fix misuses of movq instead of movl.\n\nChange-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3\n"
    },
    {
      "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f",
      "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a",
      "parents": [
        "a3c4d72210de174552f47b2d117b1946f274af1e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 11:47:51 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 14:42:13 2014 +0100"
      },
      "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n"
    },
    {
      "commit": "01ef345767ea609417fc511e42007705c9667546",
      "tree": "8a3cf1b5a576caf212ef31db966b97b6d23aaf98",
      "parents": [
        "a9f2904263581f606a5704f2bb74efcecf7e9f97"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 01 11:32:17 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 07 21:25:27 2014 +0100"
      },
      "message": "Add trivial register hints to the register allocator.\n\n- Add hints for phis, same as first input, and expected registers.\n- Make the if instruction accept non-condition instructions.\n\nChange-Id: I34fa68393f0d0c19c68128f017b7a05be556fbe5\n"
    },
    {
      "commit": "26a25ef62a13f409f941aa39825a51b4d6f0f047",
      "tree": "aa0ed991cfcea17297e85f74624a44e32e8913cf",
      "parents": [
        "17b1c174dddb1d83018740c2084ab42daa812fff"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 30 13:54:09 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Oct 06 18:52:56 2014 +0100"
      },
      "message": "Add a prepare for register allocation pass.\n\n- Currently the pass just changes the uses of checks to the\n  actual values.\n- Also optimize array access, now that inputs can be constants.\n- And fix another bug in the register allocator reveiled by\n  this change.\n\nChange-Id: I43be0dbde9330ee5c8f9d678de11361292d8bd98\n"
    },
    {
      "commit": "8ddb00ca935733f5d3b07816e5bb33d6cabe6ec4",
      "tree": "9bca67b136523eb31aab736988143295ece97b56",
      "parents": [
        "cc6b59ee25d7b9782cc971687715d664a97b05bd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 29 12:00:40 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 30 13:50:38 2014 +0100"
      },
      "message": "Improve detection of lifetime holes.\n\nThe check concluding that the next use was in a successor\nwas too conservative: two blocks following each other\nin terms of liveness are not necessarily predecessor/sucessor.\n\nChange-Id: Ideec98046c812aa5fb63781141b5fde24c706d6d\n"
    },
    {
      "commit": "740475d5f45b8caa2c3c6fc51e657ecf4f3547e5",
      "tree": "81196b753045fa16c13a4c1106031c1f28d9d233",
      "parents": [
        "13c4e8f4ef687f650aa76fb15ab12762d5a85602"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 29 10:33:25 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 29 11:04:07 2014 +0100"
      },
      "message": "Fix a bug in the insertion of parallel move.\n\nTo make sure we do not connect interval siblings in the\nsame parallel move, I added a new field in MoveOperands\nthat tells for which instruction this move is for.\nA parallel move should not contains moves for the same instructions.\n\nThe checks revealed a bug when connecting siblings, where\nwe would choose the wrong parallel move.\n\nChange-Id: I70f27ec120886745c187071453c78da4c47c1dd2\n"
    },
    {
      "commit": "7690562d40878f44823d5fb03a2084cfc677ec4a",
      "tree": "3a55347eadd55b6b1231575f363ed3278559f83c",
      "parents": [
        "34bb808affbed7a1db177b9ef4ab5461c2b2106b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 25 14:39:26 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Sep 27 12:54:23 2014 +0100"
      },
      "message": "Register allocator: refine instructions liveness.\n\nAdd support for instructions that die at the beginning\nof another instruction. Before, an instruction needed\nto stay alive during the instruction, so the register\nallocator was not able not reuse the register.\n\nChange-Id: I5f11a80b0a20778227229eb797816edcc6365297\n"
    },
    {
      "commit": "3c04974a90b0e03f4b509010bff49f0b2a3da57f",
      "tree": "52649104e3e80272c3774793350f4d9f260ae732",
      "parents": [
        "c0d36abb12cdbb9469039c1dc153a586bd984015"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 24 18:10:46 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 25 12:23:40 2014 +0100"
      },
      "message": "Optimize suspend checks in optimizing compiler.\n\n- Remove the ones added during graph build (they were added\n  for the baseline code generator).\n- Emit them at loop back edges after phi moves, so that the test\n  can directly jump to the loop header.\n- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.\n\nChange-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a\n"
    },
    {
      "commit": "3f5e9bbb1e25b50dbaf75e1b5300863c112a62d0",
      "tree": "ca535bf8e23ab08996caed729febc51838f43399",
      "parents": [
        "2e1391b9abdafdbe7e0ef5ef116c49f812394056",
        "3bca0df855f0e575c6ee020ed016999fc8f14122"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 23 13:36:28 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Sep 23 13:36:29 2014 +0000"
      },
      "message": "Merge \"Support for saving and restoring live registers in a slow path.\""
    },
    {
      "commit": "3bca0df855f0e575c6ee020ed016999fc8f14122",
      "tree": "15e15c8290ad314c29ca608f51d89d4db68fd9ba",
      "parents": [
        "d41491adb23764f28a80cbb7f2bd7af6491cd892"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 19 11:01:00 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 23 13:57:30 2014 +0100"
      },
      "message": "Support for saving and restoring live registers in a slow path.\n\nAnd use it in suspend check slow paths.\n\nChange-Id: I79caf28f334c145a36180c79a6e2fceae3990c31\n"
    },
    {
      "commit": "145f0ca7c7c5f5fd9f5226f2a65e1fd9ba3a4f47",
      "tree": "775f344295e864e60694c2d43aa7f90a6249422f",
      "parents": [
        "cff942b1f7ebb82e3d5e0a1334467544eced1575"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 22 11:51:51 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 22 11:54:48 2014 +0100"
      },
      "message": "Fix a bug in the handling of moves in register allocator.\n\nChange-Id: Iaf1f34b0bece4f252290a97c3b73cc06e365985a\n"
    },
    {
      "commit": "aac0f39a3501a7f7dd04b2342c2a16961969f139",
      "tree": "ef71b73a7d95de726d36883e6c88f7c8cbcfaaf6",
      "parents": [
        "56369897d662ea63ea5ed57ae36af0ae0fa1452d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 16 14:11:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 16 14:15:22 2014 +0100"
      },
      "message": "Fix a bug in the register allocator.\n\nWe need to take the live interval that starts first to know\nuntil when a register is free, instead of using the live interval\nthat is last in the inactive list.\n\nChange-Id: I2c9f87481ff1b4fc7b9948db7559b8d3b11d84ce\n"
    },
    {
      "commit": "2a877f32fe145ad50250389df958a559e7d4ad92",
      "tree": "ca1042989b3c7f804a8101d5c2ed5752e0ebe6c1",
      "parents": [
        "6724a9531c92368491dd17937d0087f73a7c0642"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 10 10:49:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 10 10:49:34 2014 +0100"
      },
      "message": "Fix bug in register allocator.\n\nWhen an input can be a constant, there is no need to\ndo a move.\n\nFix 003-omnibus-opcodes failure.\n\nChange-Id: Ic40f99d3ae889505c1d2be8665f8521c2ebb5feb\n"
    },
    {
      "commit": "3946844c34ad965515f677084b07d663d70ad1b8",
      "tree": "0d85bfba2ff69c34a2897351d1e50a1464509305",
      "parents": [
        "e2c23739c6395a83b30ece38f8a2e9e1bf7cf3ce"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 02 15:17:15 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 08 12:15:07 2014 +0100"
      },
      "message": "Runtime support for the new stack maps for the opt compiler.\n\nNow most of the methods supported by the compiler can be optimized,\ninstead of using the baseline.\n\nChange-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa\n"
    },
    {
      "commit": "e77493c7217efdd1a0ecef521a6845a13da0305b",
      "tree": "3055cb7aaea8b9edc498b2e209d74af36c32e0fd",
      "parents": [
        "41cba7c66cbc441b00fca48dfb2501181b1f2a53"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Aug 20 15:08:45 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Aug 20 15:09:20 2014 -0700"
      },
      "message": "Make common BitVector operations inline-able.\n\nChange-Id: Ie25de4fae56c6712539f04172c42e3eff57df7ca\n"
    },
    {
      "commit": "96f89a290eb67d7bf4b1636798fa28df14309cc7",
      "tree": "ca2b484a18107f8253aa7774cde304586a31bc60",
      "parents": [
        "4436e926aa8e64ac7e4c4afb81f2a59b2477045a"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 11 10:57:49 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 21 09:54:20 2014 +0100"
      },
      "message": "Add assembly operations with constants in optimizing compiler.\n\nChange-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f\n"
    },
    {
      "commit": "412f10cfed002ab617c78f2621d68446ca4dd8bd",
      "tree": "bbd9dddd0436da566365ada5deb1840e315e1b11",
      "parents": [
        "d6ab04646d8eec6f24b200f8649f3d942d9ad17e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 19 10:00:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 02 16:00:32 2014 +0100"
      },
      "message": "Support longs in the register allocator for x86_64.\n\nChange-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867\n"
    },
    {
      "commit": "20dfc797dc631bf8d655dcf123f46f13332d3074",
      "tree": "c1d4e4f919d54f39a6d39d9d769ed5a844afb22b",
      "parents": [
        "cbb0e809c0a4e8a4e8b7f5d3768a1864cfb381bb"
      ],
      "author": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Mon Jun 16 20:44:29 2014 -0700"
      },
      "committer": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Tue Jun 24 09:05:27 2014 -0700"
      },
      "message": "Add some more instruction support to optimizing compiler.\n\nThis adds a few more DEX instructions to the optimizing compiler\u0027s\nbuilder (constants, moves, if_xx, etc).\n\nAlso:\n* Changes the codegen for IF_XX instructions to use a condition\n  rather than comparing a value against 0.\n* Fixes some instructions in the ARM disassembler.\n* Fixes PushList and PopList in the thumb2 assembler.\n* Switches the assembler for the optimizing compiler to thumb2\n  rather than ARM.\n\nChange-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f\n"
    },
    {
      "commit": "e27f31a81636ad74bd3376ee39cf215941b85c0e",
      "tree": "12dd6a1153b78b831c887f65f0bcef715e89719d",
      "parents": [
        "dfc2091d2fb8a7694f69acf8bd39ce4953e026c2"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 17:53:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 18:05:00 2014 +0100"
      },
      "message": "Enable the register allocator on ARM.\n\n- Also fixes a few bugs/wrong assumptions in code not hit by x86.\n- We need to differentiate between moves due to connecting siblings within\n  a block, and moves due to control flow resolution.\n\nChange-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38\n"
    },
    {
      "commit": "86dbb9a12119273039ce272b41c809fa548b37b6",
      "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5",
      "parents": [
        "c936622863a50bdda9b10062515dfc02a8c8b652"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 04 11:12:39 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 10:02:06 2014 +0100"
      },
      "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n   allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n   inputs/output to be at a specific location, and the allocator\n   needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n"
    },
    {
      "commit": "31d76b42ef5165351499da3f8ee0ac147428c5ed",
      "tree": "4f9cf307923c72f73e4a814662a26406f155c38c",
      "parents": [
        "7eb3fa1e03b070c55ecbc814e2e3ae4409cf7b1e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 09 15:02:22 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 10 10:48:50 2014 +0100"
      },
      "message": "Plug code generator into liveness analysis.\n\nAlso implement spill slot support.\n\nChange-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc\n"
    },
    {
      "commit": "a7062e05e6048c7f817d784a5b94e3122e25b1ec",
      "tree": "a5d6b64ae6d5352f761fc2547bda863281adbe40",
      "parents": [
        "8b5b1e5593ffa77c393e4172b71a3d5a821d2ed8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu May 22 12:50:17 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 26 11:31:38 2014 +0100"
      },
      "message": "Add a linear scan register allocator to the optimizing compiler.\n\nThis is a \"by-the-book\" implementation. It currently only deals\nwith allocating registers, with no hint optimizations.\n\nThe changes remaining to make it functional are:\n- Allocate spill slots.\n- Resolution and placements of Move instructions.\n- Connect it to the code generator.\n\nChange-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4\n"
    }
  ]
}