)]}'
{
  "log": [
    {
      "commit": "66e3919bc42ddca40302ce5ee32e3ade248dd2b6",
      "tree": "3800e8499317efc4b5bca06e483b2bcbd9da8d9d",
      "parents": [
        "6a14c622700e088173ba909799c1e1785aeb4b34",
        "e36605910cb13da1440fb9d7a8293842a9209c97"
      ],
      "author": {
        "name": "Treehugger Robot",
        "email": "treehugger-gerrit@google.com",
        "time": "Tue Jan 03 11:13:50 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Jan 03 11:13:51 2017 +0000"
      },
      "message": "Merge \"MIPS64: java.lang.String.getChars\""
    },
    {
      "commit": "19f6c696bbb7a17d8ac521b316c40f9cbef32151",
      "tree": "6ce87f3ba9f224efc0036d3ab99e4272c48eeddb",
      "parents": [
        "aea9ffece7eb32f3884a4ad0553e1df4d90fd9e4"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Nov 30 19:19:55 2016 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Dec 13 14:07:16 2016 -0800"
      },
      "message": "MIPS64: Improve method invocation.\n\nImprovements include:\n- support for all kinds of method loads and static/direct calls\n- 32-bit and 64-bit literals for the above and future work\n- shorter instruction sequences for recursive static/direct calls\nAlso:\n- include the MIPS64 dinsu instruction (missed earlier) and minor\n  clean-up in the disassembler\n- properly prefix constant names with \u0027k\u0027 in relative patcher tests\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n       ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n       ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test64\"\n\nChange-Id: I19876fa5316b68531af7dfddfce90d2068433116\n"
    },
    {
      "commit": "e36605910cb13da1440fb9d7a8293842a9209c97",
      "tree": "6bb2097042a3ee4f0e0b64c4e22575823ca82c11",
      "parents": [
        "b487af4fc80ffabe0219657a9690be1316dab8e7"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Nov 09 11:13:42 2016 -0800"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Fri Dec 02 16:22:56 2016 -0800"
      },
      "message": "MIPS64: java.lang.String.getChars\n\nTest: run-test --64 --optimizing 020-string\nTest: run-test --64 020-string\nTest: run-test --64 --no-prebuild --optimizing 020-string\nTest: run-test --64 --no-prebuild 020-string\nTest: run-test --64 --optimizing 082-inline-execute\nTest: run-test --64 082-inline-execute\nTest: run-test --64 --no-prebuild --optimizing 082-inline-execute\nTest: run-test --64 --no-prebuild 082-inline-execute\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTest: mma test-art-target-gtest -j2\nTest: booted MIPS64R6 emulator.\n\nNote: All tests run against MIPS64 QEMU.\n\nChange-Id: I48b9a87465f2516044a2e4f598cc5dce56b0d1c9\n"
    },
    {
      "commit": "b77051ea5718fe017f2fa884b9ca4c8186c95190",
      "tree": "bb51782f8350be00195becabc3cd8758f15010a0",
      "parents": [
        "d0111420a9f924fe560a97132d09ae531852fd69"
      ],
      "author": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Mon Nov 21 19:46:00 2016 +0000"
      },
      "committer": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Nov 25 14:16:31 2016 +0000"
      },
      "message": "ARM: VIXL32: Fix breaking changes from recent VIXL update.\n\nTest: m test-art-host\nTest: m test-art-target\nChange-Id: I02a608bf51b889a2bfff43272a3619582bf9cf20\n"
    },
    {
      "commit": "674b9ee50c812d684a27a28cf09098195f068f3d",
      "tree": "9b109adff71b48aa531628bf07644bccfc580fa3",
      "parents": [
        "c6c5f6ce1c9cc44f859bbbc447478e4934be0fee"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Sep 20 14:54:15 2016 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Thu Oct 20 15:03:43 2016 -0700"
      },
      "message": "MIPS32: Implement HSelect\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R2) on CI20\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: I8a8127d8d29cb5df84ed6f4fd4478f8d889e5cb7\n"
    },
    {
      "commit": "8872cadb33bb1c62d3e67cb74badb1a9309a6a69",
      "tree": "fe575825a9fc0b0bb0127820b8fa1bda0e0fa4db",
      "parents": [
        "a1d66b9050aeecd7e698c51155f0dbc0198a6822"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Sep 26 14:14:01 2016 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Tue Sep 27 09:18:14 2016 +0000"
      },
      "message": "ARM64: Update the disassembler after the VIXL update.\n\nTest: top-level `make -j40`\n      `mma -j40 test-art-target-test-optimizing dist`\n      `mma -j40 test-art-host dist`\n\nChange-Id: I173976998dc8e3e466ca8502c3fdc447f9019cee\n"
    },
    {
      "commit": "29b0cdeb5ef85fcf1ff33ecf09a10803b4b23441",
      "tree": "d8cbdbff1fb4c09c23166fef92fe0483b74ec7b8",
      "parents": [
        "31eb450500ae9d46e1cb253defd35c8d06539d4a"
      ],
      "author": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Tue Sep 06 13:01:03 2016 +0100"
      },
      "committer": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Sep 16 16:39:23 2016 +0100"
      },
      "message": "ARM: VIXL32: Implement a disassembler.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: manual comparison with the previous oatdump output\nChange-Id: I21ae26406200e455b8b036f53d585ea0b1bd11be\n"
    },
    {
      "commit": "31fcbf83b81b95ddd5d1a630935b4e6e90396454",
      "tree": "1bc3239b8951b6e13a103fa8490e84f1dcc6599f",
      "parents": [
        "935cf1b7a5e55a8d9aeab7e8955012849f0c1b68"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Sep 12 16:22:43 2016 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Sep 12 16:32:31 2016 -0700"
      },
      "message": "ART: Remove libart from disassembler\n\nThe disassembler now only requires the headers. Also remove liblog\ndependency.\n\nBug: 15436106\nTest: m test-art-host\nTest: m test-art-host-gtest-oatdump_test\nTest: m test-art-target-gtest-oatdump_test\nChange-Id: Iecff5b7f8ffd81c89ea81a4de8bfab77b5c103a7\n"
    },
    {
      "commit": "fe6064ae8b861f1290aa793ce0de219781da6a10",
      "tree": "a24da585adbafc5932e4c3aab07f0e1d9a639628",
      "parents": [
        "090a5da3a7f320b9d2aa9fa461efc11a7eb39392"
      ],
      "author": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Tue Aug 30 13:49:26 2016 -0700"
      },
      "committer": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Thu Sep 08 11:00:53 2016 -0700"
      },
      "message": "Convert more of art to Android.bp\n\nRelanding I1b10f140e17dd5e12a9d7f6a29d47cf61f5bf6ef, with fixes to\ncompile dalvikvm32 and dalvikvm64, and add them as dependencies of\ntests.  Also fixes HOST_PREFER_32_BIT by moving the override from the\ndefaults, which are not used by everything in art, to the art_cc_binary\nmodule type.\n\nTest: rm -rf out/host; m -j HOST_PREFER_32_BIT test-art-host; m -j test-art-host\nChange-Id: I64d3eef5080e128103d052497760c3521cc253c6\n"
    },
    {
      "commit": "bda1d606f2d31086874b68edd9254e3817d8049c",
      "tree": "db07417935fe72e99c3da60152e13f0620c7d8d7",
      "parents": [
        "d14d515df39cd963179088b8721768f9645243aa"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Aug 29 17:43:45 2016 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Sep 08 10:13:47 2016 -0700"
      },
      "message": "ART: Detach libart-disassembler from libart\n\nSome more intrusive changes than I would have liked, as long as\nART logging is different from libbase logging.\n\nFix up some includes.\n\nBug: 15436106\nBug: 31338270\nTest: m test-art-host\nChange-Id: I9fbe4b85b2d74e079a4981f3aec9af63b163a461\n"
    },
    {
      "commit": "04147efc0621ce09fb4548cc482d42da2ff4e088",
      "tree": "284a0e9736c69690ff33264730af8ebe6308ebed",
      "parents": [
        "af54785797b2c2358de417780adf6bdd513f29f3"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Sep 06 11:09:41 2016 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Sep 06 11:09:41 2016 +0100"
      },
      "message": "Add build rules for statically linked oatdump on host.\n\nAlso extend oatdump_test to exercise oatdump(d)s.\n\nTest: ART_BUILD_HOST_STATIC\u003dtrue m test-art-host-gtest-oatdump_test\nBug: 29530992\nChange-Id: I6eb6c96f385832733d18d0400abd9974a6d8e45c\n"
    },
    {
      "commit": "372f3a374681ef11f003460e14249adb7bc8313d",
      "tree": "b6d2bd95975a0ce1096dc2aa761f8e6b30e42b18",
      "parents": [
        "9c07ab332b8ebbcb1586c311bfcb75e19b8a35b4"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Aug 19 10:49:06 2016 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Aug 19 16:46:56 2016 -0700"
      },
      "message": "ART: Add thread offset printing hook to disassembler\n\nTo prepare separation of disassembler from libart, add a function\nhook to the disassembler options for thread offset name printing.\n\nBug: 15436106\nChange-Id: I9e9b7e565ae923952c64026f675ac527b560f51b\n"
    },
    {
      "commit": "af4e42a0d210aa3aa5d52926536b2ca5c2952934",
      "tree": "b64d683ba6ac11c0b7730df9a579aead2905dfff",
      "parents": [
        "dce74be0c49e8a540affc0b5649a9cf8756b809b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Aug 08 15:11:24 2016 +0100"
      },
      "committer": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Aug 12 13:22:34 2016 +0100"
      },
      "message": "ARM64: VIXL: Support a newer version of VIXL.\n\nPlease note that compiling VIXL with -Wshadow is a known VIXL issue.\n\nThis will be resolved in a later version of VIXL, when we can drop\nthe deprecated API for getters and setters.\n\nFor more info take a look at VIXL_DEPRECATED in the VIXL source code.\n\nChange-Id: Iea30b1a7b065f9b16a92c6cc7ebdc50ef068b348\n"
    },
    {
      "commit": "2ea915326b0ff9e07f0b3ecb68b78f7d3200d200",
      "tree": "c7ac53f09bb71eb6da19b0a71435774637765942",
      "parents": [
        "33699c9529add1c1ec4bb5dcb0807942709de224"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Thu Aug 11 17:04:14 2016 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Thu Aug 11 17:04:14 2016 +0100"
      },
      "message": "ARM64: Use libvixld when compiling for debug mode.\n\nVIXL debug mode checks are valuable to catch dangerous code that can\nlead to bugs.\n\nThis patch includes a couple of fixes for issues spotted by VIXL in debug mode.\n\nChange-Id: I388ae1ffd9256ad74d0b6ce06f79cc7927a5f28a\n"
    },
    {
      "commit": "3719016185859778fa562d02140d04004c21d9a7",
      "tree": "30a2401e0576370bff32375fc87856739559379e",
      "parents": [
        "3d6094531e3790b25c43e59fd6cd0b6b99d3447c",
        "37dd80d701fc5f55ed5a88ce2a495bf6eeb4a321"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Aug 02 12:31:10 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Aug 02 12:31:10 2016 +0000"
      },
      "message": "Merge \"ARM: Embed 0.0 in VCMP.\""
    },
    {
      "commit": "37dd80d701fc5f55ed5a88ce2a495bf6eeb4a321",
      "tree": "2129c5f6fb822e0ca5c5671494c35aaadd78ef9c",
      "parents": [
        "6e5e3b2e914cf4bdc5f17a6011fc2b1937eb9641"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Aug 01 17:41:45 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Aug 02 11:21:49 2016 +0100"
      },
      "message": "ARM: Embed 0.0 in VCMP.\n\nTest: Run ART test suite on Nexus 5.\nChange-Id: I5cbbd98c4d64a4d9213e27adcae929ead5099a39\n"
    },
    {
      "commit": "ba65cc4a71273904294245cb37ce70e5bce797e3",
      "tree": "d53a7a816ec4c8e5bdbf80729ac945787b27bf2c",
      "parents": [
        "1a827a05afbffd5bee241f245f9aa3c40b4dbae4",
        "542451cc546779f5c67840e105c51205a1b0a8fd"
      ],
      "author": {
        "name": "Treehugger Robot",
        "email": "treehugger-gerrit@google.com",
        "time": "Tue Aug 02 03:47:35 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Aug 02 03:47:35 2016 +0000"
      },
      "message": "Merge \"ART: Convert pointer size to enum\""
    },
    {
      "commit": "542451cc546779f5c67840e105c51205a1b0a8fd",
      "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a",
      "parents": [
        "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Jul 26 09:02:02 2016 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Aug 01 18:54:48 2016 -0700"
      },
      "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n"
    },
    {
      "commit": "33dd909468e377aaa8f0ec27fc4b3cb4d8481119",
      "tree": "fc6c11800d7fa7ace2f44d0bf863f23b54084a18",
      "parents": [
        "e304fc28c4a7d57532498239f9b52d2d5b8974d5"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Aug 01 15:55:36 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Aug 01 16:11:10 2016 -0700"
      },
      "message": "Fixed bug in disassembly of roundss/roundsd\n\nRationale:\nThese instructions should be marked as load, so that, using\nIntel syntax, destination (xmm0) appears at left hand side, as in\n   roundss xmm0, xmm1\nand not the other way around. First I suspected a bug in the\nencoding (hence the test) and even the register allocator, but\nsince the code behaved correctly, only disassembly was really wrong.\n\nTest: disassembler_x86_test (but nothing for actual disassembly)\n\nBUG\u003d26327751\n\nChange-Id: I060ef57f4d5a64cdc04b97ae8a799d1c0d22da05\n"
    },
    {
      "commit": "ecf75a6a9396475759c5f8b47cdc1929614b9542",
      "tree": "c2816628ca0229ca2da6dde0699eb22f48de3f65",
      "parents": [
        "998bf2b4de04f1664a8ca0085740e266b9e7c4ff"
      ],
      "author": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Thu Jul 28 16:01:42 2016 -0700"
      },
      "committer": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Thu Jul 28 17:12:54 2016 -0700"
      },
      "message": "ART: remove gcc cruft from the makefiles\n\nART only builds with clang now, delete all logic to determine gcc\nvs. clang, and move all LOCAL_CLANG_CFLAGS into LOCAL_CFLAGS.\n\nTest: mma, make test-art-host, make test-art-target\nChange-Id: I578615233ad3e71af18afb47bb11f3be8417216c\n"
    },
    {
      "commit": "5668e58daf0f54d6cc8a6919033acc3506fc86ee",
      "tree": "de19460ff3c2f940ce5b0f7036a4bf756b59ed4e",
      "parents": [
        "24670a7aac24c7a9b661220ab76b36c75f1494c5",
        "97c72b76cf776228196c6abd33973ef751de61ad"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Jul 18 14:28:05 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Jul 18 14:28:06 2016 +0000"
      },
      "message": "Merge \"Fixes to build against new VIXL interface.\""
    },
    {
      "commit": "161c866ca742049f5c916696e1503c697be30e87",
      "tree": "b3e5c572c840c04e0651cd923b0188427e136f8f",
      "parents": [
        "edec0eb18d9a45d994acec9e8e509a1dc05bd5b3",
        "4414822df8483d499fbac02563ebe8c7fc000563"
      ],
      "author": {
        "name": "Treehugger Robot",
        "email": "treehugger-gerrit@google.com",
        "time": "Fri Jul 15 16:40:28 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Jul 15 16:40:28 2016 +0000"
      },
      "message": "Merge \"ART: disassembler_x86 doesn\u0027t recognize NOPs\""
    },
    {
      "commit": "97c72b76cf776228196c6abd33973ef751de61ad",
      "tree": "7a78a2b19b0847281f8cf69af735b30b15732fa8",
      "parents": [
        "1fd347303275a424d114c9833f954e8e27812554"
      ],
      "author": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Fri Jun 24 16:19:36 2016 +0100"
      },
      "committer": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Fri Jul 15 09:48:07 2016 +0100"
      },
      "message": "Fixes to build against new VIXL interface.\n\n- Fix namespace usage and use of deprecated functions.\n- Link all dependants to new libvixl-arm64 target for now.\n\nChange-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509\n"
    },
    {
      "commit": "194bcfea4a29db2c529de333c6a00b32608dd4e5",
      "tree": "83c8c87448730de7d8a0a4ac51414806ae0b9090",
      "parents": [
        "dedde3f10d7801ad862d1ca1de89135decff6a60"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Jul 11 15:52:00 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jul 12 12:04:19 2016 +0100"
      },
      "message": "ARM: Shorter fast-path for read barrier field load.\n\nReduces the aosp_hammerhead-userdebug boot.oat by 2.2MiB,\ni.e. ~2.2%, in the ART_USE_READ_BARRIER\u003dtrue configuration.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on Nexus 5.\nBug: 29966877\nBug: 12687968\nChange-Id: I4454150003e12a1aa7f0cf451627dc1ee9a495ae\n"
    },
    {
      "commit": "dedde3f10d7801ad862d1ca1de89135decff6a60",
      "tree": "da68a5a4d91875628c528be3556f5a681d53625f",
      "parents": [
        "a14893e4a95eb4d17759173daf8ebf78fcc28086",
        "b5390f71940f2188da9e093d4130753bfb88e25a"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Jul 11 09:24:43 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Jul 11 09:24:44 2016 +0000"
      },
      "message": "Merge \"Have LOCAL_ASFLAGS honor debug/non-debug configuration.\""
    },
    {
      "commit": "b5390f71940f2188da9e093d4130753bfb88e25a",
      "tree": "548e378c7776cf535cbe8850a391c33553397d6a",
      "parents": [
        "a7821bffd3aba0705144059c30ba0fef4a400e3d"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Jul 04 16:59:53 2016 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Jul 04 16:59:53 2016 +0100"
      },
      "message": "Have LOCAL_ASFLAGS honor debug/non-debug configuration.\n\nWith this change the NDEBUG macro can be used in assembly\nfiles.\n\nChange-Id: I640594a20d5654de62cd4116087040b565eef0ce\nTest: ART host tests.\n"
    },
    {
      "commit": "e3fb245fbdb5e91cf8a9750504df40bd629e0080",
      "tree": "a3882db92b7942b2edd6add3090b5c875fef2d09",
      "parents": [
        "1fdb340de4e608a88e8683c857cad5d0da2c16de"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue May 10 16:08:05 2016 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Fri Jul 01 14:10:14 2016 -0700"
      },
      "message": "MIPS32: Improve method invocation\n\nImprovements include:\n- CodeGeneratorMIPS::GenerateStaticOrDirectCall() supports:\n  - MethodLoadKind::kDirectAddressWithFixup (via literals)\n  - CodePtrLocation::kCallDirectWithFixup (via literals)\n  - MethodLoadKind::kDexCachePcRelative\n- 32-bit literals to support the above (not ready for general-\n  purpose applications yet because RA is not saved in leaf\n  methods, but is clobbered on MIPS32R2 when simulating\n  PC-relative addressing (MIPS32R6 is OK because it has\n  PC-relative addressing with the lwpc instruction))\n- shorter instruction sequences for recursive static/direct\n  calls\n\nTested:\n- test-art-host-gtest\n- test-art-target-gtest and test-art-target-run-test-optimizing on:\n  - MIPS32R2 QEMU\n  - CI20 board\n  - MIPS32R6 (2nd arch) QEMU\n\nChange-Id: Id5b137ad32d5590487fd154c9a01d3b3e7e044ff\n"
    },
    {
      "commit": "a77ceae14a7be2494874d9256327efa8c522e234",
      "tree": "e0f95e465187f0790617123257783fdf102b5547",
      "parents": [
        "19c10147cd5f3270c8604d06c4a0e05cbc49e2f1",
        "a8aaf5a18ad42f3aea9afb3c8d383fe331798c9f"
      ],
      "author": {
        "name": "Treehugger Robot",
        "email": "treehugger-gerrit@google.com",
        "time": "Thu Jun 30 13:41:55 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Jun 30 13:41:55 2016 +0000"
      },
      "message": "Merge \"MIPS32: Disassemble and test movf.fmt and movt.fmt (missed earlier)\""
    },
    {
      "commit": "a8aaf5a18ad42f3aea9afb3c8d383fe331798c9f",
      "tree": "56c7500a4c362f56d1c8fec471c61baf810b6658",
      "parents": [
        "12e6e9f3f1352ed58ddd41c7f31831011695b9e4"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Mon Jun 27 14:48:20 2016 -0700"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Jun 30 13:41:14 2016 +0000"
      },
      "message": "MIPS32: Disassemble and test movf.fmt and movt.fmt (missed earlier)\n\nTest: ART gtest assembler_mips_test\nChange-Id: Iafedfafe6ccd76127461d66dfa7984f196be6bd2\n"
    },
    {
      "commit": "e652c122d8cc9697d368b9ceada9b377d091e4fd",
      "tree": "699f7f7bc88ff28d2b8f8e735ea48693aa653c95",
      "parents": [
        "ca7399a1d7b3c92d73322adf54187fde31eee1bd"
      ],
      "author": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Mon Jun 13 14:42:27 2016 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Jun 28 13:29:29 2016 +0000"
      },
      "message": "ARM assembler support for VCNT and VPADDL.\n\nTest: Gtest assembler_thumb2_test.\nChange-Id: I8a0e47da746e1c67650cb68196a9f661deed7383\n"
    },
    {
      "commit": "d3059e77818a058513ed92557160bdb6d5102b67",
      "tree": "cff82528de3dd71104d9b3fa4e1a57f2c9fc81dc",
      "parents": [
        "b0fca360a081eff1a44c6f055c628e2dba44c003"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed May 11 10:30:47 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu May 12 10:01:08 2016 -0700"
      },
      "message": "Fix oatdump crash on arm64/arm code.\nAlso adds 16 bit literal information.\n\nRationale:\nWhen \"run-away\" instructions are disassembled, the literal\naddresses may go out of range, causing oatdump to crash.\nThis CL guards memory access against the full memory range\nallocated to assembly instructions and data (it is possible\nbut not really necessary to refine this a bit). Out of range\narguments are now displayed as (?) to denote the issue, which\nis a lot nicer than crashing.\n\nBUG\u003d28670871\n\nChange-Id: I51e9b6a6a99162546fe31059f14278e8980451c2\n"
    },
    {
      "commit": "cb55b29e466939d222b83f0593a1141221f2425c",
      "tree": "0f9aef9da0889961b1ce00c324e1c56487b9ef53",
      "parents": [
        "0d399c71cb176b0a31d6d51f950c7c32a43668ef"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Apr 21 14:52:03 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Apr 21 15:17:34 2016 +0100"
      },
      "message": "Thumb2: Fix disassembly of the b.w offset.\n\nBug: 28311085\nChange-Id: If729af888be65e1f24362b9c4ed79f124446024d\n"
    },
    {
      "commit": "adf1eaaac71b6b440855d48154c17bfdc326904c",
      "tree": "ab0a07335a291f8c49a19f2ff848d625a0f958a9",
      "parents": [
        "5827507da8efdaf4536c70dfdc54407c28e37852"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Apr 06 19:05:19 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Apr 06 19:08:09 2016 +0100"
      },
      "message": "Thumb2: Show the immediate in ROR (immediate) disassembly.\n\nNow disassembled as \"mov ., ., ror #imm5\".\n\nChange-Id: Iad201662fd6aa3f87b95c7293fafe030c4bbdbf3\n"
    },
    {
      "commit": "51aff3a6564303cab0b7ac82495b4e2e349c6ff3",
      "tree": "783344fdc2f757a8fce4ac1b565e2b2798415d2d",
      "parents": [
        "6a329292736c3dd74e9c8cb319c2a233d07fe524"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Thu Mar 17 17:21:45 2016 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Mon Mar 21 15:23:42 2016 -0700"
      },
      "message": "MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics.\n\nChange-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf\n"
    },
    {
      "commit": "07f6818ef68046d4749963b3bd59f7e93cf43fa9",
      "tree": "f92c036b6340bba99208ca2810f1453ed45d35d7",
      "parents": [
        "8411aa3d88f4baf583ec4ecd62bb619cacd28acb"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Mar 10 17:25:50 2016 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Mar 10 17:30:25 2016 +0000"
      },
      "message": "ART: Do not use vixld - workaround to fix dex2oatds.\n\nThis is a quick workaround for ODR violations caused\nby linking libvixl.a compiled without VIXL_DEBUG with\nthe libartd-compiler.a compiled with VIXL_DEBUG.\n\nBug: 27588884\nChange-Id: Ib1af165f177f125f03cdd99777dff4c2912f6405\n"
    },
    {
      "commit": "3acee732f9475fbfc6b046e0044b764e7ff5ac01",
      "tree": "3b87f8b93c427c05e7690ea8d14577ce3e9eb502",
      "parents": [
        "34937e2ed46fa9f56d99e9f32e0bfad050e5e798"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Nov 18 13:31:08 2015 -0800"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Feb 10 16:12:56 2016 -0800"
      },
      "message": "MIPS32: peek*/poke*, and String.charAt intrinsics.\n\n- byte libcore.io.Memory.peekByte(long address)\n- short libcore.io.Memory.peekShort(long address)\n- int libcore.io.Memory.peekInt(long address)\n- long libcore.io.Memory.peekLong(long address)\n- void libcore.io.Memory.pokeByte(long address, byte value)\n- void libcore.io.Memory.pokeShort(long address, short value)\n- void libcore.io.Memory.pokeInt(long address, int value)\n- void libcore.io.Memory.pokeLong(long address, long value)\n- char java.lang.String.charAt(int index)\n\nChange-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa\n"
    },
    {
      "commit": "8cdbc2aef0ece0f3665966e793c075844b52b67d",
      "tree": "df2370a274b937f5d2a911019efd8fa42f59bdd6",
      "parents": [
        "fc06b93dee031ec16272ec64fca92a0e639ae73e"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Feb 10 12:52:59 2016 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Feb 10 13:18:41 2016 +0000"
      },
      "message": "ART/Thumb2: Disassemble SBFX/UBFX.\n\nChange-Id: I856206de81f41959f68de0653db021903dd1a210\n"
    },
    {
      "commit": "3f67e692860d281858485d48a4f1f81b907f1444",
      "tree": "a14d3bdc1416dc3db74983d34a408a8b48cbce9c",
      "parents": [
        "6aadaef35ea52506db61e463910c2520b702ca5e"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Jan 15 14:35:12 2016 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jan 20 20:14:00 2016 -0800"
      },
      "message": "Implemented BitCount as an intrinsic. With unit test.\n\nRationale:\nRecognizing this important operation as an intrinsic has\nvarious advantages:\n(1) having the no-side-effects/no-throw allows for\n    much more GVN/LICM/BCE.\n(2) Some architectures, like x86_64, provide direct\n    support for this operation.\n\nPerformance improvements on X86_64:\nCheckersEvalBench (32-bit bitboard): 27,210KNS -\u003e 36,798KNS  \u003d  + 35%\nReversiEvalBench  (64-bit bitboard): 52,562KNS -\u003e 89,086KNS  \u003d  + 69%\n\nChange-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f\n"
    },
    {
      "commit": "4414822df8483d499fbac02563ebe8c7fc000563",
      "tree": "bb28eecb8be4603c0ce6e9cd28d93c4983689c46",
      "parents": [
        "6aadaef35ea52506db61e463910c2520b702ca5e"
      ],
      "author": {
        "name": "Serdjuk, Nikolay Y",
        "email": "nikolay.y.serdjuk@intel.com",
        "time": "Mon Sep 14 18:05:33 2015 +0600"
      },
      "committer": {
        "name": "Nikolay Y Serdjuk",
        "email": "nikolay.y.serdjuk@intel.com",
        "time": "Thu Jan 21 03:33:37 2016 +0000"
      },
      "message": "ART: disassembler_x86 doesn\u0027t recognize NOPs\n\nThere are some variations of NOPs which are possible on x86.\n\nChange-Id: I6aab3bc98682e521532cc746f3a371d9c5d98ee8\n"
    },
    {
      "commit": "92d9060c0cdff7c726549a9d9494e5655404bed7",
      "tree": "22c1274193e7f1a3bd9872a2455c758394587dee",
      "parents": [
        "376a6f3dbae7b71a6fc2c339ec416d3407277308"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Fri Dec 18 18:16:36 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Mon Jan 04 20:53:44 2016 -0800"
      },
      "message": "MIPS: Implement HRor\n\nThis also fixes differentiation between the SRL and ROTR\ninstructions in the disassembler.\n\nChange-Id: Ie19697f8d6ea8fa4e338adde3e3cf8e4a0383eae\n"
    },
    {
      "commit": "5c7aed3b9844e240cf785e5885524ac133a04396",
      "tree": "acc868d1478f0410fda4d0f6de3c60755aa6680e",
      "parents": [
        "1c70f18dce7705ff70147ddebf65a97f66df8d5c"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Nov 25 19:41:54 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Dec 16 15:33:30 2015 -0800"
      },
      "message": "MIPS32: improvements in code generation (mostly 64-bit ALU ops)\n\nSpecifically:\n- Use the delay slot in InvokeRuntime() for direct entry points\n- Use kNoOutputOverlap wherever possible\n- Improve and/or/xor/add/sub with 64-bit integer constants\n- Improve 64-bit shifts by a constant amount on R2+\n- More efficient load/store of 64-bit constants (especially, 0 \u0026 +0.0)\n\nChange-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b\n"
    },
    {
      "commit": "cd7b0ee296b0462961c63e51d99c9c323e2690df",
      "tree": "57a9071635389e58a8912d98b99d7e114c1efcc6",
      "parents": [
        "0bbc1727c446ee5f4cc3c28e68127164ef379594"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Thu Dec 03 16:46:38 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Dec 15 14:29:48 2015 -0800"
      },
      "message": "MIPS32: Fuse long and FP compare \u0026 condition in Optimizing.\n\nThis also does a minor clean-up in the assembler and\nits test.\n\nBug: 25559148\nChange-Id: I9bad3c500b592a09013b56745f70752eb284a842\n"
    },
    {
      "commit": "e384547851a9d9e5d89ae5bb4c16bfd7d93cc12e",
      "tree": "41ba461c62b6a89253b59117a68beae05df5006f",
      "parents": [
        "70014c8af8d3a20c2987c308788bc86671bc39e9"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Nov 18 12:27:15 2015 -0800"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Mon Nov 30 17:27:36 2015 -0800"
      },
      "message": "MIPS32: int java.lang.*.numberOfLeadingZeros\n\n- int java.lang.Integer.numberOfLeadingZeros(int)\n- int java.lang.Long.numberOfLeadingZeros(long)\n\nChange-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58\n"
    },
    {
      "commit": "7d4152f3520a3899ab57b61b884a17a2ba49a2ad",
      "tree": "cb57603e94688a4736798b18d157e4b325885509",
      "parents": [
        "e033ea69bcd1f343c3cf944d78beec726faf348f"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Mon Oct 19 15:17:16 2015 -0700"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Mon Oct 19 17:26:50 2015 -0700"
      },
      "message": "MIPS64: Disassembler support for rotate instructions.\n\nAlso, tighten the tests for recognizing the various shift commands. The\ntests, previously, would be unable to distinguish between \"shift right\nlogical\" and \"rotate right\" commands. In particular:\n\n- SRLV vs. ROTRV\n- DSRLV vs. DROTRV,\n- DSRL vs. DROTR, and\n- DSRL32 vs. DROTR32\n\nChange-Id: I7a6df8ab0d76fd3d34b1207da9915369ad84fa97\n"
    },
    {
      "commit": "8c434dcc78d497e18590461700894d1c3e96013d",
      "tree": "6fc88cc839c0415aa90a1bbff25e93a09705d19b",
      "parents": [
        "35ef974da353b13938fb0f3272c03070ad728431"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Wed Aug 26 14:39:44 2015 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Tue Oct 06 16:34:25 2015 +0200"
      },
      "message": "MIPS: Assemblers changes needed for optimizing compiler\n\nAlso add assembler tests for MIPS32.\n\nChange-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775\n"
    },
    {
      "commit": "e295be4a95d7861f6ec179edf6565f58cad747cc",
      "tree": "a994a7f270e8dd81e3bb1a704c4ee5f6ea98aa7c",
      "parents": [
        "9ea4a93674b42f213334bb83d1982db11091b96a",
        "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Sep 16 04:21:39 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Sep 16 04:21:39 2015 +0000"
      },
      "message": "Merge \"Additional MIPS64 instructions needed by intrinsics code.\""
    },
    {
      "commit": "bcee092d7b0cbb7181d428115ad98d25ce844061",
      "tree": "dab00e7f7dc19b002948020a8c2cbde665203c0e",
      "parents": [
        "b505997b2176bd29a108cb6c33d06d4ef29ba001"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Sep 15 21:45:01 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Sep 15 21:45:01 2015 -0400"
      },
      "message": "Add X86 bsf and rotate instructions\n\nThese are for use in new intrinsics.  Bsf (Bit Scan Forward) is used in\n{Long,Integer}NumberOfTrailingZeros and the rotates are used in\n{Long,Integer}Rotate{Left,Right}.\n\nChange-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536",
      "tree": "efdfc90c1cdb4b688c0cdf6c2cf2cfe7b8121d1c",
      "parents": [
        "010c7fd437932e0132fc4b44de6274480573ff30"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Fri Aug 14 14:56:10 2015 -0700"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Thu Sep 10 10:59:11 2015 -0700"
      },
      "message": "Additional MIPS64 instructions needed by intrinsics code.\n\nChange-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe\n"
    },
    {
      "commit": "2a5c4681ba19411c1cb22e9a7ab446dab910af1c",
      "tree": "883ea0c07aad9efdb7c86960056cbefd7992b2bc",
      "parents": [
        "228b3973b2b24783c727a55fda2b4b80375f7207"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Aug 14 08:22:54 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Aug 17 15:42:25 2015 -0700"
      },
      "message": "ART: Some header cleaning around bit-utils\n\nTry to remove dependencies where they are not necessary.\n\nChange-Id: I5ff35cb17aea369bed3725b1610b50d7eb05b81e\n"
    },
    {
      "commit": "8ae3ffb29489a127f2a6242c33845dac8d50e508",
      "tree": "cb5cc72e4a699a8ef6b044d530539c13b02604b7",
      "parents": [
        "f67ab129d868b8355a8403a9627f96ac1e41a796"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Aug 12 21:16:41 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Aug 14 12:58:40 2015 -0400"
      },
      "message": "Add \u0027bsr\u0027 instruction to x86 and x86_64\n\nAdd support for \u0027bsr\u0027 instruction.  Add tests.\n\nChange-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "b9c4bbee9364a9351376fd1fec9604e7c84778d8",
      "tree": "2e0fb139b709cb0bb10f4a15067c9b302eeb0dce",
      "parents": [
        "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Jul 01 14:26:52 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Aug 14 11:07:57 2015 -0400"
      },
      "message": "Add rep movsw to x86 and x86_64 instructions.\n\nAdd \u0027REP MOVSW\u0027 as a supported instruction for x86 32 and 64 bit.\n\nAdded tests.\n\nChange-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "3887c468d731420e929e6ad3acf190d5431e94fc",
      "tree": "67dacb849e722e33e118b97714a48e467c06cbd5",
      "parents": [
        "6a5037eb3340e4c981fd7de3ff45167ee5b7fc82"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Aug 12 18:15:42 2015 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Aug 12 18:15:42 2015 +0100"
      },
      "message": "Remove unnecessary `explicit` qualifiers on constructors.\n\nChange-Id: Id12e392ad50f66a6e2251a68662b7959315dc567\n"
    },
    {
      "commit": "5e2c8d323fbab4db8a71041ff94b6baf3953bca9",
      "tree": "12030091e7359b656abe46f601aa5230b1dec880",
      "parents": [
        "1f3f766d3b365d01f36b85dc19d40f754fa48533"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Thu Aug 06 14:49:28 2015 +0100"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Thu Aug 06 15:32:28 2015 +0100"
      },
      "message": "Introduce arch-specific checker tests.\n\n- The \u0027.cfg\u0027 output is now created on target.\n- Arch-specific checker tests can be created by inserting a\n  suffix. For example:\n      /// CHECK-START-ARM64: int Main.foo(int) register (after)\n      /// CHECK-DAG:   \u003c\u003cArg:i\\d+\u003e\u003e     ParameterValue\n\nChange-Id: I55cdb37f8e806c7ffdde6b676c8f44ac30b59051\n"
    },
    {
      "commit": "611d3395e9efc0ab8dbfa4a197fa022fbd8c7204",
      "tree": "9a0a3b6750caae13b963b244719e03b8cfb49c44",
      "parents": [
        "0c9c5bbdd6976c21602b92d9b455e6fe5d769fb0"
      ],
      "author": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Fri Jul 10 11:42:06 2015 +0100"
      },
      "committer": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Tue Aug 04 09:02:56 2015 +0100"
      },
      "message": "ARM/ARM64: Implement numberOfLeadingZeros intrinsic.\n\nChange-Id: I4042fb7a0b75140475dcfca23e8f79d310f5333b\n"
    },
    {
      "commit": "124b392d35595f5a8e31e6a9dbefcff5b3ef5760",
      "tree": "ee2e8c02bde328814d045c98067874ad3a302136",
      "parents": [
        "5d2ed003020feee437683b84e4ea6b8c6a5753e0"
      ],
      "author": {
        "name": "agicsaki",
        "email": "agicsaki@google.com",
        "time": "Thu Jul 30 13:40:13 2015 -0700"
      },
      "committer": {
        "name": "agicsaki",
        "email": "agicsaki@google.com",
        "time": "Thu Jul 30 13:58:52 2015 -0700"
      },
      "message": "Added disassembler support for repe_cmpsw instruction in x86, x86_64\n\nAlso included support for repe_cmpsl instruction. This is a follow up to\ncommit 71311f868e2 which added support for repe_cmpsw in the x86 and\nx86_64 assemblers.\n\nChange-Id: I2beac05a57341539acf96cdf77062facd031a864\n"
    },
    {
      "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907",
      "tree": "a0a488040883c14cc6cbec3186654137459d44ff",
      "parents": [
        "8ec0e20347e13592539a8c0786b1db1735149800"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Jun 19 14:47:01 2015 +0100"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Mon Jun 22 11:57:36 2015 +0100"
      },
      "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n"
    },
    {
      "commit": "4dda3376b71209fae07f5c3c8ac3eb4b54207aa8",
      "tree": "0d96a327d1b3a7e09eff178a66c0b5fb946cfc85",
      "parents": [
        "71af6f7aab7491665fe2d6beb9af4c251a99ad56"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Mon Jun 01 18:31:49 2015 -0700"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jun 19 15:43:58 2015 +0100"
      },
      "message": "MIPS: Initial version of optimizing compiler for MIPS64R6.\n\nBug: 21555893\nChange-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf\nSigned-off-by: Alexey Frunze \u003cAlexey.Frunze@imgtec.com\u003e\nSigned-off-by: Douglas Leung \u003cdouglas.leung@imgtec.com\u003e\n"
    },
    {
      "commit": "12bd7210bb2f5738e33dfa3f2f1cba2e0aab4955",
      "tree": "ceff4c27b7d3173da61dda12b1b05e062e82e3d9",
      "parents": [
        "2519fc40d4ae89322d28d1ff610fe81bb90fb564"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Jun 04 17:50:27 2015 +0100"
      },
      "committer": {
        "name": "Hiroshi Yamauchi",
        "email": "yamauchi@google.com",
        "time": "Thu Jun 04 11:26:19 2015 -0700"
      },
      "message": "If heap poisoning is on, pass the relevant flag to LOCAL_ASFLAGS.\n\nThis change ensures assembly files honoring heap poisoning\n(notably used by stub_test) are compiled with\n-DART_HEAP_POISONING\u003d1 when this feature is turned on.\n\nBug: 21621105\nChange-Id: I13fe456cd2733a09bdfd3a9808cfd70513b14698\n"
    },
    {
      "commit": "9bd88b0933a372e6a7b64b850868e6a7998567e2",
      "tree": "bcd275674c1234842b757ea8e100c4030f9ac6fe",
      "parents": [
        "01cb410f4ad23135671d821ba36c269f8c82affa"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@linaro.org",
        "time": "Wed Apr 22 16:24:46 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri May 22 12:01:07 2015 +0100"
      },
      "message": "ARM64: Move xSELF from x18 to x19.\n\nThis patch moves xSELF to callee saved x19 and removes support for\nETR (external thread register), previously used across native calls.\n\nChange-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n"
    },
    {
      "commit": "e0705f51fdc71e9670a29f8c3a47168f50724b35",
      "tree": "4a9a2d808441843bed332b0bdad3aec0a7aa4cee",
      "parents": [
        "64db01714f91bf255a79c0a88813641c240c9857"
      ],
      "author": {
        "name": "nikolay serdjuk",
        "email": "nikolay.y.serdjuk@intel.com",
        "time": "Mon Apr 27 17:52:57 2015 +0600"
      },
      "committer": {
        "name": "nikolay serdjuk",
        "email": "nikolay.y.serdjuk@intel.com",
        "time": "Wed Apr 29 12:17:35 2015 +0600"
      },
      "message": "Fix for incorrect encode and parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F 3A 15\nwas incorrectly encoded in compiler table and incorrectly\nparsed by disassembler.\n\nChange-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164\nSigned-off-by: nikolay serdjuk \u003cnikolay.y.serdjuk@intel.com\u003e\n"
    },
    {
      "commit": "2cebb24bfc3247d3e9be138a3350106737455918",
      "tree": "d04d27d21b3c7733d784e303f01f873bb99e7770",
      "parents": [
        "1f02f1a7b3073b8fef07770a67fbf94afad317f0"
      ],
      "author": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Tue Apr 21 16:50:40 2015 -0700"
      },
      "committer": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Wed Apr 22 12:44:27 2015 -0700"
      },
      "message": "Replace NULL with nullptr\n\nAlso fixed some lines that were too long, and a few other minor\ndetails.\n\nChange-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb\n"
    },
    {
      "commit": "6daa9efe959b631d063eeb8d715a740c279f6c57",
      "tree": "099cbe401a71c3951ae9f0cfcef969c42f1c167a",
      "parents": [
        "ee3b260e6b46982047a6c249b70bab3b077d7780",
        "403e0d55a3e9c18d4228d0aab31dec0c908dc73d"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Apr 09 23:33:24 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 09 23:33:25 2015 +0000"
      },
      "message": "Merge \"[MIPS] Refactoring code for disassembler\""
    },
    {
      "commit": "03fe9c80f514de61d52b65f6972d66b464a3d2fd",
      "tree": "fe4ac169af548b9720e0bdb5786328f9b2b56e88",
      "parents": [
        "19361054a362957e152db65c9033408486c6af28",
        "bd4e6a828fc4aefea7d34a1bbedb81c560c60b6b"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Apr 09 16:40:40 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 09 16:40:40 2015 +0000"
      },
      "message": "Merge \"Fix for incorrect parse of PEXTRW instruction\""
    },
    {
      "commit": "403e0d55a3e9c18d4228d0aab31dec0c908dc73d",
      "tree": "22beb87b8be836e2851bb2637446ceb47d9d4389",
      "parents": [
        "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Wed Apr 08 16:26:05 2015 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Thu Apr 09 08:23:53 2015 +0200"
      },
      "message": "[MIPS] Refactoring code for disassembler\n\nCode for mips64 is merged with code for mips.\n\nChange-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9\n"
    },
    {
      "commit": "caff30245889729f102af87e79705893401251ef",
      "tree": "4793d6d6bc4adab2ad61e6876b5a24996fb365d6",
      "parents": [
        "030d304aec321a21a4d577f3e7b4cd8e912ef901",
        "d2c80c419f1e16875f556de371e10257bcb59075"
      ],
      "author": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Tue Apr 07 12:38:57 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Apr 07 12:38:59 2015 +0000"
      },
      "message": "Merge \"Fix address formatting in Mips64 disassembler.\""
    },
    {
      "commit": "030d304aec321a21a4d577f3e7b4cd8e912ef901",
      "tree": "540a947026809e5fc69f45d9019f4b0063f901c5",
      "parents": [
        "47cf461b1b4125aedfef42aa5b4162f63aa8b8f3",
        "588e8e1359d3ef05aca27743e70d45fe57acd304"
      ],
      "author": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Tue Apr 07 12:38:16 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Apr 07 12:38:18 2015 +0000"
      },
      "message": "Merge \"Build 32-bit version of the disassembler as well.\""
    },
    {
      "commit": "bd4e6a828fc4aefea7d34a1bbedb81c560c60b6b",
      "tree": "980f9eaa46f3368927e70c0122c9542b92e3368e",
      "parents": [
        "a68a7cf8f3a6fef22d71a14350176115cb13857f"
      ],
      "author": {
        "name": "nikolay serdjuk",
        "email": "nikolay.y.serdjuk@intel.com",
        "time": "Fri Mar 27 16:32:27 2015 +0600"
      },
      "committer": {
        "name": "nikolay serdjuk",
        "email": "nikolay.y.serdjuk@intel.com",
        "time": "Tue Apr 07 11:42:00 2015 +0600"
      },
      "message": "Fix for incorrect parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F C5 has form:\nPEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and\nxmm is encoded in the R/M part of ModR/M byte. Since the order\nis opposite to the PEXTRB and PEXTRD, we have to set \u0027load\u0027 to\ntrue and \u0027store\u0027 leave as false.\n\nChange-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d\n"
    },
    {
      "commit": "65b798ea10dd716c1bb3dda029f9bf255435af72",
      "tree": "774e9901b6917989a63f07f927c3b4d8b921a013",
      "parents": [
        "c411c6cc327d3f2b3b4d1987b07dd442205d9454"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Apr 06 09:35:22 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Apr 06 14:05:07 2015 -0700"
      },
      "message": "ART: Enable more Clang warnings\n\nChange-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c\n"
    },
    {
      "commit": "d2c80c419f1e16875f556de371e10257bcb59075",
      "tree": "4005dceed1de90663568bee06f154521b9befba6",
      "parents": [
        "9d231cc422b7b32d00bd43ca6993b2dd7e9989ea"
      ],
      "author": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Mon Apr 06 18:42:26 2015 +0100"
      },
      "committer": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Mon Apr 06 18:45:58 2015 +0100"
      },
      "message": "Fix address formatting in Mips64 disassembler.\n\nUse FormatInstructionPointer like all the other disassemblers.\nThis ensures that the \u0027absolute_addresses\u0027 option is honoured.\n\nChange-Id: I5580319cc4fad40e00f3fbbde25b142f7c689390\n"
    },
    {
      "commit": "588e8e1359d3ef05aca27743e70d45fe57acd304",
      "tree": "aac3e447b0cc2ac23a05ad2d01b6aa5c51944cb7",
      "parents": [
        "9d231cc422b7b32d00bd43ca6993b2dd7e9989ea"
      ],
      "author": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Mon Apr 06 18:36:59 2015 +0100"
      },
      "committer": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Mon Apr 06 18:36:59 2015 +0100"
      },
      "message": "Build 32-bit version of the disassembler as well.\n\nChange-Id: I22ecc2611c3b05b1031b42abdb5bf8c245220e03\n"
    },
    {
      "commit": "97597c9be7f4eb5263a80e7de4684dbfa1427e9a",
      "tree": "690dc04c72690a056aa84ac0206f96e5f513b3c2",
      "parents": [
        "7775d2c1e48c0bb0880f720f3dfbd4b4d0de7c6e",
        "fb8d279bc011b31d0765dc7ca59afea324fd0d0c"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Apr 02 23:10:46 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 02 23:10:46 2015 +0000"
      },
      "message": "Merge \"[optimizing] Implement x86/x86_64 math intrinsics\""
    },
    {
      "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c",
      "tree": "01b21964ce0516bda835faa15b260ac290714fe0",
      "parents": [
        "dcff612c3a6e1427749771c4559f198fa480f709"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Mar 31 22:16:59 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Apr 01 08:45:38 2015 -0400"
      },
      "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures.  Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "82e52ce8364e3e1c644d0d3b3b4f61364bf7089a",
      "tree": "d26020cbee67645a46838c57747d2ba1533ba5d1",
      "parents": [
        "ebbb1e322d8c89e69424a543faa03402e5b63673"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Mar 26 16:50:57 2015 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Tue Mar 31 15:53:57 2015 +0100"
      },
      "message": "ARM64: Update to VIXL 1.9.\n\nUpdate VIXL\u0027s interface to VIXL 1.9.\n\nChange-Id: Iebae947539cbad65488b7195aaf01de284b71cbb\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "027f0ff64c2512b9a5f1f54f3fea1bec481eb0f5",
      "tree": "9202535f219d7343b4c26d5c43f0bcb7c31650df",
      "parents": [
        "6cc763c8b8157fb42dd44e1dfb84812546500dc1"
      ],
      "author": {
        "name": "Douglas Leung",
        "email": "douglas.leung@imgtec.com",
        "time": "Fri Feb 27 19:05:03 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Mar 20 16:51:56 2015 -0700"
      },
      "message": "ART: Add Mips32r6 backend support\n\nAdd Mips32r6 compiler support.\n\nDon\u0027t use deprecated Mips32r2 instructions if running in Mips32r6\nmode.\n\nChange-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67\n"
    },
    {
      "commit": "6ea651f0f4c7de4580beb2e887d86802c1ae0738",
      "tree": "fd97dcbd7301892cb785ca34aee21ad86437c3b3",
      "parents": [
        "0e242b5cad3c0b68b72f28c1e5fd3fdd4c05bfd8"
      ],
      "author": {
        "name": "Maja Gagic",
        "email": "maja.gagic@imgtec.com",
        "time": "Tue Feb 24 16:55:04 2015 +0100"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Mar 06 13:05:47 2015 -0800"
      },
      "message": "Initial support for quick compiler on MIPS64r6.\n\nChange-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8\n"
    },
    {
      "commit": "d737ab33a458537fca6207e9e4e25198a1511113",
      "tree": "5d365b8def0e9a8a87ff86c5b12559ff74e8f831",
      "parents": [
        "65405378f4fd207dcd7d99916c2397a0da08438f"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Fri Mar 06 09:11:12 2015 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Fri Mar 06 10:45:10 2015 +0000"
      },
      "message": "ART: Enable the use of relative addresses in the arm64 disassembler.\n\nAlso, only keep register aliases for the link register \u0027lr\u0027 and the\nthread register \u0027tr\u0027 in the arm64 disassembler. Other aliases are not\nvery important, and this way we don\u0027t have to provide aliases\nspecialised for Quick or Optimizing.\n\nChange-Id: Ie7a04910f0c587710a0cf2648203d7e89eab5d1f\n"
    },
    {
      "commit": "1cd27903529ee10229fa639dc8438a75517de492",
      "tree": "c3689e5286876ea6deb967a79869bac5d270551f",
      "parents": [
        "f5c224cca603ef1dba9bb80952613facc22598fa"
      ],
      "author": {
        "name": "Douglas Leung",
        "email": "douglas.leung@imgtec.com",
        "time": "Fri Feb 13 16:55:57 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Sat Feb 28 00:11:26 2015 +0000"
      },
      "message": "ART: Fix Mips disassembler for some floating point instructions.\n\nChange-Id: I2b661a8dae4cd924c081df85f570007cf645769c\n"
    },
    {
      "commit": "a34e760fa5cc3102ce1998f10816d380c37f43aa",
      "tree": "887177774ce2875a2938acc9be1cac18f74ba6be",
      "parents": [
        "5a7c634406b2acc4917009b43dcc7def2178a79b"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Tue Feb 03 12:03:15 2015 +0800"
      },
      "committer": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Tue Feb 03 18:39:12 2015 +0800"
      },
      "message": "ARM/ARM64: Dump thread offset.\n\nDump thread offset in compiler verbose log for arm32/arm64 and\noatdump for arm64.\n\nBefore patch :\n0x4e: ldr      lr, [rSELF, #604]\nAfter patch :\n0x4e: ldr      lr, [rSELF, #604]  ; pTestSuspend\n\nChange-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91\n"
    },
    {
      "commit": "5d718dcd46a0a3c65b3635449d80947f342b1d2f",
      "tree": "cd7ab915520775c8ab7ea2563c0b6badc066c494",
      "parents": [
        "e5deafe9cdd81238c3916b04301ea884c93f46b5",
        "031b00dc87cca699f02ce4206a9ecd99d59090dd"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Feb 02 15:57:09 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Feb 02 15:57:10 2015 +0000"
      },
      "message": "Merge \"ART: Fix x86 disassembler\""
    },
    {
      "commit": "31fb26054349db03b3f1627fe975ed099ade69dd",
      "tree": "1584fbca9d5099a25ca857531b846f5b05b61de9",
      "parents": [
        "28acb6feb50951645c37c077bd3897ea760ca322"
      ],
      "author": {
        "name": "Dan Albert",
        "email": "danalbert@google.com",
        "time": "Tue Sep 30 22:10:10 2014 -0700"
      },
      "committer": {
        "name": "Dan Albert",
        "email": "danalbert@google.com",
        "time": "Fri Jan 30 08:57:51 2015 -0800"
      },
      "message": "Add options for building/testing with coverage.\n\n    acov --clean\n    mm -B NATIVE_COVERAGE\u003dtrue ART_COVERAGE\u003dtrue test-art-host\n    acov --host\n\n-B is needed because you need to be sure you rebuild *all* of ART with\ncoverage.\n\nChange-Id: Ib94ef610bd1b44dc45624877710ed733051b7a50\n"
    },
    {
      "commit": "f36df544d421aa60fc4cf8a5db6356b45f97953b",
      "tree": "85c2a17e6ccdee567c0aee669a6b949a9eead1a8",
      "parents": [
        "ab7f56d9b9838811cb01773e45999e2cda4aa03a"
      ],
      "author": {
        "name": "Dan Albert",
        "email": "danalbert@google.com",
        "time": "Thu Jan 29 13:28:13 2015 -0800"
      },
      "committer": {
        "name": "Dan Albert",
        "email": "danalbert@google.com",
        "time": "Thu Jan 29 13:28:13 2015 -0800"
      },
      "message": "Remove libcxx.mk cruft.\n\nThis is on by default now. No need to leave it in the makefiles.\n\nChange-Id: I20eab7426da4bbbf8b70ffc5b9af7b97487d885d\n"
    },
    {
      "commit": "031b00dc87cca699f02ce4206a9ecd99d59090dd",
      "tree": "931769ccc85050469f5e5cb502021d8d35d5ae30",
      "parents": [
        "94fc0e7be35ab1dd42c6336071ea53dfc565faee"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Jan 26 19:30:23 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Jan 27 08:44:15 2015 -0800"
      },
      "message": "ART: Fix x86 disassembler\n\nIndex 4 in SIB is valid when given Rex.x, where it denotes r12 and\nnot the invalid rsp.\n\nBug: 19149560\nChange-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850\n"
    },
    {
      "commit": "57b34294758e9c00993913ebe43c7ee4698a5cc6",
      "tree": "981821619027686f83fbe00445299b0522f1df05",
      "parents": [
        "4945bfef00ac446d9c5458e55500229d463ab4c3"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Jan 14 15:45:59 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Jan 15 11:32:48 2015 -0800"
      },
      "message": "ART: Allow to compile interpret-only mips64 files\n\nInclude enough infrastructure to allow cross-compiling for mips64,\ninterpret-only. This includes the instruction-set-features, frame\nsize info and utils assembler.\n\nAlso add a disassembler for oatdump, and support in patchoat.\n\nNote: the runtime cannot run mips64, yet.\n\nChange-Id: Id106581fa76b478984741c62a8a03be0f370d992\n"
    },
    {
      "commit": "8d36591d93920e7b7830c3ffee3759b561f5339e",
      "tree": "3217249ce513848ed93dcec981d6ed4c13c2fc60",
      "parents": [
        "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Jan 13 11:32:32 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Jan 13 11:32:32 2015 -0800"
      },
      "message": "ART: Use jalr instead of jr for Mips\n\nUse the jalr instruction instead of jr in stubs and compiled code.\n\nChange-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b\n"
    },
    {
      "commit": "55d7c18a1d76eea6d038205ccb9f2d385247f6ac",
      "tree": "58d55810040aaadad98717c12cae6505cf92dede",
      "parents": [
        "3d5872eb090a04a9444b5621d381eec3846f47a3"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Jan 05 15:17:01 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jan 06 10:59:56 2015 +0000"
      },
      "message": "Improve Thumb disassembler for LDR/STR/PUSH/POP/BKPT.\n\nDisassemble 16-bit Thumb PUSH, POP, BKPT.\n\nClean up 32-bit load/store to handle all cases (including\npreviously unrecognized indexed load/store) in one place;\nthis also fixes LDRSH erroneously disassembled as LDRSB.\n\nRecognize more UNDEFINED instructions and other minor\ncleanup.\n\nChange-Id: Ifdd177745b70e3f774cc0469deb81191b035f51b\n"
    },
    {
      "commit": "6a0b920512b72542b3f1a3d232fba7ded45ea455",
      "tree": "9fb25c9217e0a0c671faf507e4990b3205bbeade",
      "parents": [
        "f610c0597e001cb1043aa4074afe25ae79a800e3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Dec 16 14:54:18 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Dec 16 14:54:18 2014 +0000"
      },
      "message": "Fix crash in x86 disassembler.\n\nProbably a typo from last refactoring.\n\nChange-Id: I086a87120ca0f0dfddbe803573b0e0f79cc6d945\n"
    },
    {
      "commit": "8683038c1f59bea790d8c7691e40eed7f6250e4a",
      "tree": "63f168876ecb6b8416082cbc141da1d478a66988",
      "parents": [
        "29045735a55726235e5c2c5156809cdcac61d4d7"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Dec 12 21:41:29 2014 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Dec 15 10:27:32 2014 -0800"
      },
      "message": "ART: Do not inline elf writer debug symbols\n\nUsing Clang, this pushes the frame size of the caller across our\nlimit. Thus forbid inlining. The function is only called once per\ncompile, impact is insignificant.\n\nBug: 18738594\nChange-Id: I19c3f1168a5104ab508a8dbf9f2a8c035cb97e3c\n"
    },
    {
      "commit": "e5eb7060dbacfd7c768692a8fcc4a6017d0bd1cc",
      "tree": "059f7f8b927e4e5fdbef2ed1f78c2a31c36699ab",
      "parents": [
        "d1512fed4e43bba77fb21fd1b6322c22ef7c5881"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Dec 12 18:44:19 2014 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Dec 15 08:15:57 2014 -0800"
      },
      "message": "ART: Break up x86 disassembler main function\n\nThe function leads to large stack frames with Clang. Break out\nsome parts and use four char* variables for opcode.\n\nBug: 18733806\nChange-Id: I8bf6da6c763175d7081c4231fa5d3b6809316220\n"
    },
    {
      "commit": "a262f7707330dccfb50af6345813083182b61043",
      "tree": "a8ab4e42654f47c9deea517f6c4e2020c62d5724",
      "parents": [
        "3e465bec65067ebfdf662469cf85dd82cd077bdd"
      ],
      "author": {
        "name": "Ningsheng Jian",
        "email": "ningsheng.jian@arm.com",
        "time": "Tue Nov 25 16:48:07 2014 +0800"
      },
      "committer": {
        "name": "Ningsheng Jian",
        "email": "ningsheng.jian@arm.com",
        "time": "Thu Dec 11 09:08:22 2014 +0800"
      },
      "message": "ARM: Combine multiply accumulate operations.\n\nTry to combine integer multiply and add(sub) into a MAC operation.\nFor AArch64, also try to combine long type multiply and add(sub).\n\nChange-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e\n"
    },
    {
      "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa",
      "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c",
      "parents": [
        "eea79dd779ba199658ada7264f8f96d776e53f19"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Tue Nov 25 20:05:46 2014 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Fri Nov 28 12:02:58 2014 +0000"
      },
      "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "834896de1c955c04d781d2bf8c53573f94ce8c3e",
      "tree": "7152aa7bebe9a82f7b35b3f233aacaf6e3e72ea7",
      "parents": [
        "7b5f98e0c17785ec64eb291856cd08dcd3d19ce1",
        "a37d925d405be9f589ac282869a997e73414d859"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Nov 19 21:09:12 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Nov 19 21:09:15 2014 +0000"
      },
      "message": "Merge \"Improvements to the ARM64 disassembler.\""
    },
    {
      "commit": "847c8db052fcb3c1a945a8206547c409d3eb06fc",
      "tree": "013b7081bf3805b25970dcd71ee18b79944fcab5",
      "parents": [
        "195c576fbff290d4c313b67ed24ca36f2531acc4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Nov 17 10:22:02 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Nov 17 10:22:02 2014 +0000"
      },
      "message": "Revert \"Arm64: Use the debug version of VIXL for debug builds.\"\n\nThis reverts commit 195c576fbff290d4c313b67ed24ca36f2531acc4.\n\nChange-Id: Id992a43ae346bb4c38a6c47639b02aea838d974a\n"
    },
    {
      "commit": "195c576fbff290d4c313b67ed24ca36f2531acc4",
      "tree": "0565c97102cc73fa989b6df822b9f2b3f1022a6c",
      "parents": [
        "ff5298ff1640b730ee62c90ca78fc96b7ee82ec4"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Nov 13 11:14:25 2014 +0000"
      },
      "committer": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Fri Nov 14 19:02:47 2014 +0000"
      },
      "message": "Arm64: Use the debug version of VIXL for debug builds.\n\nThis patch builds the debug version of ART against VIXL debug. In this\nway VIXL will assert misuses of the assembler and disassembler.\n\nChange-Id: Ic4654eb20e420f23b40e96a69be452dc50770c1c\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "d582fa4ea62083a7598dded5b82dc2198b3daac7",
      "tree": "c76704c266ef4687eab425612ddf3fd24f93fe8d",
      "parents": [
        "f20076ff813b8012096ff31af236d59db3c0f4e1"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Nov 05 23:46:43 2014 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Nov 13 16:17:46 2014 -0800"
      },
      "message": "Instruction set features for ARM64, MIPS and X86.\n\nAlso, refactor how feature strings are handled so they are additive or\nsubtractive.\nMake MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler\nrather than #ifdefs that wouldn\u0027t have worked in cross-compilation.\nAdd SIMD features for x86/x86-64 proposed in:\n  https://android-review.googlesource.com/#/c/112370/\n\nBug: 18056890\n\nChange-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666\n"
    },
    {
      "commit": "677c12fe1939cad5795e7c9f4738941508c4d56f",
      "tree": "362b74f16c2d73d5dd66268a206ee3b4fcbe22b6",
      "parents": [
        "abe07109e4128ea2adc26c0cb4312539bbe2913d"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Nov 07 16:58:38 2014 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Nov 07 16:58:38 2014 -0800"
      },
      "message": "Tidy x86 disassembler\n\nChange-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e\n"
    },
    {
      "commit": "277ccbd200ea43590dfc06a93ae184a765327ad0",
      "tree": "d89712e93da5fb2748989353c9ee071102cf3f33",
      "parents": [
        "ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Nov 03 21:36:10 2014 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Nov 04 18:40:08 2014 -0800"
      },
      "message": "ART: More warnings\n\nEnable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,\nand -Wunused-but-set-parameter for GCC builds.\n\nChange-Id: I81bbdd762213444673c65d85edae594a523836e5\n"
    },
    {
      "commit": "872dd8208f00c667af8d9e0fd07fdd0ada56d437",
      "tree": "2f69282f19c72ef157dad9fdc7b6c6daf8a1bf38",
      "parents": [
        "af62cf99a1a4320157e1074c1e65c5fbb0320349"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Oct 30 11:19:14 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Oct 30 11:19:14 2014 -0700"
      },
      "message": "Tidy and reduce ART library dependencies on the host.\n\nMove to shared rather than static libraries. Avoids capture of all static\nlibraries library dependencies.\n\nChange-Id: I2be96e92dad4ed1842d76b044745f2a2e15372eb\n"
    },
    {
      "commit": "a37d925d405be9f589ac282869a997e73414d859",
      "tree": "f48473337f07df6fb9f505651d653ed01b9d2eda",
      "parents": [
        "be29639a910daaa5bdb0c32be1e03477cf12babb"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Mon Oct 27 11:28:14 2014 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Oct 29 09:01:14 2014 +0000"
      },
      "message": "Improvements to the ARM64 disassembler.\n\nThis contains three changes:\n- Use register aliases in the disassembly.\n- When loading from a literal pool, show what is being loaded.\n- Disassemble using absolute addresses on ARM64.\n  This ensures that addresses disassembled are coherent with instruction\n  location addresses shown.\n\nExamples of disassembled instructions before and after the changes:\n\nBefore:\n  movz w17, #0x471f\n  ldr d9, pc+736 (addr 0x72690d50)\n\nAfter:\n  movz wip1, #0x471f\n  ldr d9, pc+736 (addr 0x72690d50) (-745.133)\n\nChange-Id: I72fdc160fac26f74126921834f17a581c26fd5d8"
    },
    {
      "commit": "2c4257be8191c5eefde744e8965fcefc80a0a97d",
      "tree": "9db3e1f1c60f2df29638ba3ce9d5d5bb8b26ca2c",
      "parents": [
        "98c271d517bc4d25fc6879b4b8e35ea93885d9e2"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Oct 24 14:20:06 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Oct 24 14:23:42 2014 -0700"
      },
      "message": "Tidy logging code not using UNIMPLEMENTED.\n\nChange-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe\n"
    },
    {
      "commit": "cf7f19135f0e273f7b0136315633c2abfc715343",
      "tree": "ffa4d9efd9c45f4b6789acc1f534bb9327052b7e",
      "parents": [
        "aea6888b056be21adf762e066c7f33b8939b8a06"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Oct 22 22:06:39 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Oct 22 22:21:57 2014 -0700"
      },
      "message": "C++11 related clean-up of DISALLOW_..\n\nMove DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations\nwith no definitions this prompts better warning messages so deal with these\nby correcting the code.\nAdd a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object.\nMake X86 assembly operand types ValueObjects to fix compilation errors.\nTidy the use of iostream and ostream.\nAvoid making cutils a dependency via mutex-inl.h for tests that link against\nlibart. Push tracing dependencies into appropriate files and mutex.cc.\nx86 32-bit host symbols size is increased for libarttest, avoid copying this\nin run-test 115 by using symlinks and remove this test\u0027s higher than normal\nulimit.\nFix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it\nreturns NULL when the heap is under construction by Runtime.\n\nChange-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b\n"
    }
  ],
  "next": "c7dd295a4e0cc1d15c0c96088e55a85389bade74"
}