)]}' { "log": [ { "commit": "30f54cc45bd338f9d9079786dae96ea13ab9f163", "tree": "542b2e8afa185ee3fdeb17fa1637579c110cc2c6", "parents": [ "4cb6347613e37c98bf40d8bb5e6583ac81f4d856", "672b9c1e95beed861a63d4a4c273114387f035a6" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jan 08 12:37:05 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 08 12:37:05 2018 +0000" }, "message": "Merge \"ARM: Fix breaking changes from recent VIXL update.\"" }, { "commit": "a556e6ba500ba54d1ca90d6a947dd962d9c287c7", "tree": "f9e747c6218ca741c7b0783a9d10dedf22dd36b3", "parents": [ "b0ddceb337f614dc2600d19b82fb4a6596aa7d4c" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Dec 13 12:09:42 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Jan 03 17:40:01 2018 +0100" }, "message": "MIPS: InstructionCodeGeneratorMIPS*::DivRemByPowerOfTwo()\n\nReplace [d]sll+[d]srl with [d]ins on R2+.\n\nChange-Id: I7587e46c47c8ce413d81a5c6c29d91e32a14d855\n" }, { "commit": "672b9c1e95beed861a63d4a4c273114387f035a6", "tree": "4bee8c0fe1794213fdd5502ad57dcb1ebfeaae7a", "parents": [ "a43a89470597a1d34a403add4f82cfc155e7bc33" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Dec 05 18:04:07 2017 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Dec 18 13:48:42 2017 +0000" }, "message": "ARM: Fix breaking changes from recent VIXL update.\n\nTest: test-art-target, test-art-host\n\nChange-Id: I31de1e2075226542b9919f6ca054fd5bf237e690\n" }, { "commit": "72aba71d00dd0c420a6ff196066e9378339d46d8", "tree": "ebe2840351820f536b11f1c0f4628205cd6c1251", "parents": [ "3b7ce4ecc6994ea73022c1c4d2df7a3f4fc7471c" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Mon Oct 30 15:47:20 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Nov 08 10:12:18 2017 +0100" }, "message": "MIPS: Add asub_s/u.df\n\nThese instructions are needed for implementing Sum-of-Abs-Differences\nvisitor.\n\nTest: mma test-art-host-gtest\nChange-Id: Ie708f30a450b0558215f59f21bb49b68c852f247\n" }, { "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92", "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7", "parents": [ "321b3ca9a36d769283c64d4bdee0798db80af524" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 01 14:35:42 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 02 10:11:02 2017 +0000" }, "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n" }, { "commit": "3309c01e55821f693e3b9cec0ef24969edf2528f", "tree": "cacb4a3775166297b1c9bb9e6236ab901ad725d4", "parents": [ "24276374dcaf95bfc52be2b8193eb4e337de62e4" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Fri Oct 13 14:34:32 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Oct 19 11:24:55 2017 +0200" }, "message": "MIPS: Introduce a few MSA instructions\n\nThese instructions are needed for SIMD reduction.\nAlso added assembler tests for each instruction.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18\n" }, { "commit": "9389ae7309180f4dccc3c34e26798ed428f0d054", "tree": "d8ff0d871506ad2559c505b92495b1f5125fc4f6", "parents": [ "350546494d6964daee2b9236820b7f85b88dfd59" ], "author": { "name": "Dan Willemsen", "email": "dwillemsen@google.com", "time": "Wed Sep 27 11:58:43 2017 -0700" }, "committer": { "name": "Dan Willemsen", "email": "dwillemsen@google.com", "time": "Wed Sep 27 15:11:33 2017 -0700" }, "message": "Simplify Android.bp files\n\nRemove clang: true, it\u0027s the default.\n\nRemove target.android.shared_libs \"libdl\", since it\u0027s already part of\nthe system_shared_libs list.\n\nRemove host_ldlibs, since -ldl and -lpthread are automatically added on\nDarwin and Linux. -lrt is automatically added on Linux.\n\nTest: mmma art\nChange-Id: I18aa6aa5b49cad31caf6820b1974057ad14a2798\n" }, { "commit": "f708c9a39240716eb3df024ec67bbcb9b3883f61", "tree": "00d78ed6994c79e08c829416fe0ea03dc145b6f0", "parents": [ "2ade881db8642f10007c1c46b5e7f073d463c2d3", "0cab65610a6a984a94ef4c3f232fe0273e78d95b" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Aug 17 14:40:46 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Aug 17 14:40:46 2017 +0000" }, "message": "Merge \"MIPS: Eliminate hard-coded offsets in branches\"" }, { "commit": "3332db8345de39eb5067d99987fcae140184672b", "tree": "411e0be297cb288b18511bef5f4cb11c52fde546", "parents": [ "73de4a8f0936bfb8b74db0465f277a2b68d16905" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Aug 11 15:10:30 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Aug 11 15:10:30 2017 -0700" }, "message": "Bunch of SIMD for x86 and x86_64\n\nRationale:\nFew instructions needed to implement SIMD reductions.\n\nTest: assembler_x86_[64_]test\nBug: 64091002\nChange-Id: I785acfc6c8c4ad4f290ddeab32da9b767f944e24\n" }, { "commit": "0cab65610a6a984a94ef4c3f232fe0273e78d95b", "tree": "669fa607f4cd9ad8eef9223bb124fb72265a06b3", "parents": [ "2e53f8f69f8c4175085e337445ec42aa045a2f7f" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jul 25 15:19:36 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Jul 30 20:09:26 2017 -0700" }, "message": "MIPS: Eliminate hard-coded offsets in branches\n\nThe bulk of the change is in the assemblers and their\ntests.\n\nThe main goal is to introduce \"bare\" branches to labels\n(as opposed to the existing bare branches with relative\noffsets, whose direct use we want to eliminate).\nThese branches\u0027 delay/forbidden slots are filled\nmanually and these branches do not promote to long (the\nbranch target must be within reach of the individual\nbranch instruction).\n\nThe secondary goal is to add more branch tests (mainly\nfor bare vs non-bare branches and a few extra) and\nrefactor and reorganize the branch test code a bit.\n\nThe third goal is to improve idiom recognition in the\ndisassembler, including branch idioms and a few others.\n\nFurther details:\n- introduce bare branches (R2 and R6) to labels, making\n R2 branches available for use on R6\n- make use of the above in the code generators\n- align beqz/bnez with their GNU assembler encoding to\n simplify and shorten the test code\n- update the CFI test because of the above\n- add trivial tests for bare and non-bare branches\n (addressing existing debt as well)\n- add MIPS32R6 tests for long beqc/beqzc/bc (debt)\n- add MIPS64R6 long beqzc test (debt)\n- group branch tests together\n- group constant/literal/address-loading tests together\n- make the disassembler recognize:\n - b/beqz/bnez (beq/bne with $zero reg)\n - nal (bltzal with $zero reg)\n - bal/bgezal (bal \u003d bgezal with $zero reg)\n - move (or with $zero reg)\n - li (ori/addiu with $zero reg)\n - dli (daddiu with $zero reg)\n- disassemble 16-bit immediate operands (in andi, ori,\n xori, li, dli) as signed or unsigned as appropriate\n- drop unused instructions (bltzl, bltzall, addi) from\n the disassembler as there are no plans to use them\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I62b74a6c00ce0651528114806ba24a59ba564a73\n" }, { "commit": "b3d79e430a4c0a447121890514cdee48e4675df4", "tree": "ebc0f5fc16d5caf009f59550407abadbc40415ff", "parents": [ "03ce1df8f9b1b8d207fc685fd084b96697a50182" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Tue Jul 25 11:20:52 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Tue Jul 25 14:27:30 2017 +0200" }, "message": "MIPS: Add maddv/msubv MSA instructions\n\nAdded maddv.df, msubv.df, fmadd.df and fmsub.df MSA instructions\nin assembler, disassembler and tests.\n\nThese instructions are needed for multiplyaccumulate support in\nART Vectorizer.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Idef7faaeed47f1fef83fa58676ce664afe24ffe8\n" }, { "commit": "8cf9cb386cd9286d67e879f1ee501ec00d72a4e1", "tree": "88e86e214b425e444760fe4e0ffeee677e1558a2", "parents": [ "914b7b6a6c9f399b26b41e9160e9871ef749e0db" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 19 09:28:38 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jul 24 16:07:10 2017 -0700" }, "message": "ART: Include cleanup\n\nLet clang-format reorder the header includes.\n\nDerived with:\n\n* .clang-format:\n BasedOnStyle: Google\n IncludeIsMainRegex: \u0027(_test|-inl)?$\u0027\n\n* Steps:\n find . -name \u0027*.cc\u0027 -o -name \u0027*.h\u0027 | xargs sed -i.bak -e \u0027s/^#include/ #include/\u0027 ; git commit -a -m \u0027ART: Include cleanup\u0027\n git-clang-format -style\u003dfile HEAD^\n manual inspection\n git commit -a --amend\n\nTest: mmma art\nChange-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02\n" }, { "commit": "43e99b099a8ca71eda14d8009fd38cb0d441b694", "tree": "627382bd12b0321c54aa7d06fa5092313b7634c3", "parents": [ "6375a04cae864416499865453fecd2b50706b3b2" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 28 10:53:58 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Jul 10 17:37:08 2017 +0200" }, "message": "MIPS: Print register names instead of register numbers in disassembler\n\nTest: ./testrunner.py --optimizing --target on CI20 and in QEMU\nTest: mma test-art-host-gtest\n\nChange-Id: I1fc375ae34ee8fd994192705c45d8f30a35dfc56\n" }, { "commit": "658263ec2fdc7758dd73c41cdcf0babcdef1e48d", "tree": "493f3cb75d9d856aaade47dd2d008756f9e488a5", "parents": [ "11d72c608e0565fabcf6b2d6c13fbc85c560a608" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 07 09:35:53 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 07 09:41:42 2017 +0200" }, "message": "MIPS64: Add min/max MSA instructions\n\nAdded min_s.df, max_s.df, min_u.df, max_u.df, fmin.df and fmax.df MSA\ninstructions in assembler, disassembler and tests.\n\nThese instructions are needed for min/max support in ART Vectorizer.\n\nTest: mma test-art-host-gtest\nChange-Id: I4e8dd18ca501ac09d938a49388e4a43116660ec9\n" }, { "commit": "5115efb3369d522ad34b919114de2797bcd81642", "tree": "2cba2a6038f13e52f8d416a91ef0021d83c03017", "parents": [ "7dd1e683ea61341323ba8b138684f4c4fbddb3ab" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed May 24 16:55:54 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed May 24 16:55:54 2017 -0700" }, "message": "ART: Fix soong defaults order\n\nDefaults are prepended in order of their appearance. Move debug\ndefaults first.\n\nBug: 31098551\nTest: m test-art-host\nChange-Id: I9a64db34d0e398d336dac080c7234cad77b719ee\n" }, { "commit": "a1633a7077781d9c64a77b27deb1707d1a56906d", "tree": "505f2560cfd247b2e1aab86d3ab96e5c399cb05d", "parents": [ "a774575ae3af3d46955f941ddd08a79caf2aaa94", "c8e93c736c149ce41be073dd24324fb08afb9ae4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue May 16 15:56:01 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 16 15:56:04 2017 +0000" }, "message": "Merge \"Min/max SIMDization support.\"" }, { "commit": "c8e93c736c149ce41be073dd24324fb08afb9ae4", "tree": "8e7154cf1bbcee8f5837ee9cb930174e2516ac03", "parents": [ "92f4672f811a4eccdc596f7c2235804abd196fde" ], "author": { "name": "Aart Bik", "email": "ajcbik@ajcbik2.mtv.corp.google.com", "time": "Wed May 10 10:49:22 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon May 15 11:44:58 2017 -0700" }, "message": "Min/max SIMDization support.\n\nRationale:\nThe more vectorized, the better!\n\nTest: test-art-target, test-art-host\n\nChange-Id: I758becca5beaa5b97fab2ab70f2e00cb53458703\n" }, { "commit": "3837011236058617292bee831708449e5100c08c", "tree": "1f9d72542f9309017433f3a1fe13a5a2dac4e000", "parents": [ "7e4f71f9014c5dc573b4dbbf7faefc4c72d5f55d" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed May 10 14:30:28 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu May 11 10:35:34 2017 +0200" }, "message": "MIPS64: Add ilvr.df MSA instructions\n\nThese instructions are needed for compressed string support\nin ART Vectorizer.\n\nTest: mma test-art-host-gtest\nChange-Id: I269473bb8bcce5aba72201380bb71860e5498d73\n" }, { "commit": "80248d7ba4e952f0e0110c036b48963080ef9470", "tree": "887cbde7b310371d8ecba019cec0b2a1000e520a", "parents": [ "6d3c61d8c6d2f96dec8345263c948fae3caa4e1a" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 20 11:55:47 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Apr 21 16:11:50 2017 +0200" }, "message": "MIPS64: Add add_a.df, ave_s/u.df and aver_s/u.df MSA instructions\n\nThese instructions are needed for implementing VecAbs and\nVecHalvingAdd visitors.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Idaec03ea32bbeaba9cb7476dd0f740aa4d9cfa70\n" }, { "commit": "7cd18fb5a7ce83d98b1bbc3c55583fc5f93dc16f", "tree": "2aaab2ad3d40d9044d02a8818991f6845190e118", "parents": [ "674bc3c984b8e24e90e5e8dda20197005dbf8300", "8939c6474a34eb6d642db8fecb8b3a5c3194e464" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Apr 04 17:59:09 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 04 17:59:14 2017 +0000" }, "message": "Merge \"SIMD pcmpgtb,w,d,q for x86/x86_64\"" }, { "commit": "8939c6474a34eb6d642db8fecb8b3a5c3194e464", "tree": "a0a2db32a5147416d796907a3977dd29e04e9328", "parents": [ "08ae45625d059891754e3c3ad63a5e6cae80b96b" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Apr 03 14:09:01 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Apr 04 09:15:45 2017 -0700" }, "message": "SIMD pcmpgtb,w,d,q for x86/x86_64\n\nRationale:\nEnables fast compare gt.\n\nTest: assembler_x86[_64]_test\nChange-Id: I0a069649480529f3fec2c2b100e2aaaa2cd79820\n" }, { "commit": "e2a239560959dafe08c499d61905b69c6f628c02", "tree": "bfc4889ebe0d83d4a6ccf6392708ff0d6c383e9e", "parents": [ "432fccc4c001fcd822f401aea1a4214b713bd896", "3f44403fb5b6c9c6176339ab5888e97d0b617746" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Apr 03 21:42:11 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 03 21:42:13 2017 +0000" }, "message": "Merge \"MIPS64: Add ldi.df MSA instruction\"" }, { "commit": "67d3fd77d1572e46f537dea2fd4ded3ecfd7c202", "tree": "168e7ddf85cbe0710266dc501dac6d7717f25cf8", "parents": [ "5b92c48f99391ae764e1699a22881f9d5cbce721" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Mar 31 15:11:53 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Mar 31 15:11:53 2017 -0700" }, "message": "SIMD pavgb,w for x86/x86_64\n\nRationale:\nBreak-out CL of ART Vectorizer.\nEnables fast halving add with rounding\n\nBug: 34083438\nTest: assembler_x86[_64]_test\nChange-Id: I09173376b803d671a6b05a33e630f45f778cea52\n" }, { "commit": "3f44403fb5b6c9c6176339ab5888e97d0b617746", "tree": "765e3d3968b48fa5236177905fa57c5b60e57653", "parents": [ "bb75449355575a4b1ae72147b80cc7b225092149" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:20 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:55 2017 +0200" }, "message": "MIPS64: Add ldi.df MSA instruction\n\nAlso fixes RepeatTemplatedRegisterImmBits template.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Ib23f8a65ba924623f8c3a2d75d4ec4491d18feb0\n" }, { "commit": "149fb784740a48d9a7ffdcaa9aabbbfcaa9acb98", "tree": "2749c1c096b8f92f00c81dea75f3784da321b472", "parents": [ "f633fb0f1b959410dbb7ce114e203aba1cfa4059" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 22 16:27:27 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 22 16:27:27 2017 -0700" }, "message": "Properly disassemble cmpeq for x86/x86_64\n\nRationale:\nBreak-out CL of ART Vectorizer.\n\nBug: 34083438\nTest: test-art-host\nChange-Id: I4027033cbe48a19c426326fc307fe4437b143d61\n" }, { "commit": "5a9e51d39ed3d1015f20b3d12b35747612cca40e", "tree": "17d4d1e616d5a516dc8187f165fc68ee97ada185", "parents": [ "8f2b925473cfdc7650cef407102957befe0c6bb5" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Mar 16 16:11:43 2017 +0000" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 17 11:17:49 2017 +0100" }, "message": "Revert \"Revert \"Introduce a number of MSA instructions for MIPS64\"\"\n\nThis reverts commit 219bf253e5158c4f3438e70864b8bf7235c1e193.\n\nFixed memory leak in assembler_mips64_test.cc.\n\nTest: mma valgrind-test-art-host-gtest-assembler_mips64_test64\n\nChange-Id: I238833fd4555623c2716432fc67eab7696f1e28e\n" }, { "commit": "219bf253e5158c4f3438e70864b8bf7235c1e193", "tree": "0ba845434b3b5679ee62b099c42ad455b4dcc37d", "parents": [ "dcabc8b740bf3066d59348ffdf21c164d2b27cb4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "message": "Revert \"Introduce a number of MSA instructions for MIPS64\"\n\nThis reverts commit dcabc8b740bf3066d59348ffdf21c164d2b27cb4.\n\n\nReason:\nFAILING TESTS\nvalgrind-test-art-host-gtest-assembler_mips64_test32\nninja: build stopped: subcommand failed.\n19:36:36 ninja failed with: exit status 1\nmake: *** [run_soong_ui] Error 1\n\nChange-Id: If658375528d2a0f34bb6b22b6565fab1d863b3f5\n" }, { "commit": "dcabc8b740bf3066d59348ffdf21c164d2b27cb4", "tree": "1b16fe71dc17f5e3fad5e1f6a865141b5d22da6b", "parents": [ "96cc0a004b5685d8a3fea3cee3105fbbff73437f" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 10 11:53:48 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Mar 14 17:21:19 2017 +0100" }, "message": "Introduce a number of MSA instructions for MIPS64\n\nAdded a number of MSA (The MIPS SIMD Architecture) instructions.\nAdded assembler tests for each instruction.\nMade necessary changes in disassembler for these instructions.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I380f02c6ae5424a96ad999037153228acb07a108\n" }, { "commit": "3c89d4234589816fb7dafb5215543f2cf023ce6c", "tree": "a9f6429ffd6625203bdba9c01520b6a5e64ac539", "parents": [ "1fed1dc7b1ea75b0465c0b2b3457718aab5a0f34" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Feb 17 11:30:23 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Feb 17 11:32:59 2017 +0000" }, "message": "x86/string compression: Use TESTB instead of TESTL in String.charAt().\n\nAnd fix disassembly of the now unused TESTL.\n\nTest: testrunner.py --host with string compression enabled.\nTest: Manual inspection of dump-oat output.\nBug: 35433135\nBug: 31040547\nChange-Id: I36c955bc1f2243954ecc315266a2f3fce5d87693\n" }, { "commit": "68555e952eea58023fa403951b1491496acf0f4b", "tree": "304d10e4d1b11698d73e0b5fb3d9aa69daccca9d", "parents": [ "5abcfe6254acce99bf25a151b19ffe5c9b50494f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 13 14:28:45 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 13 14:28:45 2017 -0800" }, "message": "Added a few integral SIMD extensions for x86/x86_64 (SSE).\n\nRationale:\nART vectorizer needs SIMD for integer operations too.\n\nTest: assembler_x86[_64]_test\nBug: 34083438\nChange-Id: Id6fec558c617d38cb643839eafcd10e59dcd6e0a\n" }, { "commit": "66e3919bc42ddca40302ce5ee32e3ade248dd2b6", "tree": "3800e8499317efc4b5bca06e483b2bcbd9da8d9d", "parents": [ "6a14c622700e088173ba909799c1e1785aeb4b34", "e36605910cb13da1440fb9d7a8293842a9209c97" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jan 03 11:13:50 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 03 11:13:51 2017 +0000" }, "message": "Merge \"MIPS64: java.lang.String.getChars\"" }, { "commit": "19f6c696bbb7a17d8ac521b316c40f9cbef32151", "tree": "6ce87f3ba9f224efc0036d3ab99e4272c48eeddb", "parents": [ "aea9ffece7eb32f3884a4ad0553e1df4d90fd9e4" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 30 19:19:55 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 13 14:07:16 2016 -0800" }, "message": "MIPS64: Improve method invocation.\n\nImprovements include:\n- support for all kinds of method loads and static/direct calls\n- 32-bit and 64-bit literals for the above and future work\n- shorter instruction sequences for recursive static/direct calls\nAlso:\n- include the MIPS64 dinsu instruction (missed earlier) and minor\n clean-up in the disassembler\n- properly prefix constant names with \u0027k\u0027 in relative patcher tests\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test64\"\n\nChange-Id: I19876fa5316b68531af7dfddfce90d2068433116\n" }, { "commit": "e36605910cb13da1440fb9d7a8293842a9209c97", "tree": "6bb2097042a3ee4f0e0b64c4e22575823ca82c11", "parents": [ "b487af4fc80ffabe0219657a9690be1316dab8e7" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 09 11:13:42 2016 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Dec 02 16:22:56 2016 -0800" }, "message": "MIPS64: java.lang.String.getChars\n\nTest: run-test --64 --optimizing 020-string\nTest: run-test --64 020-string\nTest: run-test --64 --no-prebuild --optimizing 020-string\nTest: run-test --64 --no-prebuild 020-string\nTest: run-test --64 --optimizing 082-inline-execute\nTest: run-test --64 082-inline-execute\nTest: run-test --64 --no-prebuild --optimizing 082-inline-execute\nTest: run-test --64 --no-prebuild 082-inline-execute\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTest: mma test-art-target-gtest -j2\nTest: booted MIPS64R6 emulator.\n\nNote: All tests run against MIPS64 QEMU.\n\nChange-Id: I48b9a87465f2516044a2e4f598cc5dce56b0d1c9\n" }, { "commit": "b77051ea5718fe017f2fa884b9ca4c8186c95190", "tree": "bb51782f8350be00195becabc3cd8758f15010a0", "parents": [ "d0111420a9f924fe560a97132d09ae531852fd69" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Mon Nov 21 19:46:00 2016 +0000" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Nov 25 14:16:31 2016 +0000" }, "message": "ARM: VIXL32: Fix breaking changes from recent VIXL update.\n\nTest: m test-art-host\nTest: m test-art-target\nChange-Id: I02a608bf51b889a2bfff43272a3619582bf9cf20\n" }, { "commit": "674b9ee50c812d684a27a28cf09098195f068f3d", "tree": "9b109adff71b48aa531628bf07644bccfc580fa3", "parents": [ "c6c5f6ce1c9cc44f859bbbc447478e4934be0fee" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Sep 20 14:54:15 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Oct 20 15:03:43 2016 -0700" }, "message": "MIPS32: Implement HSelect\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R2) on CI20\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: I8a8127d8d29cb5df84ed6f4fd4478f8d889e5cb7\n" }, { "commit": "8872cadb33bb1c62d3e67cb74badb1a9309a6a69", "tree": "fe575825a9fc0b0bb0127820b8fa1bda0e0fa4db", "parents": [ "a1d66b9050aeecd7e698c51155f0dbc0198a6822" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Sep 26 14:14:01 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Sep 27 09:18:14 2016 +0000" }, "message": "ARM64: Update the disassembler after the VIXL update.\n\nTest: top-level `make -j40`\n `mma -j40 test-art-target-test-optimizing dist`\n `mma -j40 test-art-host dist`\n\nChange-Id: I173976998dc8e3e466ca8502c3fdc447f9019cee\n" }, { "commit": "29b0cdeb5ef85fcf1ff33ecf09a10803b4b23441", "tree": "d8cbdbff1fb4c09c23166fef92fe0483b74ec7b8", "parents": [ "31eb450500ae9d46e1cb253defd35c8d06539d4a" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Tue Sep 06 13:01:03 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Sep 16 16:39:23 2016 +0100" }, "message": "ARM: VIXL32: Implement a disassembler.\n\nTest: m test-art-host\nTest: m test-art-target\nTest: manual comparison with the previous oatdump output\nChange-Id: I21ae26406200e455b8b036f53d585ea0b1bd11be\n" }, { "commit": "31fcbf83b81b95ddd5d1a630935b4e6e90396454", "tree": "1bc3239b8951b6e13a103fa8490e84f1dcc6599f", "parents": [ "935cf1b7a5e55a8d9aeab7e8955012849f0c1b68" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 12 16:22:43 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 12 16:32:31 2016 -0700" }, "message": "ART: Remove libart from disassembler\n\nThe disassembler now only requires the headers. Also remove liblog\ndependency.\n\nBug: 15436106\nTest: m test-art-host\nTest: m test-art-host-gtest-oatdump_test\nTest: m test-art-target-gtest-oatdump_test\nChange-Id: Iecff5b7f8ffd81c89ea81a4de8bfab77b5c103a7\n" }, { "commit": "fe6064ae8b861f1290aa793ce0de219781da6a10", "tree": "a24da585adbafc5932e4c3aab07f0e1d9a639628", "parents": [ "090a5da3a7f320b9d2aa9fa461efc11a7eb39392" ], "author": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Tue Aug 30 13:49:26 2016 -0700" }, "committer": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Thu Sep 08 11:00:53 2016 -0700" }, "message": "Convert more of art to Android.bp\n\nRelanding I1b10f140e17dd5e12a9d7f6a29d47cf61f5bf6ef, with fixes to\ncompile dalvikvm32 and dalvikvm64, and add them as dependencies of\ntests. Also fixes HOST_PREFER_32_BIT by moving the override from the\ndefaults, which are not used by everything in art, to the art_cc_binary\nmodule type.\n\nTest: rm -rf out/host; m -j HOST_PREFER_32_BIT test-art-host; m -j test-art-host\nChange-Id: I64d3eef5080e128103d052497760c3521cc253c6\n" }, { "commit": "bda1d606f2d31086874b68edd9254e3817d8049c", "tree": "db07417935fe72e99c3da60152e13f0620c7d8d7", "parents": [ "d14d515df39cd963179088b8721768f9645243aa" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 29 17:43:45 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 08 10:13:47 2016 -0700" }, "message": "ART: Detach libart-disassembler from libart\n\nSome more intrusive changes than I would have liked, as long as\nART logging is different from libbase logging.\n\nFix up some includes.\n\nBug: 15436106\nBug: 31338270\nTest: m test-art-host\nChange-Id: I9fbe4b85b2d74e079a4981f3aec9af63b163a461\n" }, { "commit": "04147efc0621ce09fb4548cc482d42da2ff4e088", "tree": "284a0e9736c69690ff33264730af8ebe6308ebed", "parents": [ "af54785797b2c2358de417780adf6bdd513f29f3" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Sep 06 11:09:41 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Sep 06 11:09:41 2016 +0100" }, "message": "Add build rules for statically linked oatdump on host.\n\nAlso extend oatdump_test to exercise oatdump(d)s.\n\nTest: ART_BUILD_HOST_STATIC\u003dtrue m test-art-host-gtest-oatdump_test\nBug: 29530992\nChange-Id: I6eb6c96f385832733d18d0400abd9974a6d8e45c\n" }, { "commit": "372f3a374681ef11f003460e14249adb7bc8313d", "tree": "b6d2bd95975a0ce1096dc2aa761f8e6b30e42b18", "parents": [ "9c07ab332b8ebbcb1586c311bfcb75e19b8a35b4" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 10:49:06 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 16:46:56 2016 -0700" }, "message": "ART: Add thread offset printing hook to disassembler\n\nTo prepare separation of disassembler from libart, add a function\nhook to the disassembler options for thread offset name printing.\n\nBug: 15436106\nChange-Id: I9e9b7e565ae923952c64026f675ac527b560f51b\n" }, { "commit": "af4e42a0d210aa3aa5d52926536b2ca5c2952934", "tree": "b64d683ba6ac11c0b7730df9a579aead2905dfff", "parents": [ "dce74be0c49e8a540affc0b5649a9cf8756b809b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Aug 08 15:11:24 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Aug 12 13:22:34 2016 +0100" }, "message": "ARM64: VIXL: Support a newer version of VIXL.\n\nPlease note that compiling VIXL with -Wshadow is a known VIXL issue.\n\nThis will be resolved in a later version of VIXL, when we can drop\nthe deprecated API for getters and setters.\n\nFor more info take a look at VIXL_DEPRECATED in the VIXL source code.\n\nChange-Id: Iea30b1a7b065f9b16a92c6cc7ebdc50ef068b348\n" }, { "commit": "2ea915326b0ff9e07f0b3ecb68b78f7d3200d200", "tree": "c7ac53f09bb71eb6da19b0a71435774637765942", "parents": [ "33699c9529add1c1ec4bb5dcb0807942709de224" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Thu Aug 11 17:04:14 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Thu Aug 11 17:04:14 2016 +0100" }, "message": "ARM64: Use libvixld when compiling for debug mode.\n\nVIXL debug mode checks are valuable to catch dangerous code that can\nlead to bugs.\n\nThis patch includes a couple of fixes for issues spotted by VIXL in debug mode.\n\nChange-Id: I388ae1ffd9256ad74d0b6ce06f79cc7927a5f28a\n" }, { "commit": "3719016185859778fa562d02140d04004c21d9a7", "tree": "30a2401e0576370bff32375fc87856739559379e", "parents": [ "3d6094531e3790b25c43e59fd6cd0b6b99d3447c", "37dd80d701fc5f55ed5a88ce2a495bf6eeb4a321" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 02 12:31:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 02 12:31:10 2016 +0000" }, "message": "Merge \"ARM: Embed 0.0 in VCMP.\"" }, { "commit": "37dd80d701fc5f55ed5a88ce2a495bf6eeb4a321", "tree": "2129c5f6fb822e0ca5c5671494c35aaadd78ef9c", "parents": [ "6e5e3b2e914cf4bdc5f17a6011fc2b1937eb9641" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 01 17:41:45 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 02 11:21:49 2016 +0100" }, "message": "ARM: Embed 0.0 in VCMP.\n\nTest: Run ART test suite on Nexus 5.\nChange-Id: I5cbbd98c4d64a4d9213e27adcae929ead5099a39\n" }, { "commit": "ba65cc4a71273904294245cb37ce70e5bce797e3", "tree": "d53a7a816ec4c8e5bdbf80729ac945787b27bf2c", "parents": [ "1a827a05afbffd5bee241f245f9aa3c40b4dbae4", "542451cc546779f5c67840e105c51205a1b0a8fd" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Aug 02 03:47:35 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 02 03:47:35 2016 +0000" }, "message": "Merge \"ART: Convert pointer size to enum\"" }, { "commit": "542451cc546779f5c67840e105c51205a1b0a8fd", "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a", "parents": [ "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 26 09:02:02 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 18:54:48 2016 -0700" }, "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n" }, { "commit": "33dd909468e377aaa8f0ec27fc4b3cb4d8481119", "tree": "fc6c11800d7fa7ace2f44d0bf863f23b54084a18", "parents": [ "e304fc28c4a7d57532498239f9b52d2d5b8974d5" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Aug 01 15:55:36 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Aug 01 16:11:10 2016 -0700" }, "message": "Fixed bug in disassembly of roundss/roundsd\n\nRationale:\nThese instructions should be marked as load, so that, using\nIntel syntax, destination (xmm0) appears at left hand side, as in\n roundss xmm0, xmm1\nand not the other way around. First I suspected a bug in the\nencoding (hence the test) and even the register allocator, but\nsince the code behaved correctly, only disassembly was really wrong.\n\nTest: disassembler_x86_test (but nothing for actual disassembly)\n\nBUG\u003d26327751\n\nChange-Id: I060ef57f4d5a64cdc04b97ae8a799d1c0d22da05\n" }, { "commit": "ecf75a6a9396475759c5f8b47cdc1929614b9542", "tree": "c2816628ca0229ca2da6dde0699eb22f48de3f65", "parents": [ "998bf2b4de04f1664a8ca0085740e266b9e7c4ff" ], "author": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Thu Jul 28 16:01:42 2016 -0700" }, "committer": { "name": "Colin Cross", "email": "ccross@android.com", "time": "Thu Jul 28 17:12:54 2016 -0700" }, "message": "ART: remove gcc cruft from the makefiles\n\nART only builds with clang now, delete all logic to determine gcc\nvs. clang, and move all LOCAL_CLANG_CFLAGS into LOCAL_CFLAGS.\n\nTest: mma, make test-art-host, make test-art-target\nChange-Id: I578615233ad3e71af18afb47bb11f3be8417216c\n" }, { "commit": "5668e58daf0f54d6cc8a6919033acc3506fc86ee", "tree": "de19460ff3c2f940ce5b0f7036a4bf756b59ed4e", "parents": [ "24670a7aac24c7a9b661220ab76b36c75f1494c5", "97c72b76cf776228196c6abd33973ef751de61ad" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 18 14:28:05 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 18 14:28:06 2016 +0000" }, "message": "Merge \"Fixes to build against new VIXL interface.\"" }, { "commit": "161c866ca742049f5c916696e1503c697be30e87", "tree": "b3e5c572c840c04e0651cd923b0188427e136f8f", "parents": [ "edec0eb18d9a45d994acec9e8e509a1dc05bd5b3", "4414822df8483d499fbac02563ebe8c7fc000563" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Jul 15 16:40:28 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 15 16:40:28 2016 +0000" }, "message": "Merge \"ART: disassembler_x86 doesn\u0027t recognize NOPs\"" }, { "commit": "97c72b76cf776228196c6abd33973ef751de61ad", "tree": "7a78a2b19b0847281f8cf69af735b30b15732fa8", "parents": [ "1fd347303275a424d114c9833f954e8e27812554" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jun 24 16:19:36 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jul 15 09:48:07 2016 +0100" }, "message": "Fixes to build against new VIXL interface.\n\n- Fix namespace usage and use of deprecated functions.\n- Link all dependants to new libvixl-arm64 target for now.\n\nChange-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509\n" }, { "commit": "194bcfea4a29db2c529de333c6a00b32608dd4e5", "tree": "83c8c87448730de7d8a0a4ac51414806ae0b9090", "parents": [ "dedde3f10d7801ad862d1ca1de89135decff6a60" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 11 15:52:00 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 12:04:19 2016 +0100" }, "message": "ARM: Shorter fast-path for read barrier field load.\n\nReduces the aosp_hammerhead-userdebug boot.oat by 2.2MiB,\ni.e. ~2.2%, in the ART_USE_READ_BARRIER\u003dtrue configuration.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on Nexus 5.\nBug: 29966877\nBug: 12687968\nChange-Id: I4454150003e12a1aa7f0cf451627dc1ee9a495ae\n" }, { "commit": "dedde3f10d7801ad862d1ca1de89135decff6a60", "tree": "da68a5a4d91875628c528be3556f5a681d53625f", "parents": [ "a14893e4a95eb4d17759173daf8ebf78fcc28086", "b5390f71940f2188da9e093d4130753bfb88e25a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 11 09:24:43 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 11 09:24:44 2016 +0000" }, "message": "Merge \"Have LOCAL_ASFLAGS honor debug/non-debug configuration.\"" }, { "commit": "b5390f71940f2188da9e093d4130753bfb88e25a", "tree": "548e378c7776cf535cbe8850a391c33553397d6a", "parents": [ "a7821bffd3aba0705144059c30ba0fef4a400e3d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 04 16:59:53 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 04 16:59:53 2016 +0100" }, "message": "Have LOCAL_ASFLAGS honor debug/non-debug configuration.\n\nWith this change the NDEBUG macro can be used in assembly\nfiles.\n\nChange-Id: I640594a20d5654de62cd4116087040b565eef0ce\nTest: ART host tests.\n" }, { "commit": "e3fb245fbdb5e91cf8a9750504df40bd629e0080", "tree": "a3882db92b7942b2edd6add3090b5c875fef2d09", "parents": [ "1fdb340de4e608a88e8683c857cad5d0da2c16de" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue May 10 16:08:05 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Jul 01 14:10:14 2016 -0700" }, "message": "MIPS32: Improve method invocation\n\nImprovements include:\n- CodeGeneratorMIPS::GenerateStaticOrDirectCall() supports:\n - MethodLoadKind::kDirectAddressWithFixup (via literals)\n - CodePtrLocation::kCallDirectWithFixup (via literals)\n - MethodLoadKind::kDexCachePcRelative\n- 32-bit literals to support the above (not ready for general-\n purpose applications yet because RA is not saved in leaf\n methods, but is clobbered on MIPS32R2 when simulating\n PC-relative addressing (MIPS32R6 is OK because it has\n PC-relative addressing with the lwpc instruction))\n- shorter instruction sequences for recursive static/direct\n calls\n\nTested:\n- test-art-host-gtest\n- test-art-target-gtest and test-art-target-run-test-optimizing on:\n - MIPS32R2 QEMU\n - CI20 board\n - MIPS32R6 (2nd arch) QEMU\n\nChange-Id: Id5b137ad32d5590487fd154c9a01d3b3e7e044ff\n" }, { "commit": "a77ceae14a7be2494874d9256327efa8c522e234", "tree": "e0f95e465187f0790617123257783fdf102b5547", "parents": [ "19c10147cd5f3270c8604d06c4a0e05cbc49e2f1", "a8aaf5a18ad42f3aea9afb3c8d383fe331798c9f" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jun 30 13:41:55 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jun 30 13:41:55 2016 +0000" }, "message": "Merge \"MIPS32: Disassemble and test movf.fmt and movt.fmt (missed earlier)\"" }, { "commit": "a8aaf5a18ad42f3aea9afb3c8d383fe331798c9f", "tree": "56c7500a4c362f56d1c8fec471c61baf810b6658", "parents": [ "12e6e9f3f1352ed58ddd41c7f31831011695b9e4" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 27 14:48:20 2016 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 30 13:41:14 2016 +0000" }, "message": "MIPS32: Disassemble and test movf.fmt and movt.fmt (missed earlier)\n\nTest: ART gtest assembler_mips_test\nChange-Id: Iafedfafe6ccd76127461d66dfa7984f196be6bd2\n" }, { "commit": "e652c122d8cc9697d368b9ceada9b377d091e4fd", "tree": "699f7f7bc88ff28d2b8f8e735ea48693aa653c95", "parents": [ "ca7399a1d7b3c92d73322adf54187fde31eee1bd" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon Jun 13 14:42:27 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jun 28 13:29:29 2016 +0000" }, "message": "ARM assembler support for VCNT and VPADDL.\n\nTest: Gtest assembler_thumb2_test.\nChange-Id: I8a0e47da746e1c67650cb68196a9f661deed7383\n" }, { "commit": "d3059e77818a058513ed92557160bdb6d5102b67", "tree": "cff82528de3dd71104d9b3fa4e1a57f2c9fc81dc", "parents": [ "b0fca360a081eff1a44c6f055c628e2dba44c003" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed May 11 10:30:47 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu May 12 10:01:08 2016 -0700" }, "message": "Fix oatdump crash on arm64/arm code.\nAlso adds 16 bit literal information.\n\nRationale:\nWhen \"run-away\" instructions are disassembled, the literal\naddresses may go out of range, causing oatdump to crash.\nThis CL guards memory access against the full memory range\nallocated to assembly instructions and data (it is possible\nbut not really necessary to refine this a bit). Out of range\narguments are now displayed as (?) to denote the issue, which\nis a lot nicer than crashing.\n\nBUG\u003d28670871\n\nChange-Id: I51e9b6a6a99162546fe31059f14278e8980451c2\n" }, { "commit": "cb55b29e466939d222b83f0593a1141221f2425c", "tree": "0f9aef9da0889961b1ce00c324e1c56487b9ef53", "parents": [ "0d399c71cb176b0a31d6d51f950c7c32a43668ef" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 21 14:52:03 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 21 15:17:34 2016 +0100" }, "message": "Thumb2: Fix disassembly of the b.w offset.\n\nBug: 28311085\nChange-Id: If729af888be65e1f24362b9c4ed79f124446024d\n" }, { "commit": "adf1eaaac71b6b440855d48154c17bfdc326904c", "tree": "ab0a07335a291f8c49a19f2ff848d625a0f958a9", "parents": [ "5827507da8efdaf4536c70dfdc54407c28e37852" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 06 19:05:19 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 06 19:08:09 2016 +0100" }, "message": "Thumb2: Show the immediate in ROR (immediate) disassembly.\n\nNow disassembled as \"mov ., ., ror #imm5\".\n\nChange-Id: Iad201662fd6aa3f87b95c7293fafe030c4bbdbf3\n" }, { "commit": "51aff3a6564303cab0b7ac82495b4e2e349c6ff3", "tree": "783344fdc2f757a8fce4ac1b565e2b2798415d2d", "parents": [ "6a329292736c3dd74e9c8cb319c2a233d07fe524" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Mar 17 17:21:45 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Mar 21 15:23:42 2016 -0700" }, "message": "MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics.\n\nChange-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf\n" }, { "commit": "07f6818ef68046d4749963b3bd59f7e93cf43fa9", "tree": "f92c036b6340bba99208ca2810f1453ed45d35d7", "parents": [ "8411aa3d88f4baf583ec4ecd62bb619cacd28acb" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 10 17:25:50 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 10 17:30:25 2016 +0000" }, "message": "ART: Do not use vixld - workaround to fix dex2oatds.\n\nThis is a quick workaround for ODR violations caused\nby linking libvixl.a compiled without VIXL_DEBUG with\nthe libartd-compiler.a compiled with VIXL_DEBUG.\n\nBug: 27588884\nChange-Id: Ib1af165f177f125f03cdd99777dff4c2912f6405\n" }, { "commit": "3acee732f9475fbfc6b046e0044b764e7ff5ac01", "tree": "3b87f8b93c427c05e7690ea8d14577ce3e9eb502", "parents": [ "34937e2ed46fa9f56d99e9f32e0bfad050e5e798" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 18 13:31:08 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Feb 10 16:12:56 2016 -0800" }, "message": "MIPS32: peek*/poke*, and String.charAt intrinsics.\n\n- byte libcore.io.Memory.peekByte(long address)\n- short libcore.io.Memory.peekShort(long address)\n- int libcore.io.Memory.peekInt(long address)\n- long libcore.io.Memory.peekLong(long address)\n- void libcore.io.Memory.pokeByte(long address, byte value)\n- void libcore.io.Memory.pokeShort(long address, short value)\n- void libcore.io.Memory.pokeInt(long address, int value)\n- void libcore.io.Memory.pokeLong(long address, long value)\n- char java.lang.String.charAt(int index)\n\nChange-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa\n" }, { "commit": "8cdbc2aef0ece0f3665966e793c075844b52b67d", "tree": "df2370a274b937f5d2a911019efd8fa42f59bdd6", "parents": [ "fc06b93dee031ec16272ec64fca92a0e639ae73e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 10 12:52:59 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 10 13:18:41 2016 +0000" }, "message": "ART/Thumb2: Disassemble SBFX/UBFX.\n\nChange-Id: I856206de81f41959f68de0653db021903dd1a210\n" }, { "commit": "3f67e692860d281858485d48a4f1f81b907f1444", "tree": "a14d3bdc1416dc3db74983d34a408a8b48cbce9c", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 15 14:35:12 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 20 20:14:00 2016 -0800" }, "message": "Implemented BitCount as an intrinsic. With unit test.\n\nRationale:\nRecognizing this important operation as an intrinsic has\nvarious advantages:\n(1) having the no-side-effects/no-throw allows for\n much more GVN/LICM/BCE.\n(2) Some architectures, like x86_64, provide direct\n support for this operation.\n\nPerformance improvements on X86_64:\nCheckersEvalBench (32-bit bitboard): 27,210KNS -\u003e 36,798KNS \u003d + 35%\nReversiEvalBench (64-bit bitboard): 52,562KNS -\u003e 89,086KNS \u003d + 69%\n\nChange-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f\n" }, { "commit": "4414822df8483d499fbac02563ebe8c7fc000563", "tree": "bb28eecb8be4603c0ce6e9cd28d93c4983689c46", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Serdjuk, Nikolay Y", "email": "nikolay.y.serdjuk@intel.com", "time": "Mon Sep 14 18:05:33 2015 +0600" }, "committer": { "name": "Nikolay Y Serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Thu Jan 21 03:33:37 2016 +0000" }, "message": "ART: disassembler_x86 doesn\u0027t recognize NOPs\n\nThere are some variations of NOPs which are possible on x86.\n\nChange-Id: I6aab3bc98682e521532cc746f3a371d9c5d98ee8\n" }, { "commit": "92d9060c0cdff7c726549a9d9494e5655404bed7", "tree": "22c1274193e7f1a3bd9872a2455c758394587dee", "parents": [ "376a6f3dbae7b71a6fc2c339ec416d3407277308" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Dec 18 18:16:36 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jan 04 20:53:44 2016 -0800" }, "message": "MIPS: Implement HRor\n\nThis also fixes differentiation between the SRL and ROTR\ninstructions in the disassembler.\n\nChange-Id: Ie19697f8d6ea8fa4e338adde3e3cf8e4a0383eae\n" }, { "commit": "5c7aed3b9844e240cf785e5885524ac133a04396", "tree": "acc868d1478f0410fda4d0f6de3c60755aa6680e", "parents": [ "1c70f18dce7705ff70147ddebf65a97f66df8d5c" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 25 19:41:54 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Dec 16 15:33:30 2015 -0800" }, "message": "MIPS32: improvements in code generation (mostly 64-bit ALU ops)\n\nSpecifically:\n- Use the delay slot in InvokeRuntime() for direct entry points\n- Use kNoOutputOverlap wherever possible\n- Improve and/or/xor/add/sub with 64-bit integer constants\n- Improve 64-bit shifts by a constant amount on R2+\n- More efficient load/store of 64-bit constants (especially, 0 \u0026 +0.0)\n\nChange-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b\n" }, { "commit": "cd7b0ee296b0462961c63e51d99c9c323e2690df", "tree": "57a9071635389e58a8912d98b99d7e114c1efcc6", "parents": [ "0bbc1727c446ee5f4cc3c28e68127164ef379594" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Dec 03 16:46:38 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 15 14:29:48 2015 -0800" }, "message": "MIPS32: Fuse long and FP compare \u0026 condition in Optimizing.\n\nThis also does a minor clean-up in the assembler and\nits test.\n\nBug: 25559148\nChange-Id: I9bad3c500b592a09013b56745f70752eb284a842\n" }, { "commit": "e384547851a9d9e5d89ae5bb4c16bfd7d93cc12e", "tree": "41ba461c62b6a89253b59117a68beae05df5006f", "parents": [ "70014c8af8d3a20c2987c308788bc86671bc39e9" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 18 12:27:15 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Nov 30 17:27:36 2015 -0800" }, "message": "MIPS32: int java.lang.*.numberOfLeadingZeros\n\n- int java.lang.Integer.numberOfLeadingZeros(int)\n- int java.lang.Long.numberOfLeadingZeros(long)\n\nChange-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58\n" }, { "commit": "7d4152f3520a3899ab57b61b884a17a2ba49a2ad", "tree": "cb57603e94688a4736798b18d157e4b325885509", "parents": [ "e033ea69bcd1f343c3cf944d78beec726faf348f" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 19 15:17:16 2015 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 19 17:26:50 2015 -0700" }, "message": "MIPS64: Disassembler support for rotate instructions.\n\nAlso, tighten the tests for recognizing the various shift commands. The\ntests, previously, would be unable to distinguish between \"shift right\nlogical\" and \"rotate right\" commands. In particular:\n\n- SRLV vs. ROTRV\n- DSRLV vs. DROTRV,\n- DSRL vs. DROTR, and\n- DSRL32 vs. DROTR32\n\nChange-Id: I7a6df8ab0d76fd3d34b1207da9915369ad84fa97\n" }, { "commit": "8c434dcc78d497e18590461700894d1c3e96013d", "tree": "6fc88cc839c0415aa90a1bbff25e93a09705d19b", "parents": [ "35ef974da353b13938fb0f3272c03070ad728431" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Aug 26 14:39:44 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Oct 06 16:34:25 2015 +0200" }, "message": "MIPS: Assemblers changes needed for optimizing compiler\n\nAlso add assembler tests for MIPS32.\n\nChange-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775\n" }, { "commit": "e295be4a95d7861f6ec179edf6565f58cad747cc", "tree": "a994a7f270e8dd81e3bb1a704c4ee5f6ea98aa7c", "parents": [ "9ea4a93674b42f213334bb83d1982db11091b96a", "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 16 04:21:39 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 16 04:21:39 2015 +0000" }, "message": "Merge \"Additional MIPS64 instructions needed by intrinsics code.\"" }, { "commit": "bcee092d7b0cbb7181d428115ad98d25ce844061", "tree": "dab00e7f7dc19b002948020a8c2cbde665203c0e", "parents": [ "b505997b2176bd29a108cb6c33d06d4ef29ba001" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "message": "Add X86 bsf and rotate instructions\n\nThese are for use in new intrinsics. Bsf (Bit Scan Forward) is used in\n{Long,Integer}NumberOfTrailingZeros and the rotates are used in\n{Long,Integer}Rotate{Left,Right}.\n\nChange-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536", "tree": "efdfc90c1cdb4b688c0cdf6c2cf2cfe7b8121d1c", "parents": [ "010c7fd437932e0132fc4b44de6274480573ff30" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Aug 14 14:56:10 2015 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Sep 10 10:59:11 2015 -0700" }, "message": "Additional MIPS64 instructions needed by intrinsics code.\n\nChange-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe\n" }, { "commit": "2a5c4681ba19411c1cb22e9a7ab446dab910af1c", "tree": "883ea0c07aad9efdb7c86960056cbefd7992b2bc", "parents": [ "228b3973b2b24783c727a55fda2b4b80375f7207" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 14 08:22:54 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 17 15:42:25 2015 -0700" }, "message": "ART: Some header cleaning around bit-utils\n\nTry to remove dependencies where they are not necessary.\n\nChange-Id: I5ff35cb17aea369bed3725b1610b50d7eb05b81e\n" }, { "commit": "8ae3ffb29489a127f2a6242c33845dac8d50e508", "tree": "cb5cc72e4a699a8ef6b044d530539c13b02604b7", "parents": [ "f67ab129d868b8355a8403a9627f96ac1e41a796" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Aug 12 21:16:41 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 12:58:40 2015 -0400" }, "message": "Add \u0027bsr\u0027 instruction to x86 and x86_64\n\nAdd support for \u0027bsr\u0027 instruction. Add tests.\n\nChange-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b9c4bbee9364a9351376fd1fec9604e7c84778d8", "tree": "2e0fb139b709cb0bb10f4a15067c9b302eeb0dce", "parents": [ "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jul 01 14:26:52 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 11:07:57 2015 -0400" }, "message": "Add rep movsw to x86 and x86_64 instructions.\n\nAdd \u0027REP MOVSW\u0027 as a supported instruction for x86 32 and 64 bit.\n\nAdded tests.\n\nChange-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "3887c468d731420e929e6ad3acf190d5431e94fc", "tree": "67dacb849e722e33e118b97714a48e467c06cbd5", "parents": [ "6a5037eb3340e4c981fd7de3ff45167ee5b7fc82" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 12 18:15:42 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 12 18:15:42 2015 +0100" }, "message": "Remove unnecessary `explicit` qualifiers on constructors.\n\nChange-Id: Id12e392ad50f66a6e2251a68662b7959315dc567\n" }, { "commit": "5e2c8d323fbab4db8a71041ff94b6baf3953bca9", "tree": "12030091e7359b656abe46f601aa5230b1dec880", "parents": [ "1f3f766d3b365d01f36b85dc19d40f754fa48533" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Thu Aug 06 14:49:28 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Aug 06 15:32:28 2015 +0100" }, "message": "Introduce arch-specific checker tests.\n\n- The \u0027.cfg\u0027 output is now created on target.\n- Arch-specific checker tests can be created by inserting a\n suffix. For example:\n /// CHECK-START-ARM64: int Main.foo(int) register (after)\n /// CHECK-DAG: \u003c\u003cArg:i\\d+\u003e\u003e ParameterValue\n\nChange-Id: I55cdb37f8e806c7ffdde6b676c8f44ac30b59051\n" }, { "commit": "611d3395e9efc0ab8dbfa4a197fa022fbd8c7204", "tree": "9a0a3b6750caae13b963b244719e03b8cfb49c44", "parents": [ "0c9c5bbdd6976c21602b92d9b455e6fe5d769fb0" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jul 10 11:42:06 2015 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Tue Aug 04 09:02:56 2015 +0100" }, "message": "ARM/ARM64: Implement numberOfLeadingZeros intrinsic.\n\nChange-Id: I4042fb7a0b75140475dcfca23e8f79d310f5333b\n" }, { "commit": "124b392d35595f5a8e31e6a9dbefcff5b3ef5760", "tree": "ee2e8c02bde328814d045c98067874ad3a302136", "parents": [ "5d2ed003020feee437683b84e4ea6b8c6a5753e0" ], "author": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Thu Jul 30 13:40:13 2015 -0700" }, "committer": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Thu Jul 30 13:58:52 2015 -0700" }, "message": "Added disassembler support for repe_cmpsw instruction in x86, x86_64\n\nAlso included support for repe_cmpsl instruction. This is a follow up to\ncommit 71311f868e2 which added support for repe_cmpsw in the x86 and\nx86_64 assemblers.\n\nChange-Id: I2beac05a57341539acf96cdf77062facd031a864\n" }, { "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907", "tree": "a0a488040883c14cc6cbec3186654137459d44ff", "parents": [ "8ec0e20347e13592539a8c0786b1db1735149800" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 22 11:57:36 2015 +0100" }, "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n" }, { "commit": "4dda3376b71209fae07f5c3c8ac3eb4b54207aa8", "tree": "0d96a327d1b3a7e09eff178a66c0b5fb946cfc85", "parents": [ "71af6f7aab7491665fe2d6beb9af4c251a99ad56" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 01 18:31:49 2015 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 19 15:43:58 2015 +0100" }, "message": "MIPS: Initial version of optimizing compiler for MIPS64R6.\n\nBug: 21555893\nChange-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf\nSigned-off-by: Alexey Frunze \u003cAlexey.Frunze@imgtec.com\u003e\nSigned-off-by: Douglas Leung \u003cdouglas.leung@imgtec.com\u003e\n" }, { "commit": "12bd7210bb2f5738e33dfa3f2f1cba2e0aab4955", "tree": "ceff4c27b7d3173da61dda12b1b05e062e82e3d9", "parents": [ "2519fc40d4ae89322d28d1ff610fe81bb90fb564" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 04 17:50:27 2015 +0100" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jun 04 11:26:19 2015 -0700" }, "message": "If heap poisoning is on, pass the relevant flag to LOCAL_ASFLAGS.\n\nThis change ensures assembly files honoring heap poisoning\n(notably used by stub_test) are compiled with\n-DART_HEAP_POISONING\u003d1 when this feature is turned on.\n\nBug: 21621105\nChange-Id: I13fe456cd2733a09bdfd3a9808cfd70513b14698\n" }, { "commit": "9bd88b0933a372e6a7b64b850868e6a7998567e2", "tree": "bcd275674c1234842b757ea8e100c4030f9ac6fe", "parents": [ "01cb410f4ad23135671d821ba36c269f8c82affa" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Apr 22 16:24:46 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri May 22 12:01:07 2015 +0100" }, "message": "ARM64: Move xSELF from x18 to x19.\n\nThis patch moves xSELF to callee saved x19 and removes support for\nETR (external thread register), previously used across native calls.\n\nChange-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "e0705f51fdc71e9670a29f8c3a47168f50724b35", "tree": "4a9a2d808441843bed332b0bdad3aec0a7aa4cee", "parents": [ "64db01714f91bf255a79c0a88813641c240c9857" ], "author": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Mon Apr 27 17:52:57 2015 +0600" }, "committer": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Wed Apr 29 12:17:35 2015 +0600" }, "message": "Fix for incorrect encode and parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F 3A 15\nwas incorrectly encoded in compiler table and incorrectly\nparsed by disassembler.\n\nChange-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164\nSigned-off-by: nikolay serdjuk \u003cnikolay.y.serdjuk@intel.com\u003e\n" }, { "commit": "2cebb24bfc3247d3e9be138a3350106737455918", "tree": "d04d27d21b3c7733d784e303f01f873bb99e7770", "parents": [ "1f02f1a7b3073b8fef07770a67fbf94afad317f0" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Apr 21 16:50:40 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 12:44:27 2015 -0700" }, "message": "Replace NULL with nullptr\n\nAlso fixed some lines that were too long, and a few other minor\ndetails.\n\nChange-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb\n" }, { "commit": "6daa9efe959b631d063eeb8d715a740c279f6c57", "tree": "099cbe401a71c3951ae9f0cfcef969c42f1c167a", "parents": [ "ee3b260e6b46982047a6c249b70bab3b077d7780", "403e0d55a3e9c18d4228d0aab31dec0c908dc73d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Apr 09 23:33:24 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 23:33:25 2015 +0000" }, "message": "Merge \"[MIPS] Refactoring code for disassembler\"" }, { "commit": "03fe9c80f514de61d52b65f6972d66b464a3d2fd", "tree": "fe4ac169af548b9720e0bdb5786328f9b2b56e88", "parents": [ "19361054a362957e152db65c9033408486c6af28", "bd4e6a828fc4aefea7d34a1bbedb81c560c60b6b" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Apr 09 16:40:40 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 16:40:40 2015 +0000" }, "message": "Merge \"Fix for incorrect parse of PEXTRW instruction\"" }, { "commit": "403e0d55a3e9c18d4228d0aab31dec0c908dc73d", "tree": "22beb87b8be836e2851bb2637446ceb47d9d4389", "parents": [ "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Apr 08 16:26:05 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 09 08:23:53 2015 +0200" }, "message": "[MIPS] Refactoring code for disassembler\n\nCode for mips64 is merged with code for mips.\n\nChange-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9\n" }, { "commit": "caff30245889729f102af87e79705893401251ef", "tree": "4793d6d6bc4adab2ad61e6876b5a24996fb365d6", "parents": [ "030d304aec321a21a4d577f3e7b4cd8e912ef901", "d2c80c419f1e16875f556de371e10257bcb59075" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 12:38:57 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 07 12:38:59 2015 +0000" }, "message": "Merge \"Fix address formatting in Mips64 disassembler.\"" }, { "commit": "030d304aec321a21a4d577f3e7b4cd8e912ef901", "tree": "540a947026809e5fc69f45d9019f4b0063f901c5", "parents": [ "47cf461b1b4125aedfef42aa5b4162f63aa8b8f3", "588e8e1359d3ef05aca27743e70d45fe57acd304" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 12:38:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 07 12:38:18 2015 +0000" }, "message": "Merge \"Build 32-bit version of the disassembler as well.\"" }, { "commit": "bd4e6a828fc4aefea7d34a1bbedb81c560c60b6b", "tree": "980f9eaa46f3368927e70c0122c9542b92e3368e", "parents": [ "a68a7cf8f3a6fef22d71a14350176115cb13857f" ], "author": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Fri Mar 27 16:32:27 2015 +0600" }, "committer": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Tue Apr 07 11:42:00 2015 +0600" }, "message": "Fix for incorrect parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F C5 has form:\nPEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and\nxmm is encoded in the R/M part of ModR/M byte. Since the order\nis opposite to the PEXTRB and PEXTRD, we have to set \u0027load\u0027 to\ntrue and \u0027store\u0027 leave as false.\n\nChange-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d\n" }, { "commit": "65b798ea10dd716c1bb3dda029f9bf255435af72", "tree": "774e9901b6917989a63f07f927c3b4d8b921a013", "parents": [ "c411c6cc327d3f2b3b4d1987b07dd442205d9454" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 09:35:22 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 14:05:07 2015 -0700" }, "message": "ART: Enable more Clang warnings\n\nChange-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c\n" }, { "commit": "d2c80c419f1e16875f556de371e10257bcb59075", "tree": "4005dceed1de90663568bee06f154521b9befba6", "parents": [ "9d231cc422b7b32d00bd43ca6993b2dd7e9989ea" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:42:26 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:45:58 2015 +0100" }, "message": "Fix address formatting in Mips64 disassembler.\n\nUse FormatInstructionPointer like all the other disassemblers.\nThis ensures that the \u0027absolute_addresses\u0027 option is honoured.\n\nChange-Id: I5580319cc4fad40e00f3fbbde25b142f7c689390\n" }, { "commit": "588e8e1359d3ef05aca27743e70d45fe57acd304", "tree": "aac3e447b0cc2ac23a05ad2d01b6aa5c51944cb7", "parents": [ "9d231cc422b7b32d00bd43ca6993b2dd7e9989ea" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:36:59 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:36:59 2015 +0100" }, "message": "Build 32-bit version of the disassembler as well.\n\nChange-Id: I22ecc2611c3b05b1031b42abdb5bf8c245220e03\n" } ], "next": "97597c9be7f4eb5263a80e7de4684dbfa1427e9a" }