)]}' { "log": [ { "commit": "8758454d380a2b0de1f4a99e9623cfac5460ccdf", "tree": "0c23241949fc3ab94c826a18ffa2185218521bd4", "parents": [ "e619f6c51d0ff99a00c63d3d092e0132522e8fc8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 12 17:47:52 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Dec 14 16:05:15 2017 +0000" }, "message": "Clean up InstanceOf/CheckCast.\n\nAvoid read barriers for boot image class InstanceOf. Boot\nimage classes are non-moveable, so comparing them against\nfrom-space and to-space reference yields the same result.\n\nChange the notion of a \"fatal\" type check slow path to mean\nthat the runtime call shall not return by normal path, i.e.\n\"fatal\" now includes certainly throwing in a try-block. This\navoids unnecessary code to restore registers and jump back.\nFor boot image classes the CheckCast comparisons do not need\nread barriers (for the same reason as for InstanceOf), so we\nshall not have any false negatives and can treat the check\u0027s\nslow paths as final in the same cases as in non-CC configs.\n\nBoot image size for aosp_taimen-userdebug in AOSP master:\n - before:\n arm boot*.oat: 37075460\n arm64 boot*.oat: 43431768\n - after:\n arm boot*.oat: 36894292 (-177KiB, -0.5%)\n arm64 boot*.oat: 43201256 (-225KiB, -0.5%)\n\nAlso remove some obsolete helpers from CodeGenerator.\n\nTest: Additional test in 603-checker-instanceof.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 12687968\nChange-Id: Ib1381084e46a10e70320dcc618f0502ad725f0b8\n" }, { "commit": "f3c52b42a035902245d00a619fed0275afb063d2", "tree": "c46dab07826be55e9ca92ab301eed586c2f307ca", "parents": [ "b360bff818ad0bf59668cd2bebaaeeaa8a3b5dfe" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 17 17:32:12 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 21 17:09:44 2017 +0000" }, "message": "Fill Class and String .bss slots in runtime.\n\nShift the responsibility for filling Class and String .bss\nslots from compiled code to runtime. This reduces the size\nof the compiled code.\n\nMake oatdump list .bss slot mappings (ArtMethod, Class and\nString) for each dex file.\n\naosp_taimen-userdebug boot image size:\n - before:\n arm boot*.oat: 36534524\n arm64 boot*.oat: 42723256\n - after:\n arm boot*.oat: 36431448 (-101KiB, -0.3%)\n arm64 boot*.oat: 42645016 (-76KiB, -0.2%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nTest: m dump-oat, manually inspect output.\nBug: 65737953\nChange-Id: I1330d070307410107e12c309d4c7f8121baba83c\n" }, { "commit": "cefd676fb79d225fcd7e8e8c0ef141d70a2f45b8", "tree": "be625fa0bc1255cbea5c5066dd878fb0b2a1c454", "parents": [ "dbc26ad5e8ded15688d20a39344c677077311279", "86083f7cd118f3d6c757191e83b4e4abaabdc5d7" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Nov 08 03:26:30 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 08 03:26:30 2017 +0000" }, "message": "Merge \"runtime: Bitstring implementation for subtype checking (4/4).\"" }, { "commit": "86083f7cd118f3d6c757191e83b4e4abaabdc5d7", "tree": "8e5b81ae0d09d41bfd90284a1b6b16b2332435e5", "parents": [ "495e783c9180c3fc033ce459ee0a783e633f7754" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Fri Oct 27 10:59:04 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue Nov 07 14:47:51 2017 -0800" }, "message": "runtime: Bitstring implementation for subtype checking (4/4).\n\nIntegrate the previous CLs into ART Runtime. Subsequent CLs to add\noptimizing compiler support.\n\nUse spare 24-bits from \"Class#status_\" field to\nimplement faster subtype checking in the runtime. Does not incur any extra memory overhead,\nand (when in compiled code) this is always as fast or faster than the original check.\n\nThe new subtype checking is O(1) of the form:\n\n src \u003c: target :\u003d\n (*src).status \u003e\u003e #imm_target_mask \u003d\u003d #imm_target_shifted\n\nBased on the original prototype CL by Zhengkai Wu:\nhttps://android-review.googlesource.com/#/c/platform/art/+/440996/\n\nTest: art/test.py -b -j32 --host\nBug: 64692057\nChange-Id: Iec3c54af529055a7f6147eebe5611d9ecd46942b\n" }, { "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92", "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7", "parents": [ "321b3ca9a36d769283c64d4bdee0798db80af524" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 01 14:35:42 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 02 10:11:02 2017 +0000" }, "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n" }, { "commit": "96b7474ebf313abdaf99e657e4ba9758e2467fb1", "tree": "175c7a007ef033c3fccc1e74da2e4424e74da336", "parents": [ "6247604714ae7fb2b64451b225cc0ecd3d4b716f", "174b2e27ebf933b80f4e8b64b4b024ab4306aaac" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 20 10:31:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 20 10:31:25 2017 +0000" }, "message": "Merge \"Use ScopedArenaAllocator for code generation.\"" }, { "commit": "61b922847403ac0e74b6477114c81a28ac2e01a0", "tree": "02674602fb2592f758f51389b3c7b276ab4df3ee", "parents": [ "6783118d2ad9d759f0617b1219a9e29a10a569f7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 11 13:23:17 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 18 15:52:51 2017 +0100" }, "message": "ART: Introduce Uint8 loads in compiled code.\n\nSome vectorization patterns are not recognized anymore.\nThis shall be fixed later.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --target --optimizing on Nexus 5X\nTest: Nexus 5X boots.\nBug: 23964345\nBug: 67935418\nChange-Id: I587a328d4799529949c86fa8045c6df21e3a8617\n" }, { "commit": "174b2e27ebf933b80f4e8b64b4b024ab4306aaac", "tree": "968cdd8d7fd68571115db77cc288807c3b257911", "parents": [ "6783118d2ad9d759f0617b1219a9e29a10a569f7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 12 13:34:49 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 17 11:12:08 2017 +0100" }, "message": "Use ScopedArenaAllocator for code generation.\n\nReuse the memory previously allocated on the ArenaStack by\noptimization passes.\n\nThis CL handles only the architecture-independent codegen\nand slow paths, architecture-dependent codegen allocations\nshall be moved to the ScopedArenaAllocator in a follow-up.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n BatteryStats.dumpCheckinLocked() : 19.6MiB -\u003e 18.5MiB (-1189KiB)\n BatteryStats.dumpLocked(): 39.3MiB -\u003e 37.0MiB (-2379KiB)\n\nAlso move definitions of functions that use bit_vector-inl.h\nfrom bit_vector.h also to bit_vector-inl.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 64312607\nChange-Id: I84688c3a5a95bf90f56bd3a150bc31fedc95f29c\n" }, { "commit": "bea75ff0835324076fed6ff5d443b9e02c65d223", "tree": "61ae2e8fe552938fcae1e277f51823ba2a4f6e74", "parents": [ "567563a9c6ccc06c2c9889d1c3c4feaa3c2b2dab" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 11 20:39:54 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 12 10:58:02 2017 +0100" }, "message": "Fix using LiveIntervals beyond their lifetime.\n\nFixes a bug introduced by\n https://android-review.googlesource.com/504041\n\nTest: test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 64312607\nChange-Id: I7fd2d55c2a657f736eaed7c94c41d1237ae2ec0b\n" }, { "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1", "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07", "parents": [ "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 14:49:14 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 06 17:53:50 2017 +0100" }, "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n" }, { "commit": "d5d2f2ce627aa0f6920d7ae05197abd1a396e035", "tree": "e8e780780c832e3614a22438a23fb60ee4960ca3", "parents": [ "efac0df8c738764823c637deeca1f3be33912064" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 26 12:37:26 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 10:40:51 2017 +0100" }, "message": "ART: Introduce Uint8 compiler data type.\n\nThis CL adds all the necessary codegen for the Uint8 type\nbut does not add code transformations that use that code.\nVectorization codegens are modified to use Uint8 as the\npacked type when appropriate. The side effects are now\ndisconnected from the instruction\u0027s type after the graph has\nbeen built to allow changing HArrayGet/H*FieldGet/HVecLoad\nto use a type different from the underlying field or array.\n\nNote: HArrayGet for String.charAt() is modified to have\nno side effects whatsoever; Strings are immutable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --target --optimizing on Nexus 6P\nTest: Nexus 6P boots.\nBug: 23964345\nChange-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0\n" }, { "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32", "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af", "parents": [ "e1e347dace0ded83774999bb26c37527dcdb1d5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 22:50:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 25 15:45:01 2017 +0100" }, "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n" }, { "commit": "d8dbc8da0e5cc6b5c2176ce2d3877e6194d72c0c", "tree": "af6e9fb02471d75ebdea46190a0aa3e9dbdb892d", "parents": [ "93780a60090356921b844dbefdc13442c9f18b52" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 13:37:47 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 15:55:10 2017 +0100" }, "message": "Refactor compiled_method.h .\n\nMove LinkerPatch to compiler/linker/linker_patch.h .\nMove SrcMapElem to compiler/debug/src_map_elem.h .\nIntroduce compiled_method-inl.h to reduce the number\nof `#include`s in compiled_method.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: Id211cdf94a63ad265bf4709f1a5e06dffbe30f64\n" }, { "commit": "09659c22dc2f2c85a0ade965d1fc5160944b8692", "tree": "66fd5729395d27569c4d9d255a5ce9b44cb000bf", "parents": [ "4d159807a4854caa6396b708a38bbd6fa49d736f" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 18 18:23:32 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 19 10:26:51 2017 -0700" }, "message": "ART: Remove heap poisoning from globals.h\n\nRemove mostly-unused include and move it to its users.\n\nTest: m\nChange-Id: Ibb40f919db64a490290c6e18cf1123aaf44199fc\n" }, { "commit": "fc8b422c286501346b5b797420fb616aaa5e952a", "tree": "61c857a895cdad9ce387a899f92824701259df32", "parents": [ "7090dfe84f78b1928fcbdfd664d0dd9ea52633ff" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Sun Sep 17 13:44:24 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Sep 18 10:57:06 2017 -0700" }, "message": "Clean up AtomicDexRefMap\n\nMake ClassReference, TypeReference, and MethodReference extend\nDexFileReference. This enables using all of these types as the key\nfor AtomicDexRefMap.\n\nTest: test-art-host\nBug: 63851220\nBug: 63756964\n\nChange-Id: Ida3c94cadb53272cb5057e5cebc5971c1ab4d366\n" }, { "commit": "94ec2db21332ee1dcdbbf254b99a9a999a304fe0", "tree": "6ced7e596731b61f95a3693f336527f55ea3cf3a", "parents": [ "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 06 17:21:03 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 11 15:12:51 2017 +0100" }, "message": "Use mmapped boot image class table for PIC app HLoadClass.\n\nImplement new HLoadClass load kind for boot image classes\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image ClassTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image classes compared to the kBssEntry\nas we can completely avoid the slow path and stack map\nunless we need to do the class initialization check.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20312800\n - after: 19775352 (-525KiB)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I13adb19a1fa7d095a72a41f09daa6101876e77a8\n" }, { "commit": "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63", "tree": "f92b309ddc43c2254b6067346a653170fbbf7316", "parents": [ "0f3c7003e08a42a4ed8c9f8dfffb1bee1118de59" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 25 13:26:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 07 17:52:35 2017 +0100" }, "message": "Use mmapped boot image intern table for PIC app HLoadString.\n\nImplement new HLoadString load kind for boot image strings\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image InternTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image strings compared to the kBssEntry\nas we can completely avoid the slow path and stack map.\n\nWe separate the InternedStrings and ClassTable sections of\nthe boot image (.art) file from the rest, aligning the\nstart of the InternedStrings section to a page boundary.\nThis may actually increase the size of the boot image file\nby a page but it also allows mprotecting() these tables as\nread-only. The ClassTable section is included in\nanticipation of a similar load kind for HLoadClass.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20862776\n - after: 20308512 (-541KiB)\nNote that 92KiB savings could have been achieved by simply\navoiding the read barrier, similar to the HLoadClass flag\nIsInBootImage(). Such flag is now unnecessary.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I5f2bf1fc0bb36a8483244317cfdfa69e192ef6c5\n" }, { "commit": "2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40", "tree": "4d5fb728acd7f98f8949c84364375a804ff0ba63", "parents": [ "461ec567f16039374dff35e2f3b808986c100249" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jun 06 16:09:59 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Aug 10 18:17:47 2017 +0100" }, "message": "Instrument ARM64 generated code to check the Marking Register.\n\nGenerate run-time code in the Optimizing compiler checking that\nthe Marking Register\u0027s value matches `self.tls32_.is.gc_marking`\nin debug mode (on target; and on host with JIT, or with AOT when\ncompiling the core image). If a check fails, abort.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test with libartd.\nBug: 37707231\nChange-Id: Ie9b322b22b3d26654a06821e1db71dbda3c43061\n" }, { "commit": "8cf9cb386cd9286d67e879f1ee501ec00d72a4e1", "tree": "88e86e214b425e444760fe4e0ffeee677e1558a2", "parents": [ "914b7b6a6c9f399b26b41e9160e9871ef749e0db" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 19 09:28:38 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jul 24 16:07:10 2017 -0700" }, "message": "ART: Include cleanup\n\nLet clang-format reorder the header includes.\n\nDerived with:\n\n* .clang-format:\n BasedOnStyle: Google\n IncludeIsMainRegex: \u0027(_test|-inl)?$\u0027\n\n* Steps:\n find . -name \u0027*.cc\u0027 -o -name \u0027*.h\u0027 | xargs sed -i.bak -e \u0027s/^#include/ #include/\u0027 ; git commit -a -m \u0027ART: Include cleanup\u0027\n git-clang-format -style\u003dfile HEAD^\n manual inspection\n git commit -a --amend\n\nTest: mmma art\nChange-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02\n" }, { "commit": "97c46466aea25ab63a99b3d1afc558f0d9f55abb", "tree": "afd225f51d28a77329bc2590a025400e088f260c", "parents": [ "00cca3a275562d110a8b35094b9b12fac37f67ab" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu May 11 14:04:03 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 11 17:43:27 2017 +0100" }, "message": "Introduce a Marking Register in ARM64 code generation.\n\nWhen generating code for ARM64, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register X20,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test\nBug: 37707231\nChange-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b\n" }, { "commit": "6fda42718a348cfb758d8714e223cab7e855765b", "tree": "d6f0f4d0c1ca2eec26a56e2aadaf00d3205b70a0", "parents": [ "a0e63dfbfe2f2513a709e94b8a1ac17418396fdf" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 26 09:12:45 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 26 10:59:17 2017 +0100" }, "message": "Fix braino when handling branches fallthrough in arm backend.\n\nbug: 62210114\nTest: 657-branches\nChange-Id: I753a9a57e404c792cd4375ea66c91839684bdee2\n" }, { "commit": "5678db5b3a0275d04bc610236f89fac9f76b5b1e", "tree": "efc4ffe5d59a0c6c5f4c15a886459962d24de4aa", "parents": [ "83b140474aa1759739c8ee4464bf226c4fa0f6d7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jun 08 14:11:18 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jun 08 14:11:18 2017 -0700" }, "message": "ART: Refactor bit_utils and stl_util\n\nMove iterator code from bit_utils.h into bit_utils_iterator.h. Move\nIdentity into stl_util_identity.h. Remove now unnecessary includes,\nand fix up transitive users.\n\nTest: m\nChange-Id: Id1ce9cda66827c5d00584f39ed310b6b37629906\n" }, { "commit": "0eb882bfc5d260e8014c26adfda11602065aa5d8", "tree": "e66dbebfb1e9a254c20954a2f2f98541aebfd5af", "parents": [ "b5f5d746ac3f2c3088292395603cb1470e7749d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 15 13:39:18 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 15:39:24 2017 +0100" }, "message": "Use ArtMethod* .bss entries for HInvokeStaticOrDirect.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug.\nBug: 30627598\nChange-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f\n" }, { "commit": "3c8a91250b3e4e87548ec16bf1ab1ea46dbb84a4", "tree": "b5da100b358d1335eab403372e4f616c5c2d607c", "parents": [ "0a87f31513e5f9da27856af054d2241452898b22", "e7197bf7d58c705a048e13e241d7ca320502cd40" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 10:38:10 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 07 10:38:11 2017 +0000" }, "message": "Merge \"Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\"" }, { "commit": "e7197bf7d58c705a048e13e241d7ca320502cd40", "tree": "496032b40145660b40002b9d5b7a78f1c2eeb44f", "parents": [ "4ee8e291a7d5b7b98f35f495eb97705836910871" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 17:00:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 06 15:26:42 2017 +0100" }, "message": "Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\n\nIn preparation for replacing the dex cache method array\nwith a hash-based array, get rid of one unnecessary use.\nThis method load kind is currently used only on mips for\nirreducible loops and OSR, so this should have no impact\non x86/x86-64/arm/arm64.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Repeat the above tests with manually changing\n kDexCachePcRelative to kRuntimeCall in sharpening.cc.\n (Ignore failures in 552-checker-sharpening.)\nBug: 30627598\nChange-Id: Ifce42645f2dcc350bbb88c2f4642e88fc5f98152\n" }, { "commit": "ab6393400f0dd213d335092c6e83f6a8743f00c2", "tree": "43f35b71321e7b96af7ad5ddc557638e365d2f06", "parents": [ "2c97600c1107931825bf9f7f25517e89b7210ab4", "d254f5c0d7b43397e8b8885a56ec4d36e9b61602" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 05 12:11:07 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jun 05 12:11:09 2017 +0000" }, "message": "Merge \"Revert \"ART: Reference.getReferent intrinsic for arm and arm64\"\"" }, { "commit": "d254f5c0d7b43397e8b8885a56ec4d36e9b61602", "tree": "ef645025a42f88a2c9eb0ab9483ff519886f0a4c", "parents": [ "cff1b21b3e19c5d3a2d726fdb60dacd7de2a6f0d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 15:18:36 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 16:24:33 2017 +0100" }, "message": "Revert \"ART: Reference.getReferent intrinsic for arm and arm64\"\n\nReverting because GenerateCalleeMethodStaticOrDirectCall()\nprevents replacing kDexCacheViaMethod with kRuntimeCall\nwhere we would not retrieve the target method at all and\nleave the runtime to retrieve and call it just like for\nunresolved methods.\n\nThe intrinsic should be re-implemented by loading the\nflags through HLoadClass.\n\nNote that the intrinsic was unimplemented for CC and a bit\nbroken for non-CC, using LDR instead of LDRB for loading\nthe flags.\n\nTest: Rely on TreeHugger.\nBug: 32535355\nBug: 30627598\n\nThis reverts commit d8c052ac0aa3382c4807add33afa32580ffeecbb.\n\nChange-Id: I81fd14dac60c94ac543e336f4f3c888259fc8bd7\n" }, { "commit": "847e6ce98b4b822fd94c631975763845978ebaa3", "tree": "760e26dea1597d8219d8c515317d978b0213cdc1", "parents": [ "cff1b21b3e19c5d3a2d726fdb60dacd7de2a6f0d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 13:55:07 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 14:03:28 2017 +0100" }, "message": "Rename kDexCacheViaMethod to kRuntimeCall for HLoadClass/String.\n\nThe old name does not reflect the actual code anymore.\n\nTest: testrunner.py --host\nChange-Id: I2e13cf727bba9d901c4d3fc821bb526d38a775b8\n" }, { "commit": "d49012909625c3bf87bf51138fe79315ce1b1bdc", "tree": "349ef2cdcb7255d042244046601bd0fd5eb3a092", "parents": [ "726e1793d3f54470705e5b84e7860074e029b0ed" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue May 30 18:41:34 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue May 30 20:44:33 2017 -0700" }, "message": "ART: Clean up heap headers\n\nUse more forward declarations for accounting structures and spaces.\nFactor out structs to reduce header surface. Remove heap include where\nunnecessary. Fix up transitive users. Move some debug-only code out\nof line.\n\nTest: m test-art-host\nChange-Id: I16db4aaa803f39e155ce6e1b0778b7e393dcbb17\n" }, { "commit": "6597946d29be9108e2cc51223553d3db9290a3d9", "tree": "cea6647a45cc59fa1423751179e647124f269990", "parents": [ "a654e0378a8d0bb149362399917e4da2959e6991" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 19 17:25:12 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 22 18:35:05 2017 +0100" }, "message": "Use PC-relative pointer to boot image methods.\n\nIn preparation for adding ArtMethod entries to the .bss\nsection, add direct PC-relative pointers to methods so that\nthe number of needed .bss entries for boot image is small.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target on Nexus 6P\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug\nBug: 30627598\nChange-Id: Ia89f5f9975b741ddac2816e1570077ba4b4c020f\n" }, { "commit": "764d454d1d51448deb81f6e8d2d7d317c7f4d1b4", "tree": "029f9e65cfe7e953df55b7af45e099924ffdbbac", "parents": [ "7974468d32b817be1d49dfcf513605f646c481bc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 10:31:41 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 15:08:55 2017 +0100" }, "message": "Remove LoadString/Class kind kBootImageLinkTimeAddress.\n\nWe no longer support non-PIC boot image compilation.\n\nAlso clean up some obsolete code for method patches\nand make JIT correctly report itself as non-PIC.\n\nTest: testrunner.py --host\nTest: testrunner.py --target\nBug: 33192586\nChange-Id: I593289c5c1b0e88b82b86a933038be97bbb15ad2\n" }, { "commit": "de6fc4a429b69f074dc6d28b52197b425aacd78c", "tree": "879e5eacda2af3bad1aa9dc81ea08922c6c26cc8", "parents": [ "99a77162e9dc351da14bb7819a2718395d7277ed", "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu May 11 11:59:40 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 11 11:59:42 2017 +0000" }, "message": "Merge \"ARM64: Share address computation across SIMD LDRs/STRs.\"" }, { "commit": "7d157fcaaae137cc98dbfb872aa1bdc0105a898f", "tree": "2b7d8affda23908e5bfbfaad446079db2ef1ee09", "parents": [ "58d7ddc678e5bcd2364c24c4bdc8a3cfbcfc5358" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 10 16:29:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 11 11:14:54 2017 +0100" }, "message": "Clean up some uses of \"auto\".\n\nMake actual types more explicit, either by replacing \"auto\"\nwith actual type or by assigning std::pair\u003c\u003e elements of\nan \"auto\" variable to typed variables. Avoid binding const\nreferences to temporaries. Avoid copying a container.\n\nTest: m test-art-host-gtest\nChange-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603\n" }, { "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0", "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788", "parents": [ "7113885fcd983b33ee1e350865d21517d6297843" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Apr 27 16:50:47 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu May 11 10:06:04 2017 +0100" }, "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n for (i...) {\n a[i] \u003d a[i] + 5;\n b[i] \u003d b[i] + c[i];\n }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n" }, { "commit": "92f4672f811a4eccdc596f7c2235804abd196fde", "tree": "03449148ef022c9c3afc50bc960f2851e0098f97", "parents": [ "5528d1c7cf686d2edea51ff12881e495c2124f09", "952b23505e2512c9327e6d20c8304493bf8fcf7c" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed May 10 17:24:56 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 10 17:24:58 2017 +0000" }, "message": "Merge \"Improve the documentation of an ARM64 parallel move resolver corner case.\"" }, { "commit": "270970e660d3c99e62a88b18144d159dd8699c55", "tree": "910248487abab475a9109925a9089fedd08b45c1", "parents": [ "201c81947f23b3f43c2ff78d9c1078dd53157fe5", "88abba2b0cb0151d89e16da3e64025878dc2f142" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed May 10 14:04:18 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 10 14:04:19 2017 +0000" }, "message": "Merge \"ARM/AOT: Allow 16-bit LDR for Baker read barrier loads.\"" }, { "commit": "ddc38fe3e5618e3922ecc445193dacb2f39ef736", "tree": "090cf77abda6a5755371673966ceea83f858048c", "parents": [ "45f9865cc974d344c9a859508c8ec8ce101f4c52", "4e92c3ce7ef354620a785553bbada554fca83a67" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 10 10:55:45 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 10 10:55:47 2017 +0000" }, "message": "Merge \"Add runtime reasons for deopt.\"" }, { "commit": "4e92c3ce7ef354620a785553bbada554fca83a67", "tree": "42029deff4d3ba7f89b5fdbf79ff410da575f431", "parents": [ "549844e9ccf432d1396b19af890eedb602b8ba04" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 08 09:34:26 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 10 09:27:33 2017 +0100" }, "message": "Add runtime reasons for deopt.\n\nCurrently to help investigate. Also:\n1) Log when deoptimization happens (which method and what reason)\n2) Trace when deoptimization happens (to make it visible in systrace)\n\nbug:37655083\nTest: test-art-host test-art-target\nChange-Id: I0c2d87b40db09e8e475cf97a7c784a034c585e97\n" }, { "commit": "88abba2b0cb0151d89e16da3e64025878dc2f142", "tree": "231e5551a1b8d3c8bf162c9d0f30916b36ba2742", "parents": [ "b9c3a99096c746b09af611e55e11b86600374011" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 03 17:09:25 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 09 15:43:34 2017 +0100" }, "message": "ARM/AOT: Allow 16-bit LDR for Baker read barrier loads.\n\nTest: m test-art-target-gtest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target on Nexus 6P with heap poisoning enabled.\nTest: Repeat the above tests with ART_USE_OLD_ARM_BACKEND\u003dtrue.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: I458f2ec5fe9abead4db06c7595d992945096fb68\n" }, { "commit": "93029177d766269e2685cf60625f61e38820e78d", "tree": "744e11e81a301a59c2be15adf3bc7fe4190ccdd5", "parents": [ "91f956c925f015b8cd355e8ec2a697a4ba69f7ab", "ff48700df9da9aa0c6a8c1f65c9d862f936e1a89" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon May 08 08:58:16 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 08 08:58:18 2017 +0000" }, "message": "Merge \"Improve the implementation of UnsafeCASObject with Baker read barriers.\"" }, { "commit": "ff48700df9da9aa0c6a8c1f65c9d862f936e1a89", "tree": "932dd5749a82d9477d24200db6d747d6008a0a5d", "parents": [ "15cb9753075bcaa5b91a6497a2d35e8bd98af1f0" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 07 16:50:01 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri May 05 16:08:50 2017 +0100" }, "message": "Improve the implementation of UnsafeCASObject with Baker read barriers.\n\nOn ARM and ARM64, avoid loading the reference altogether when the\nGC is not marking.\n\nAlso, extract the code logic for updating a reference field from\nGenerateReferenceLoadWithBakerReadBarrier routines and move it to\nnew routines (UpdateReferenceFieldWithBakerReadBarrier), to make\nthe implementation more legible.\n\nTest: Run ART target tests in Baker read barrier configuration.\nBug: 29516974\nChange-Id: I11c53f0607e997cd02ec7911725e98ef3dc97d90\n" }, { "commit": "952b23505e2512c9327e6d20c8304493bf8fcf7c", "tree": "ff82866fef9b738a3d90df30fd31c0fdafb8c4de", "parents": [ "15cb9753075bcaa5b91a6497a2d35e8bd98af1f0" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed May 03 19:49:14 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed May 03 19:52:06 2017 +0100" }, "message": "Improve the documentation of an ARM64 parallel move resolver corner case.\n\nTest: m test-art-host-gtest-codegen_test\nBug: 34760542\nBug: 34834461\nChange-Id: I7e716c4b665ed51af9908042f88fb2e4bcefb849\n" }, { "commit": "d01745ef88bfd25df574a885d90a1a7785db5f5b", "tree": "058eb1593dbb0fe8a8e26b901909bec8aa01d474", "parents": [ "a57c334075b193de9690fff97acf6c1b1d1283fc" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Wed Apr 05 16:40:31 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue May 02 09:45:45 2017 -0700" }, "message": "optimizing: constructor fence redundancy elimination - remove dmb after LSE\n\nPart one of a few upcoming CLs to optimize constructor fences.\n\nThis improves load-store-elimination; all singleton objects that are not\nreturned will have their associated constructor fence removed.\n\nIf the allocation is removed, so is the fence. Even if allocation is not\nremoved, fences can sometimes be removed.\n\nThis change is enabled by tracking the \"this\" object associated with the\nconstructor fence as an input. Fence inputs are considered weak; they do not keep\nthe \"this\" object alive; if the instructions for \"this\" are all deleted,\nthe fence can also be deleted.\n\nBug: 36656456\nTest: art/test.py --host \u0026\u0026 art/test.py --target\nChange-Id: I05659ab07e20d6e2ecd4be051b722726776f4ab1\n" }, { "commit": "66d691de219e840b3f84385d8bd1b7001562b0e5", "tree": "4034e867246db26acaa1a36b89b823ce5d0f1a58", "parents": [ "38870a8a2717ccf1bcd3faddc53b1999985bb29f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Apr 07 17:53:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 25 18:29:33 2017 +0100" }, "message": "ARM64: Link-time generated thunks for ArrayGet Baker CC read barrier.\n\nTest: Added a test to relative_patcher_arm64\nTest: m test-art-target-gtest on Nexus 6P.\nTest: Nexus 6P boots.\nTest: testrunner.py --target on Nexus 6P.\nTest: Nexus 6P boots with heap poisoning.\nTest: testrunner.py --target on Nexus 6P with heap poisoning.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: Id0f23089c55cbb53b84305c11bb4b03718561ade\n" }, { "commit": "d1ef87339c5af782652678d5849d1dfab14d79ce", "tree": "8b8b936ce58043248b2b58497e7b210c49a704b1", "parents": [ "1cae72e6cfc0b4cd4ad20467dfea243139296998" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 18 13:55:13 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 19 10:31:50 2017 +0100" }, "message": "ARM64: Heap poisoning for link-time Baker CC read barrier thunks.\n\nAnd fix running out of scratch registers for HArraySet\nwith large constant index and a reference to poison.\n\nTest: Nexus 6P boots with heap poisoning enabled.\nTest: testrunner.py --target with heap poisoning enabled on Nexus 6P.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: Ifb38f4a0e23a2963468772f34f294febfc340b8c\n" }, { "commit": "dda7360caf19d44cfef5307e8a6ec4d7cba6b474", "tree": "9f9a7f0c7197b72c9eca9665efae0d4fe17d9268", "parents": [ "27fb1dc467effbd8df43e6207743fdb7bcee4044" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Apr 17 12:50:45 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Apr 17 12:50:45 2017 -0700" }, "message": "Disable read barrier thunks for heap poisoning\n\nLogic to unpoison is not yet implemented, this causes SIGSEGVs in\nvarious places.\n\nBug: 29516974\nBug: 30126666\nBug: 36141117\n\nTest: ./test/testrunner/testrunner.py -j4 --optimizing --debuggable --ndebuggable --target --verbose\nChange-Id: I8317a142d07af36090d5f05ce46100dfa07c17e7\n" }, { "commit": "7b331261c6bdb6316a649ab591813f4dd1a5892f", "tree": "22b60227265c73903428ea55cde3123ea992ac4e", "parents": [ "b1a52116a1ca418dcccad2ca2acd6cb36f8ca0e7", "f4f2daafb38c9c07ea74044a0fb89a2a19288b7a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 13 12:54:22 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 13 12:54:23 2017 +0000" }, "message": "Merge \"ARM64: Use link-time generated thunks for Baker CC read barrier.\"" }, { "commit": "f4f2daafb38c9c07ea74044a0fb89a2a19288b7a", "tree": "13fd63a65c12e60074bc2bc1e693fbb3b788ed8e", "parents": [ "26c25d5da32fe1bdd94dd1404197c14994ecab60" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Mar 20 18:26:59 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 12 17:02:06 2017 +0100" }, "message": "ARM64: Use link-time generated thunks for Baker CC read barrier.\n\nRemaining work for follow-up CLs:\n - array loads,\n - volatile field loads,\n - use implicit null check in field thunk.\n\nTest: Added tests to relative_patcher_arm64\nTest: New run-test 160-read-barrier-stress\nTest: m test-art-target-gtest on Nexus 6P.\nTest: testrunner.py --target on Nexus 6P.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: Id68ff171c55a3f1bf1ac1b657f480531aa7b3710\n" }, { "commit": "d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331", "tree": "2890740d9cab3eee2be223666f528c6707b89f90", "parents": [ "903b8169074c01590ab3f5ad9190d9c7e3fe795b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 03 18:47:32 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Apr 10 11:43:33 2017 +0100" }, "message": "ARM64: Support 128-bit registers for SIMD.\n\nTest: test-art-host, test-art-target\n\nChange-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa\n" }, { "commit": "7957d9500ca53b78acb1eba754416535d4418a89", "tree": "518792ef3c5556686d7b075dbc4f2e3dc8af8632", "parents": [ "8309d9b173b205bb9530dbd94e48731c20b8e4f4" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Apr 04 15:44:09 2017 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Apr 06 16:38:32 2017 +0100" }, "message": "ARM64: Saves 128-bit regs state along SuspendCheckSlowPath.\n\nWe need to save 128 bits of data (default ABI of ART runtime\nonly saves 64 bits). Note that this is *only* done for Q-registers\nthat are live, so overhead is not too big.\n\nTest: test-art-target, test-art-host.\nChange-Id: I1f018a708c316f9d426db13b2e3b3071aa4c999b\n" }, { "commit": "7b7f8b4e07b57962cacbd9a05d9f5fad4f0a91aa", "tree": "c3bb9f99befcac1b1bbcdc8718a815eef8d410cf", "parents": [ "fbffc6706a826ef3a6f0839cb75393a34f0c2ef1", "c70d1d99654b25491997589b6ecfa431679ea2e3" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Mar 28 17:47:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 28 17:47:25 2017 +0000" }, "message": "Merge \"Fix arm64 and x86_64 code generator assertion\"" }, { "commit": "c70d1d99654b25491997589b6ecfa431679ea2e3", "tree": "a6cac410c977ba669b666853b799075eabaab98a", "parents": [ "ae60e48f1077a2221549c733623c25f79733caf0" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Mar 27 18:10:04 2017 -0700" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Mar 27 18:10:04 2017 -0700" }, "message": "Fix arm64 and x86_64 code generator assertion\n\nTest: m test-art-host\nChange-Id: I273d2dab079b60707a8ffb72227cac5788d1a3bc\n" }, { "commit": "d9911eeca13f609c885e0f6a5ce81af9b6340bfa", "tree": "f850510643ee120dba140bf0bb3e1c1b9c9ce4db", "parents": [ "46bfb7c047a590ac5c24b658f31c170631556bb6" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 27 13:27:24 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 27 13:53:48 2017 -0700" }, "message": "ART: Clean up field initialization\n\nAdd explicit field initialization to default value where necessary.\nAlso clean up interpreter intrinsics header.\n\nTest: m\nChange-Id: I7a850ac30dcccfb523a5569fb8400b9ac892c8e5\n" }, { "commit": "60afd6fe2858c211890845380cd81d4f113bbf2e", "tree": "99ba909eea08ca036e05a10dee33e8f29eac23dd", "parents": [ "99d035fa0f6915d011d2be9ab2303266ec2fee34", "87c9705263d2421607b58a0f1ed397371154fd84" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 15 10:37:59 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 15 10:38:01 2017 +0000" }, "message": "Merge \"ARM64: Improve LocationBuilder for Shifts and IntermediateAddress.\"" }, { "commit": "d1d4530ffa97729aa8944932a7ac2009ae51c7e3", "tree": "b544c9de6459c97b3e51d3984b2348cb0c48df4a", "parents": [ "5ed51e3176f3dc4ff2e50ba4bf52743d404b5b4f", "426b49c45d8088ff3114d3fbcec26db4e00c9324" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Mar 09 15:11:23 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 09 15:11:24 2017 +0000" }, "message": "Merge \"ARM(64): Improve the code generated for HSelect\"" }, { "commit": "87c9705263d2421607b58a0f1ed397371154fd84", "tree": "51eb5d6a033938c74b8f4f1a719475069651ef3d", "parents": [ "335f644f617d9837bc44219c70a2943f36c3f496" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Sep 23 13:34:31 2016 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Mar 09 13:29:26 2017 +0000" }, "message": "ARM64: Improve LocationBuilder for Shifts and IntermediateAddress.\n\nAdd Location::kNoOutputOverlap for OutRegister.\n\nTest: m test-art-target; m test-art-host\n\nChange-Id: Ic8e2f3088427b96a16fcd97b8f5fa6f19325e127\n" }, { "commit": "5ed51e3176f3dc4ff2e50ba4bf52743d404b5b4f", "tree": "1638115757601e4d41d1dc3f3cb9045f5d3d6dd9", "parents": [ "079f5fd58799a23aa5d60a5f85008a4663a33f2a", "54f869ed3c7910e6eb7bade924d41570e9a4cb14" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Mar 09 13:02:12 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 09 13:02:12 2017 +0000" }, "message": "Merge changes Ia26b07f0,Id3d2758c\n\n* changes:\n Revert \"Revert \"Use the holder\u0027s gray bit in Baker read barrier slow paths (ARM, ARM64).\"\"\n Revert \"Revert \"Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\"\"\n" }, { "commit": "426b49c45d8088ff3114d3fbcec26db4e00c9324", "tree": "446ae3073d93e2771882885423c0e290f19d44fa", "parents": [ "c02fe5f31d487765a8c59922c46d459ba6ebf939" ], "author": { "name": "Donghui Bai", "email": "donghui.bai@linaro.org", "time": "Tue Nov 08 14:55:38 2016 +0800" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Thu Mar 09 12:57:41 2017 +0000" }, "message": "ARM(64): Improve the code generated for HSelect\n\nTest: m test-art-target-run-test-566-checker-codegen-select\nTest: m test-art-target-run-test-570-checker-select\nChange-Id: If0140892303490701782df9a818e6d8346bf3d6c\nSigned-off-by: Anton Kirilov \u003canton.kirilov@linaro.org\u003e\n" }, { "commit": "c52f3034b06c03632e937aff07d46c2bdcadfef5", "tree": "031e4d1b2ca0961014e57e4987d80d7aa2c435b0", "parents": [ "ef81e988d0eb4db390e576aac346701b2d820916" ], "author": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Thu Mar 02 13:45:45 2017 +0000" }, "committer": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Wed Mar 08 10:55:17 2017 +0000" }, "message": "Remove --include-patch-information option from dex2oat.\n\nBecause we no longer support running patchoat on npic oat files, which\nmeans the included patch information is unused .\n\nBug: 33192586\nTest: m test-art-host\n\nChange-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67\n" }, { "commit": "54f869ed3c7910e6eb7bade924d41570e9a4cb14", "tree": "668545b4100216adfa3db98635473d26306f9561", "parents": [ "ba650a4d5a0a82c6c88d6546b6111013c2ee8072" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Mar 06 13:54:11 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Mar 06 14:05:15 2017 +0000" }, "message": "Revert \"Revert \"Use the holder\u0027s gray bit in Baker read barrier slow paths (ARM, ARM64).\"\"\n\nThis reverts commit 47b3ab2fd83aaa530b7d2c62bfc024209b8b6923.\n\nIn compiler-generated code, when deciding whether to mark\na heap reference or not in a read barrier, after checking\nwhether the GC is currently marking, also check (in the\nslow path) whether the lock word of the reference\u0027s holder\nis gray, before actually marking the reference.\n\nThis change is only for ARM and ARM64, as it does not\nbenefit x86 nor x86-64.\n\nChange-Id: Ia26b07f0485e23589bfc0e65f83852f2795688c0\nTest: Run ART tests in Baker read barrier configuration.\nTest: Boot a device in Baker read barrier configuration.\nBug: 35780827\nBug: 29516974\n" }, { "commit": "ba650a4d5a0a82c6c88d6546b6111013c2ee8072", "tree": "cc3046a30aab382cc9c346391ca7cc22f3bf11ad", "parents": [ "ef81e988d0eb4db390e576aac346701b2d820916" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Mar 06 13:52:32 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Mar 06 13:57:15 2017 +0000" }, "message": "Revert \"Revert \"Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\"\"\n\nThis reverts commit 35345a555bd7928582a7ffa6369b374b3ddc379d.\n\nIn compiler-generated code, when deciding whether to mark\na heap reference or not in a read barrier, check whether\nthe GC is currently marking, instead of checking the gray\nbit in the reference\u0027s holder\u0027s lock word.\n\nThis change is only for ARM and ARM64, as it does not\nbenefit x86 nor x86-64.\n\nChange-Id: Id3d2758c600115b2f07d345442cfa87edfc2792c\nTest: Run ART tests in Baker read barrier configuration.\nTest: Boot a device in Baker read barrier configuration.\nBug: 35780827\nBug: 29516974\n" }, { "commit": "331605a7ba842573b3876e14c933175382b923c8", "tree": "8a660cc7d1563272e747ac051b3e3e3dd2b90070", "parents": [ "ec280c9a8f9c192eb6ea74fba40bfa1b668c14c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 01 11:01:41 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 01 11:32:02 2017 +0000" }, "message": "Revert \"Revert \"Intrinsify Integer.valueOf.\"\"\n\nFix heap poisoning.\nLOG INFO instead of ERROR to avoid run-test failures with --no-image.\n\nbug:30933338\nTest: ART_HEAP_POISONING\u003dtrue test-art-host test-art-target\n\nThis reverts commit db7b44ac3ea80a722aaed12e913ebc1661a57998.\n\nChange-Id: I0b7d4f1eb11c62c9a3df8e0de0b1a5d8af760181\n" }, { "commit": "db7b44ac3ea80a722aaed12e913ebc1661a57998", "tree": "ef5e6236203e04b59151b2e1b1529f9b389957b4", "parents": [ "cd0b27287843cfd904dd163056322579ab4bbf27" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 28 17:04:50 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 28 17:04:50 2017 +0000" }, "message": "Revert \"Intrinsify Integer.valueOf.\"\n\nHeap poisoning missing\njit-gcstress not optimizing it.\n\nbug:30933338\n\nThis reverts commit cd0b27287843cfd904dd163056322579ab4bbf27.\n\nChange-Id: I5ece1818afbca5214babb6803f62614a649aedeb\n" }, { "commit": "cd0b27287843cfd904dd163056322579ab4bbf27", "tree": "e5e1f0a8cae1f8d604123a72e3377528e4e4f333", "parents": [ "0fc3e418428f9f29a52c1dd60b1d86c71eb00d18" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 23 16:18:41 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 27 23:13:20 2017 +0000" }, "message": "Intrinsify Integer.valueOf.\n\nImproves performance of ArrayListStress and Ritz by ~10% and ~3%.\n\nTest: test-art-host test-art-target\nbug: 30933338\n\nChange-Id: I639046e3a18dae50069d3a7ecb538a900bb590a1\n" }, { "commit": "35345a555bd7928582a7ffa6369b374b3ddc379d", "tree": "ef5e6236203e04b59151b2e1b1529f9b389957b4", "parents": [ "e25fc07d3d3b31fe46cb02a3ed0933c7af3999fd" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Feb 27 14:32:08 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Feb 27 14:33:37 2017 +0000" }, "message": "Revert \"Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\"\n\nThis reverts commit 1372c9f40df1e47bf775f1466bbb96f472b6b9ed.\n\nThis change (along with https://android-review.googlesource.com/#/c/342429/)\ncreates null pointer dereferences.\n\nBug: 35780827\nBug: 29516974\nChange-Id: I2a9c4d0ad8d2ab870c2e0ddbff32152933c77abe\n" }, { "commit": "47b3ab2fd83aaa530b7d2c62bfc024209b8b6923", "tree": "d00923d1045ab66c6aa07ed5a42a69899580d210", "parents": [ "27b1f9cbfc1409418eee4b0e22f29f033e10b64d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Feb 27 14:31:35 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Feb 27 14:31:35 2017 +0000" }, "message": "Revert \"Use the holder\u0027s gray bit in Baker read barrier slow paths (ARM, ARM64).\"\n\nThis reverts commit 27b1f9cbfc1409418eee4b0e22f29f033e10b64d.\n\nThis change (along with https://android-review.googlesource.com/#/c/342428/)\ncreates null pointer dereferences.\n\nBug: 35780827\nBug: 29516974\nChange-Id: If731960a405f9b89528f3daaf235da57cabc5c11\n" }, { "commit": "27b1f9cbfc1409418eee4b0e22f29f033e10b64d", "tree": "07e101c30d024d436086056768fc383d405cd8af", "parents": [ "1372c9f40df1e47bf775f1466bbb96f472b6b9ed" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jan 17 16:56:34 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 23 14:27:50 2017 +0000" }, "message": "Use the holder\u0027s gray bit in Baker read barrier slow paths (ARM, ARM64).\n\nIn compiler-generated code, when deciding whether to mark\na heap reference or not in a read barrier, after checking\nwhether the GC is currently marking, also check (in the\nslow path) whether the lock word of the reference\u0027s holder\nis gray, before actually marking the reference.\n\nThis change is only for ARM and ARM64, as it does not\nbenefit x86 nor x86-64.\n\nTest: Run ART tests in Baker read barrier configuration.\nTest: Boot a device in Baker read barrier configuration.\nBug: 29516974\nChange-Id: I60595a8f4987747faeaa359ad873e9758c1ded75\n" }, { "commit": "1372c9f40df1e47bf775f1466bbb96f472b6b9ed", "tree": "d00923d1045ab66c6aa07ed5a42a69899580d210", "parents": [ "6cc0250f1d1507957fc2fe1543179eab5a8b53f9" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 13 11:47:39 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 23 13:50:11 2017 +0000" }, "message": "Use the \"GC is marking\" information in compiler read barriers (ARM, ARM64).\n\nIn compiler-generated code, when deciding whether to mark\na heap reference or not in a read barrier, check whether\nthe GC is currently marking, instead of checking the gray\nbit in the reference\u0027s holder\u0027s lock word.\n\nThis change is only for ARM and ARM64, as it does not\nbenefit x86 nor x86-64.\n\nTest: Run ART tests in Baker read barrier configuration.\nTest: Boot a device in Baker read barrier configuration.\nBug: 29516974\nChange-Id: Ia5d90286bb9f753f3bbcb3a6254eb166523a2ff5\n" }, { "commit": "74234daabb28a4b9c804bf8bf908e7334bd4d400", "tree": "0b60cb00ab117c1a9a4b92983514962198b548bf", "parents": [ "a7e9bfafeb64b1142433a41b05ddc263cadc61e3" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Jan 13 14:42:47 2017 +0000" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Feb 17 14:59:27 2017 +0000" }, "message": "ARM: Merge data-processing instructions and shifts/(un)signed extensions\n\nThis commit mirrors the work that has already been done for ARM64.\n\nTest: m test-art-target-run-test-551-checker-shifter-operand\nChange-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8\n" }, { "commit": "47bad4dc4d400ce51ba9d5640ae34b28360d9b85", "tree": "5a32492b80c504023f6487eb74f800a91e8c47d6", "parents": [ "4ab54e1935677102c7bec6ec174c7438d89fcd86", "64be0070b3e54454683ad049ae653ee7a91c0076" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Feb 13 11:58:38 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Feb 13 11:58:39 2017 +0000" }, "message": "Merge changes I425a7d61,I30365ad6\n\n* changes:\n Regression test for issue with VIXL AArch64 veneer pool.\n ARM64: Remove all uses of BlockPoolsScope.\n" }, { "commit": "914d7a8fca1184837475016d186585d863e81830", "tree": "e0b2ea229d4071d3d1149aa3c60307b75e350d6c", "parents": [ "4e4b62e21672dbacf5d5abb688a126aabad29269" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Feb 07 14:33:49 2017 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Feb 10 15:12:36 2017 +0000" }, "message": "ARM64: Remove all uses of BlockPoolsScope.\n\nBlockPoolsScope should not be used because it is a VIXL scope\nfor VIXL internal usage only. In arm64 backend the intent was to\nblock pools between a particular instruction (Ldr, Str, Blr, etc)\nand a subsequent MaybeRecordImplicitNullCheck or RecordPcInfo call.\nHowever pools should be emitted at the opening of a scope if this\nis required to satisfy branch/ldr ranges. This is not done by the\nBlockPoolsScope, so proper scopes are now used now:\nExactAssemblyScope and EmissionCheckScope.\n\nTest: test-art-host\nTest: test-art-target\n\nBug: 34850123\n\nChange-Id: I30365ad63c644cf9dd85d5a3c2118f9c57be9d20\n" }, { "commit": "ffa5130425d582ecaa10b6f93bb5fa632fcd93af", "tree": "cbe451cded4fb1d404256fae6c74f6e057c7ea75", "parents": [ "1c66504e0613bdf02dd15e15cd7e5167a4569d19", "d966ce7739bebbdce5481900a1b3220b31f3f3ad" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Feb 10 14:15:33 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Feb 10 14:15:34 2017 +0000" }, "message": "Merge \"Use entrypoint switching on x86 \u0026 x86-64 for GC root read barriers.\"" }, { "commit": "d966ce7739bebbdce5481900a1b3220b31f3f3ad", "tree": "2dc80fcf35d1db73fa4b4a0fa9492d407a1b7a4b", "parents": [ "8d4b1189639f0d8982bde681ccbdd7c03fe6ddbf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 09 16:20:14 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 09 16:45:52 2017 +0000" }, "message": "Use entrypoint switching on x86 \u0026 x86-64 for GC root read barriers.\n\nFor consistency reason (with the ARM and ARM64 implementations),\ncheck the read barrier marking entrypoint\n(`Thread::Current()-\u003epReadBarrierMarkReg ## root.reg()`)\ninstead of `Thread::Current()-\u003eGetIsGcMarking()` to decide whether\nto mark a GC root.\n\nThis change should have no impact on the performance or the\nsize of the generated code.\n\nTest: m test-art-host\nBug: 32638713\nChange-Id: Ifd71312992fdfd6067447cccb7d95860f3771b57\n" }, { "commit": "ea4c126a0165c5a4b997986e6e01c7f975642167", "tree": "0fdfd53472db379a1702846a89933ff1be7a4137", "parents": [ "f8512f8515f7568984e1ca209929262ea88e4b59" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 06 19:59:33 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 08 21:24:01 2017 +0000" }, "message": "Change type initialization entrypoints to kSaveEverything.\n\nAlso avoid the unnecessary read barriers for boot image\nclasses with kBssEntry or kJitTableAddress (the kBssEntry\nand JIT work missed the `read_barrier_option` flag), fix\nbit-rotten non-Baker read barriers on ARM and ARM64 and\nfix bit-rotten ARM64 relative patcher\u0027s IsAdrpPatch() used\nfor erratum 843419 workaround.\n\naosp_angler-userdebug with CC:\n before:\n arm boot*.oat: 35440420\n arm64 boot*.oat: 43504952\n after:\n arm boot*.oat: 35222292 (-218128, -0.62%)\n arm64 boot*.oat: 43389048 (-115904, -0.26%)\n\naosp_angler-userdebug without CC:\n before:\n arm boot*.oat: 31927412\n arm64 boot*.oat: 39340512\n after:\n arm boot*.oat: 31708736 (-218676, -0.68%)\n arm64 boot*.oat: 39211768 (-128744, -0.33%)\n\nTest: m test-art-host (non-CC, Baker CC, table lookup CC)\nTest: m test-art-target on Nexus 6P (non-CC, Baker CC, table lookup CC)\nTest: Nexus 6P boots (non-CC, Baker CC, table lookup CC)\nBug: 30627598\nChange-Id: Ida5bbce414844de9e4273e40334165d4494230d4\n" }, { "commit": "83c8e27a292e6e002fb3b3def75cf6d8653378e8", "tree": "f49ff5c239f318a0290a0d1e0a5b4d9a1ee1d2ba", "parents": [ "357dcb73934356239292c46d6fbedba734da5e00" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 31 14:36:37 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 03 15:12:46 2017 +0000" }, "message": "Code refactoring around sharpening HLoadClass.\n\nEven if the class is not accessible through the dex cache, we\ncan access it by other means (eg boot class, jit table). So rewrite\nstatic field access instruction builder to not bail out if a class\ncannot be accessed through the dex cache.\n\nbug:34966607\n\ntest: test-art-host test-art-target\nChange-Id: I88e4e09951a002b480eb8f271726b56f981291bd\n" }, { "commit": "558dea16c0d3134376634bd1de0fef3146959995", "tree": "2d3b666ab2cc5f3f201ea54b14e664f07ddbb901", "parents": [ "d8f6e6430b26bf199f4a52f0624becb7c29f3c19" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 27 19:40:44 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jan 30 13:12:51 2017 +0000" }, "message": "Handle cycles with double stack slots in ARM64 parallel moves.\n\nWhen acquiring a scratch register to emit a move between two\ndouble stack slots, ask for a FP register first, to avoid\ndepleting the core scratch register pool, which is used in\nvixl::aarch64::MacroAssembler::LoadStoreMacro when the\noffset does not fit in the immediate field of the load\ninstruction.\n\nTest: make test-art-target (on ARM64)\nBug: 34760542\nChange-Id: Ie9b37d007ed6ec5886931a35dcb22a9aff73bbbe\n" }, { "commit": "d8f6e6430b26bf199f4a52f0624becb7c29f3c19", "tree": "1b8970d32b9d1a41fe2e3c1496771c073eebca3a", "parents": [ "f919e8933cdcabbb5769f598a1022d27d0117f67", "d0b51838d5cbec18a9b3a6de7bd9bd2a7a3905d5" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 27 16:42:57 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jan 27 16:42:57 2017 +0000" }, "message": "Merge \"Don\u0027t use VIXL\u0027s temp registers in LocationsBuilderARM64::HandleFieldGet.\"" }, { "commit": "f255be763cd15b78da7891879ec44bd37871eeaf", "tree": "52ff95413b58d0b2dc4d34f8329c6e59084d3831", "parents": [ "ca21dc47adeed92a15a9d3fd090bdd0e6654679c", "86e9d26921d669de6b6b7802517f6b4aabaf5137" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 27 15:08:49 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jan 27 15:08:50 2017 +0000" }, "message": "Merge changes from topic \u0027VIXL-update-270117\u0027\n\n* changes:\n ARM: VIXL32: Keep jump table base label within range of adr.\n ARM64: VIXL: Fix breaking changes to ternary operator with Register inputs.\n" }, { "commit": "d0b51838d5cbec18a9b3a6de7bd9bd2a7a3905d5", "tree": "4304574849efa0b36c19b2e122d29ac67d0dd59a", "parents": [ "fbf47ea64a9f797a82030e919fa4f085c9eb5b28" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jan 26 19:04:23 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 27 13:31:09 2017 +0000" }, "message": "Don\u0027t use VIXL\u0027s temp registers in LocationsBuilderARM64::HandleFieldGet.\n\nBefore this CL, when emitting a volatile field load with a\nlarge offset, it was possible to deplete the pool of VIXL\nARM64 temporary registers (IP0, IP1) in the concurrent\ncollector configuration. To avoid this, we now request a\ntemporary register from the register allocator instead.\n\nTest: m test-art-target-run-test-635-checker-arm64-volatile-load-cc\nBug: 34726333\nChange-Id: Idf73a0306142c6133e259783aacaf7ad5401a2fd\n" }, { "commit": "79db99711f6b27f6ced6b7ed52c827f5211010a9", "tree": "f153b68f97eaa8f71e87f5978b82112544af0acf", "parents": [ "e36c51aee58e61e9fc89851b767379c587f050e3" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Thu Jan 19 14:08:42 2017 +0000" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jan 27 10:17:44 2017 +0000" }, "message": "ARM64: VIXL: Fix breaking changes to ternary operator with Register inputs.\n\nTest: mma art\nChange-Id: I33d1e05e47f337f1a9271b35dba9227057cda096\n" }, { "commit": "b048cb74b742b03eb6dd5f1d6dd49e559f730b36", "tree": "b1f663cbb343488a548cce4db352dbc4af720a89", "parents": [ "f34077c96af3389e8eae65252d4c5d51cf630039" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 23 22:50:24 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 26 09:56:36 2017 +0000" }, "message": "Add per array size allocation entrypoints.\n\n- Update architectures that have fast paths for\n array allocation to use it.\n- Will add more fast paths in follow-up CLs.\n\nTest: test-art-target test-art-host.\nChange-Id: I138cccd16464a85de22a8ed31c915f876e78fb04\n" }, { "commit": "dc5912772707f5b91c3475bbb620c57afb24bb97", "tree": "3e04212c1a46e197c9e512e249fdccaae51876da", "parents": [ "95cf7e42526d4da84086f197dd7d670e407938e0", "5e8d5f01b0fe87a6c649bd3a9f1534228b93423d" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jan 23 18:18:44 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 23 18:18:45 2017 +0000" }, "message": "Merge \"Fix some typos in ART.\"" }, { "commit": "c51842b8dd2ad57a1b05f31ab20ad01123443c50", "tree": "1f252e84d65dda9e301e2db3760adcbddb55bed6", "parents": [ "b0dde4397fa5b0756312b46bd18477a2c1f6a7da", "d8c052ac0aa3382c4807add33afa32580ffeecbb" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jan 23 16:48:50 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 23 16:48:51 2017 +0000" }, "message": "Merge \"ART: Reference.getReferent intrinsic for arm and arm64\"" }, { "commit": "5e8d5f01b0fe87a6c649bd3a9f1534228b93423d", "tree": "a1441acc0021d170f412542ae2a1ae62794e7846", "parents": [ "b0dde4397fa5b0756312b46bd18477a2c1f6a7da" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 18 18:03:43 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jan 23 15:50:01 2017 +0000" }, "message": "Fix some typos in ART.\n\nTest: m build-art-host\nTest: m cpplint-art\nChange-Id: Ifc6ce3d0d645c4a8dca72dd483fc03fc05077130\n" }, { "commit": "d8c052ac0aa3382c4807add33afa32580ffeecbb", "tree": "97679692824fee4b12b03b4d71cb0763a8233e70", "parents": [ "4cd515521828b1f9ce0d5e2f545cb3376a94e9f3" ], "author": { "name": "TatWai Chong", "email": "tatwai.chong@linaro.org", "time": "Wed Nov 02 16:12:48 2016 +0800" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jan 23 14:20:35 2017 +0000" }, "message": "ART: Reference.getReferent intrinsic for arm and arm64\n\nTest: m test-art-host\nTest: m test-art-target\nTest: export ART_HEAP_POISONING\u003dtrue; m test-art-host\nTest: export ART_HEAP_POISONING\u003dtrue; m test-art-target\nBug: 32535355\nChange-Id: Ie63317689dd9e03a24e701c30411f8014970173a\n" }, { "commit": "e761bccf9f0d884cc4d4ec104568cef968296492", "tree": "05a2d20d61c0e91270df2747f0c242433b5ce62b", "parents": [ "b0355130e38034db6b904783a00f74a3524e1881" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 19 08:59:37 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 19 09:32:17 2017 +0000" }, "message": "Revert \"Revert \"Load the array class in the compiler for allocations.\"\"\n\nThis reverts commit fee255039e30c1c3dfc70c426c3d176221c3cdf9.\n\nChange-Id: I02b45f9a659d872feeb35df40b42c1be9878413a\n" }, { "commit": "fee255039e30c1c3dfc70c426c3d176221c3cdf9", "tree": "8207b72cc76513fed9f7b3c01aaa32cd54a87f1c", "parents": [ "cc99df230feb46ba717252f002d0cc2da6828421" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 19 02:11:15 2017 +0000" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 19 02:11:15 2017 +0000" }, "message": "Revert \"Load the array class in the compiler for allocations.\"\n\nlibcore test fails.\n\nThis reverts commit cc99df230feb46ba717252f002d0cc2da6828421.\n\nChange-Id: I5bac595acd2b240886062e8c1f11f9095ff6a9ed\n" }, { "commit": "cc99df230feb46ba717252f002d0cc2da6828421", "tree": "73ac045673e150fa367a8da4d46874f28e928491", "parents": [ "4507fdcb70bd570d5f3968061bf991f0a1233a93" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 17 23:00:24 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 18 15:16:32 2017 +0000" }, "message": "Load the array class in the compiler for allocations.\n\nRemoving one other dependency for needing to pass\nthe current method, and having dex_cache_resolved_types_\nin ArtMethod.\n\noat file increase:\n- x64: 0.25%\n- arm32: 0.30%\n- x86: 0.28%\n\ntest: test-art-host, test-art-target\nChange-Id: Ibca4fa00d3e31954db2ccb1f65a584b8c67cb230\n" }, { "commit": "dcc7ab628c9d59bfab203ab752ff7e11bfd60181", "tree": "b37f3f978c06d4205145eab948d51f86560f64b0", "parents": [ "9748d3d2094c1d3c443a350cf12b9d77b4c4d1e3", "5247c08fb186a5a2ac02226827cf6b994f41a681" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 17 10:25:57 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 17 10:25:57 2017 +0000" }, "message": "Merge \"Put the resolved class in HLoadClass.\"" }, { "commit": "e037a736be43c1e8ba9340dcbf1d17722356a37b", "tree": "f0bc7b4a78d04376b042046afbfd0677d766b523", "parents": [ "db54cc42859a8cc24ed1cda7f9b2f64b27dcb34a", "5d37c152f21a0807459c6f53bc25e2d84f56d259" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 17 09:16:31 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 17 09:16:31 2017 +0000" }, "message": "Merge \"Put inlined ArtMethod pointer in stack maps.\"" }, { "commit": "5247c08fb186a5a2ac02226827cf6b994f41a681", "tree": "8b1305f9fb918024302382b8e8aa43962098e9fa", "parents": [ "0d478f289f0e33f19693d135f1d562b57427ed32" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 13 14:17:29 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 16 23:42:09 2017 +0000" }, "message": "Put the resolved class in HLoadClass.\n\nTo avoid repeated lookups in sharpening/rtp/inlining.\n\nTest: test-art-host test-art-target\nChange-Id: I08d0da36a4bb061cdaa490ea2af3a3217a875bbe\n" }, { "commit": "5d37c152f21a0807459c6f53bc25e2d84f56d259", "tree": "7d8cbce0a55f258150a047def70244f79afc866d", "parents": [ "aa89a4c6fca095904521842c018399f1e3501a45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 12 13:25:19 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 16 22:56:56 2017 +0000" }, "message": "Put inlined ArtMethod pointer in stack maps.\n\nCurrently done for JIT. Can be extended for AOT and inlined boot\nimage methods.\n\nAlso refactor the lookup of a inlined method at runtime to not\nrely on the dex cache, but look at the class loader tables.\n\nbug: 30933338\ntest: test-art-host, test-art-target\nChange-Id: I58bd4d763b82ab8ca3023742835ac388671d1794\n" }, { "commit": "1998cd02603197f2acdc0734397a6d48b2f59b80", "tree": "aa639c7ec96f71d7aaf5d0c865a8a133dbc457c3", "parents": [ "6bec91c7d4670905cd67440991ec76fd54d0f000" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 13 13:02:58 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 13:39:24 2017 +0000" }, "message": "Implement HLoadClass/kBssEntry for boot image.\n\nTest: m test-art-host\nTest: m test-art-host with CC\nTest: m test-art-target on Nexus 9\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng\nBug: 30627598\nChange-Id: I168f24dedd5fb54a1e4215ecafb947ffb0dc3280\n" }, { "commit": "6bec91c7d4670905cd67440991ec76fd54d0f000", "tree": "05f4ba288e629270773c65b34b71be7bae5e92ff", "parents": [ "4155998a2f5c7a252a6611e3926943e931ea280a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 09 15:03:12 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Store resolved types for AOT code in .bss.\n\nTest: m test-art-host\nTest: m test-art-target on Nexus 9.\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng.\nBug: 30627598\nBug: 34193123\nChange-Id: I8ec60a98eb488cb46ae3ea56341f5709dad4f623\n" }, { "commit": "4155998a2f5c7a252a6611e3926943e931ea280a", "tree": "3495370417d54a9bf7d0acedeefe89bd511062e0", "parents": [ "48886c2ee655a16224870fee52dc8721a52babcf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 06 14:04:23 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Make runtime call on main for HLoadClass/kDexCacheViaMethod.\n\nRemove dependency of the compiled code on types dex cache\narray in preparation for changing to a hash-based array.\n\nTest: m test-art-host\nTest: m test-art-target on Nexus 9\nBug: 30627598\nChange-Id: I3c426ed762c12eb9eb4bb61ea9a23a0659abf0a2\n" }, { "commit": "48886c2ee655a16224870fee52dc8721a52babcf", "tree": "debc8b7d9c99a83e2c056c47a8e0718be00c12c3", "parents": [ "58207cfd229d9f0b39fc634cff489dac83e1c010" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 06 11:45:47 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Remove HLoadClass::LoadKind::kDexCachePcRelative.\n\nTest: m test-art-host\nTest: m test-art-target-run-test-552-checker-sharpening\nBug: 30627598\nChange-Id: Ic809b0f3a8ed0bd4dc7ab67aa64866f9cdff9bdb\n" }, { "commit": "ac141397dc29189ad2b2df41f8d4312246beec60", "tree": "a2f481463a14695bf9327fd2f549878ecf30c77b", "parents": [ "5c9f90c5ecf2ff6f93ada0f7b18b46d866c59ea1" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri Jan 13 11:53:47 2017 +0000" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Sun Jan 15 15:18:07 2017 +0000" }, "message": "Revert \"Revert \"ART: Compiler support for invoke-polymorphic.\"\"\n\nThis reverts commit 0fb5af1c8287b1ec85c55c306a1c43820c38a337.\n\nThis takes us back to the original change and attempts to fix the\nissues encountered:\n\n- Adds transition record push/pop around artInvokePolymorphic.\n- Changes X86/X64 relocations for MacSDK.\n- Implements MIPS entrypoint for art_quick_invoke_polymorphic.\n- Corrects size of returned reference in art_quick_invoke_polymorphic\n on ARM.\n\nBug: 30550796,33191393\nTest: art/test/run-test 953\nTest: m test-art-run-test\n\nChange-Id: Ib6b93e00b37b9d4ab743a3470ab3d77fe857cda8\n" }, { "commit": "0d3998b5ff619364acf47bec0b541e7a49bd6fe7", "tree": "a4763c0660372f6311b612c09267cbbc2fe71e89", "parents": [ "aa89a4c6fca095904521842c018399f1e3501a45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 12 15:35:12 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 12 16:51:12 2017 +0000" }, "message": "Revert \"Revert \"Make object allocation entrypoints only take a class.\"\"\n\nThis reverts commit f7aaacd97881c6924b8212c7f8fe4a4c8721ef53.\n\nChange-Id: I6756cd1e6110bb45231f62f5e388f16c044cb145\n" }, { "commit": "c8144cdad955b77988a48777cfbdc6fd2e8c1916", "tree": "354e00610ec25279a8c4b77e8b685e380815813f", "parents": [ "d1a277954284c4dd4b5b14fd4e58f1854daed848", "f7aaacd97881c6924b8212c7f8fe4a4c8721ef53" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jan 12 06:19:22 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 12 06:19:23 2017 +0000" }, "message": "Merge \"Revert \"Make object allocation entrypoints only take a class.\"\"" }, { "commit": "f7aaacd97881c6924b8212c7f8fe4a4c8721ef53", "tree": "780209ac8e992fa63307062977f672aa5bb55d9e", "parents": [ "2b615ba29c4dfcf54aaf44955f2eac60f5080b2e" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 12 02:58:38 2017 +0000" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 12 02:58:38 2017 +0000" }, "message": "Revert \"Make object allocation entrypoints only take a class.\"\n\n960-default-smali64 is failing.\n\nThis reverts commit 2b615ba29c4dfcf54aaf44955f2eac60f5080b2e.\n\nChange-Id: Iebb8ee5a917fa84c5f01660ce432798524d078ef\n" } ], "next": "dcf52765ab5886abdd85a4436fa0358b2a31341d" }