)]}' { "log": [ { "commit": "e7de5ec3e4cd1d607b647d98ea64df105479b867", "tree": "d692c4d1dee08eea4beffd71bd8cdf1d106c059e", "parents": [ "bee510c94560703102ca553a08ec47119959c204" ], "author": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Thu Dec 14 10:25:20 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Fri Dec 15 17:33:12 2017 +0100" }, "message": "MIPS: Support swaps between 128-bit locations\n\nAdd support for swaps between two SIMDStackSlots, two\nVectorRegisters (extended FpuRegister) and between a\nSIMDStackSlot and a VectorRegister.\n\nThis fixes test 623-checker-loop-regressions for\nMIPS64R6 and MIPS32R6.\n\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS64R6)\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS32R6)\n\nChange-Id: I36aa209f79790fb6c08b9a171f810769a6b40afc\n" }, { "commit": "3853017d05d5395250882c68482d8168a0392391", "tree": "a591eb83627e99a4d92108f26dd42629a1ebc360", "parents": [ "c5bf424c340e5610f6677b1ca0a2ae27df43d0d9" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Thu Nov 16 11:11:50 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Mon Dec 04 11:47:18 2017 +0100" }, "message": "MIPS: Improve HandleBinaryOp (Add/Sub) for constant inputs\n\nTest: ./testrunner.py --optimizing --target\nChange-Id: I35154a85f16b4f46d3b4d5827b130b1e20153461\n" }, { "commit": "dbd4303b0da3bd30f53479c14ef541441c8d01f7", "tree": "30f71b12c47f9f148cd694dffdd0efe248aaf1d0", "parents": [ "d40e416f329fa7d7a3ad9cf1bcfbc5eb8137cbc4" ], "author": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Wed Nov 15 16:31:56 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Fri Dec 01 17:46:04 2017 +0100" }, "message": "MIPS: Improve BoundsCheck for constant inputs\n\nNote: All tests were executed on CI20 (MIPS32R2) and in\n QEMU (MIPS32R6 and MIPS64R6).\n\nTest: ./testrunner.py --optimizing --target\nTest: mma test-art-target-gtest\n\nChange-Id: I012fb1013af43d5669a9b0080d481da28ffa7ef2\n" }, { "commit": "f3c52b42a035902245d00a619fed0275afb063d2", "tree": "c46dab07826be55e9ca92ab301eed586c2f307ca", "parents": [ "b360bff818ad0bf59668cd2bebaaeeaa8a3b5dfe" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 17 17:32:12 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 21 17:09:44 2017 +0000" }, "message": "Fill Class and String .bss slots in runtime.\n\nShift the responsibility for filling Class and String .bss\nslots from compiled code to runtime. This reduces the size\nof the compiled code.\n\nMake oatdump list .bss slot mappings (ArtMethod, Class and\nString) for each dex file.\n\naosp_taimen-userdebug boot image size:\n - before:\n arm boot*.oat: 36534524\n arm64 boot*.oat: 42723256\n - after:\n arm boot*.oat: 36431448 (-101KiB, -0.3%)\n arm64 boot*.oat: 42645016 (-76KiB, -0.2%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nTest: m dump-oat, manually inspect output.\nBug: 65737953\nChange-Id: I1330d070307410107e12c309d4c7f8121baba83c\n" }, { "commit": "3e5fecdeacdacf847d376adb05a9ad5587648139", "tree": "5a846ea9547a03a0aa52197058c7fdb5e922c0f6", "parents": [ "2202d56061941b4fecbdb018d84bcefb05b6c683" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Thu Nov 09 14:21:28 2017 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Thu Nov 09 14:24:37 2017 -0800" }, "message": "MIPS32: Use conditional moves to compute 64-bit shifts.\n\nUse conditional moves in\nInstructionCodeGeneratorMIPS::HandleShift()\u0027s 64-bit variable\nshifts to avoid conditional branches (Beqz(TMP, \u0026done)).\n\nAlso, on R6 use Beqzc(TMP, \u0026done, /* is_bare */ true) in place of\nBeqz(TMP, \u0026done).\n\nTest: Boot \u0026 run tests on MIPS32r6 QEMU \u0026 on CI-20 hardware (MIPS32r2).\nTest: test/testrunner/testrunner.py --target --optimizing\n\nChange-Id: I4d34a51cd2397c845f936af853cb5f30e82de438\n" }, { "commit": "cefd676fb79d225fcd7e8e8c0ef141d70a2f45b8", "tree": "be625fa0bc1255cbea5c5066dd878fb0b2a1c454", "parents": [ "dbc26ad5e8ded15688d20a39344c677077311279", "86083f7cd118f3d6c757191e83b4e4abaabdc5d7" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Nov 08 03:26:30 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 08 03:26:30 2017 +0000" }, "message": "Merge \"runtime: Bitstring implementation for subtype checking (4/4).\"" }, { "commit": "86083f7cd118f3d6c757191e83b4e4abaabdc5d7", "tree": "8e5b81ae0d09d41bfd90284a1b6b16b2332435e5", "parents": [ "495e783c9180c3fc033ce459ee0a783e633f7754" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Fri Oct 27 10:59:04 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue Nov 07 14:47:51 2017 -0800" }, "message": "runtime: Bitstring implementation for subtype checking (4/4).\n\nIntegrate the previous CLs into ART Runtime. Subsequent CLs to add\noptimizing compiler support.\n\nUse spare 24-bits from \"Class#status_\" field to\nimplement faster subtype checking in the runtime. Does not incur any extra memory overhead,\nand (when in compiled code) this is always as fast or faster than the original check.\n\nThe new subtype checking is O(1) of the form:\n\n src \u003c: target :\u003d\n (*src).status \u003e\u003e #imm_target_mask \u003d\u003d #imm_target_shifted\n\nBased on the original prototype CL by Zhengkai Wu:\nhttps://android-review.googlesource.com/#/c/platform/art/+/440996/\n\nTest: art/test.py -b -j32 --host\nBug: 64692057\nChange-Id: Iec3c54af529055a7f6147eebe5611d9ecd46942b\n" }, { "commit": "ea604b2a0e2e08c757e509879f6699df8945449d", "tree": "9fa1300027a848db5a1af2c9c432851052a8bc60", "parents": [ "71976e21f12d5886990eb40747dbdee778e31fc1", "a204591b4537141aa6b0fa01f81cc03d92a90456" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Nov 06 12:02:23 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 06 12:02:23 2017 +0000" }, "message": "Merge \"MIPS: Improve InstructionCodeGeneratorMIPS*::GenerateSuspendCheck().\"" }, { "commit": "a204591b4537141aa6b0fa01f81cc03d92a90456", "tree": "2f08659b74a1c3f76d47fd061837622394f28dd0", "parents": [ "a4d89d9bb911f7f3d0a6e4d3b45372e0aea6476d" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Thu Nov 02 12:39:54 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Fri Nov 03 11:18:47 2017 -0700" }, "message": "MIPS: Improve InstructionCodeGeneratorMIPS*::GenerateSuspendCheck().\n\nRelax the only back-edge restriction. Implement optimization for\nMIPS32/MIPS64 which has already been done for the ARM \u0026 x86\narchitectures in\nhttps://android-review.googlesource.com/#/c/platform/art/+/149370/.\n\nTest: Boot \u0026 run tests on 32- \u0026 64-bit version of QEMU.\nTest: test/testrunner/testrunner.py --target --optimizing\nTest: test-art-host-gtest\nTest: test-art-target-gtest\n\nChange-Id: Ie0a4c19ee50ad532fe53933d5808f9d7a4f89b8e\n" }, { "commit": "72627a5f675b1c664beb2ad33d60a1c8dca80826", "tree": "03c363a13cfff3e7c7e9feb158cb2ba56c97ff8e", "parents": [ "ab13432123bc22c997f9dbb12596f05ce782561a", "e0eb48353ddf0c1b79bfec2ba15c899a413c2c70" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 03 10:16:38 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Nov 03 10:16:38 2017 +0000" }, "message": "Merge \"Fix LSA hunt for original reference bug.\"" }, { "commit": "e0eb48353ddf0c1b79bfec2ba15c899a413c2c70", "tree": "71dfe896afa05c39d64373518d1e1e36cb8d8d43", "parents": [ "3e6c13997373efac343a65740da0c4f6e77338b9" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon Oct 30 13:43:14 2017 +0000" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Thu Nov 02 16:17:17 2017 +0000" }, "message": "Fix LSA hunt for original reference bug.\n\nFix a bug in LSA where it doesn\u0027t take IntermediateAddress\ninto account during hunting for original reference.\n\nIn following example, original reference i0 can be transformed\nby NullCheck, BoundType, IntermediateAddress, etc.\n i0 NewArray\n i1 HInstruction(i0)\n i2 ArrayGet(i1, index)\n\nTest: test-art-host\nTest: test-art-target\nTest: load_store_analysis_test\nTest: 706-checker-scheduler\n\nChange-Id: I162dd8a86fcd31daee3517357c6af638c950b31b\n" }, { "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92", "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7", "parents": [ "321b3ca9a36d769283c64d4bdee0798db80af524" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 01 14:35:42 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 02 10:11:02 2017 +0000" }, "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n" }, { "commit": "715f43e1553330bc804cea2951be195473dc343d", "tree": "55e143005efe10e8448c91eff6b88a635af2a3f6", "parents": [ "9e842d3e7d6102d964178e36e5d596ca91895147" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 23 11:00:32 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 23 11:00:32 2017 -0700" }, "message": "MIPS32: Improve stack alignment, use sdc1/ldc1, where possible.\n\n- Ensure that SP is a multiple of 16 at all times, and\n- Use ldc1/sdc1 to load/store FPU registers from/to 8-byte-aligned\n locations wherever possible.\n\nUse `export ART_MIPS32_CHECK_ALIGNMENT\u003dtrue` when building Android\nto enable the new runtime alignment checks.\n\nTest: Boot \u0026 run tests on 32-bit version of QEMU, and CI-20.\nTest: test/testrunner/testrunner.py --target --optimizing --32\nTest: test-art-host-gtest\nTest: test-art-target-gtest\n\nChange-Id: Ia667004573f419fd006098fcfadf5834239cb485\n" }, { "commit": "2e61a57988a9172d446a1638bbd61d94c86ed4d9", "tree": "d39b3405dcfadeb19e2c8cf64c082e2b9a693013", "parents": [ "59c5dfe792d3288c5df75a035f6614cb228d7352" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Oct 23 08:58:15 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Oct 23 08:58:15 2017 +0200" }, "message": "MIPS32: Do implicit null check properly\n\nThis fixes 122-npe test failure in debuggable mode for MIPS32.\n\nTest: ./testrunner.py --target --optimizing --debuggable --ndebuggable on CI20\nChange-Id: I7c5c1e72a92f29e750265b612079ab0bac2a1dc0\n" }, { "commit": "96b7474ebf313abdaf99e657e4ba9758e2467fb1", "tree": "175c7a007ef033c3fccc1e74da2e4424e74da336", "parents": [ "6247604714ae7fb2b64451b225cc0ecd3d4b716f", "174b2e27ebf933b80f4e8b64b4b024ab4306aaac" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 20 10:31:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 20 10:31:25 2017 +0000" }, "message": "Merge \"Use ScopedArenaAllocator for code generation.\"" }, { "commit": "b277aa1385f7f4593c9978d8106669142d158f4f", "tree": "02b4919913ca6193db721f486062b949efb1fbfc", "parents": [ "dfce43569a32ed7da881796713647cd8051d0d4e", "61b922847403ac0e74b6477114c81a28ac2e01a0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 19 09:21:21 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 19 09:21:21 2017 +0000" }, "message": "Merge \"ART: Introduce Uint8 loads in compiled code.\"" }, { "commit": "61b922847403ac0e74b6477114c81a28ac2e01a0", "tree": "02674602fb2592f758f51389b3c7b276ab4df3ee", "parents": [ "6783118d2ad9d759f0617b1219a9e29a10a569f7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 11 13:23:17 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 18 15:52:51 2017 +0100" }, "message": "ART: Introduce Uint8 loads in compiled code.\n\nSome vectorization patterns are not recognized anymore.\nThis shall be fixed later.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --target --optimizing on Nexus 5X\nTest: Nexus 5X boots.\nBug: 23964345\nBug: 67935418\nChange-Id: I587a328d4799529949c86fa8045c6df21e3a8617\n" }, { "commit": "174b2e27ebf933b80f4e8b64b4b024ab4306aaac", "tree": "968cdd8d7fd68571115db77cc288807c3b257911", "parents": [ "6783118d2ad9d759f0617b1219a9e29a10a569f7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 12 13:34:49 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 17 11:12:08 2017 +0100" }, "message": "Use ScopedArenaAllocator for code generation.\n\nReuse the memory previously allocated on the ArenaStack by\noptimization passes.\n\nThis CL handles only the architecture-independent codegen\nand slow paths, architecture-dependent codegen allocations\nshall be moved to the ScopedArenaAllocator in a follow-up.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n BatteryStats.dumpCheckinLocked() : 19.6MiB -\u003e 18.5MiB (-1189KiB)\n BatteryStats.dumpLocked(): 39.3MiB -\u003e 37.0MiB (-2379KiB)\n\nAlso move definitions of functions that use bit_vector-inl.h\nfrom bit_vector.h also to bit_vector-inl.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 64312607\nChange-Id: I84688c3a5a95bf90f56bd3a150bc31fedc95f29c\n" }, { "commit": "3b8c82f4864624da8a1efd09f02bfec754413a20", "tree": "175a5835f4f62f539b5ae457a9e62ec3dcb91d13", "parents": [ "26d46e51a8c387d26e7971857e26f4582b936204" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Oct 10 23:01:34 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Oct 16 17:06:21 2017 -0700" }, "message": "MIPS32R2: Enable table-based switch in presence of irreducible loops\n\nTest: test-art-host-gtest\nTest: booted MIPS32R2 in QEMU\nTest: testrunner.py --target --optimizing --32\nTest: repeat all of the above with suppressed generation\n of HMipsPackedSwitch\n\nChange-Id: Ic8a27d88cd2d7eebaf5826ce8fd1a5607a024844\n" }, { "commit": "bea75ff0835324076fed6ff5d443b9e02c65d223", "tree": "61ae2e8fe552938fcae1e277f51823ba2a4f6e74", "parents": [ "567563a9c6ccc06c2c9889d1c3c4feaa3c2b2dab" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 11 20:39:54 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 12 10:58:02 2017 +0100" }, "message": "Fix using LiveIntervals beyond their lifetime.\n\nFixes a bug introduced by\n https://android-review.googlesource.com/504041\n\nTest: test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 64312607\nChange-Id: I7fd2d55c2a657f736eaed7c94c41d1237ae2ec0b\n" }, { "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1", "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07", "parents": [ "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 14:49:14 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 06 17:53:50 2017 +0100" }, "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n" }, { "commit": "a290160f74ee53c0ffb51c7b3ac916d239c9556a", "tree": "0bfc9728ccee68dbd359b023319423f703448aac", "parents": [ "86d244ec33f333b32301a9ee09088300c8544a7b" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Sep 21 13:50:52 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Oct 05 11:43:34 2017 +0200" }, "message": "MIPS32R2: Share address computation\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nThe address part (index \u003c\u003c ELEM_SHIFT) can be shared across array\naccesses with the same data type and index.\n\nFor example, in the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n for (i...) {\n a[i] \u003d a[i] + 5;\n b[i] \u003d b[i] + c[i];\n }\n}\n\nTest: test-art-host, test-art-target\nChange-Id: Id09fa782934aad4ee47669275e7e1a4d7d23b0fa\n" }, { "commit": "d5d2f2ce627aa0f6920d7ae05197abd1a396e035", "tree": "e8e780780c832e3614a22438a23fb60ee4960ca3", "parents": [ "efac0df8c738764823c637deeca1f3be33912064" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 26 12:37:26 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 10:40:51 2017 +0100" }, "message": "ART: Introduce Uint8 compiler data type.\n\nThis CL adds all the necessary codegen for the Uint8 type\nbut does not add code transformations that use that code.\nVectorization codegens are modified to use Uint8 as the\npacked type when appropriate. The side effects are now\ndisconnected from the instruction\u0027s type after the graph has\nbeen built to allow changing HArrayGet/H*FieldGet/HVecLoad\nto use a type different from the underlying field or array.\n\nNote: HArrayGet for String.charAt() is modified to have\nno side effects whatsoever; Strings are immutable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --target --optimizing on Nexus 6P\nTest: Nexus 6P boots.\nBug: 23964345\nChange-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0\n" }, { "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32", "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af", "parents": [ "e1e347dace0ded83774999bb26c37527dcdb1d5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 22:50:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 25 15:45:01 2017 +0100" }, "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n" }, { "commit": "994cfb3d1595e28b61b8831264c5fc0ebdb6d156", "tree": "701912858cd2e6cca5bae653fcab37d9afb2e0c2", "parents": [ "478abf08c6d2a95eef12e78d3b12857917a91872", "debb510e34b844cc6d80d0304db34c7530fbaf44" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 21:29:42 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Sep 21 21:29:42 2017 +0000" }, "message": "Merge \"MIPS32R2: Allow all kinds of class/string loads and invokes\"" }, { "commit": "debb510e34b844cc6d80d0304db34c7530fbaf44", "tree": "d54afd723f4477a67a5aaef4eb1f639794fd75fe", "parents": [ "5402edd0630cb6f30d98ff712ed914eadce6586c" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Sep 21 14:24:06 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Sep 21 14:24:06 2017 +0200" }, "message": "MIPS32R2: Allow all kinds of class/string loads and invokes\n\nForce generating nal instruction before PC-relative addressing in the\npresence of irreducible loops (HMipsComputeBaseMethodAddress is not\nused in those situations).\n\nThis patch fixes a lot of JIT tests failures.\n\nTest: ./testrunner.py --target --optimizing --jit (CI20 and QEMU)\nTest: mma test-art-target-gtest (CI20 and QEMU)\n\nChange-Id: I1815a6bb5783f439c8263612abff557f797bfef1\n" }, { "commit": "d8dbc8da0e5cc6b5c2176ce2d3877e6194d72c0c", "tree": "af6e9fb02471d75ebdea46190a0aa3e9dbdb892d", "parents": [ "93780a60090356921b844dbefdc13442c9f18b52" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 13:37:47 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 15:55:10 2017 +0100" }, "message": "Refactor compiled_method.h .\n\nMove LinkerPatch to compiler/linker/linker_patch.h .\nMove SrcMapElem to compiler/debug/src_map_elem.h .\nIntroduce compiled_method-inl.h to reduce the number\nof `#include`s in compiled_method.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: Id211cdf94a63ad265bf4709f1a5e06dffbe30f64\n" }, { "commit": "09659c22dc2f2c85a0ade965d1fc5160944b8692", "tree": "66fd5729395d27569c4d9d255a5ce9b44cb000bf", "parents": [ "4d159807a4854caa6396b708a38bbd6fa49d736f" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 18 18:23:32 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 19 10:26:51 2017 -0700" }, "message": "ART: Remove heap poisoning from globals.h\n\nRemove mostly-unused include and move it to its users.\n\nTest: m\nChange-Id: Ibb40f919db64a490290c6e18cf1123aaf44199fc\n" }, { "commit": "fc8b422c286501346b5b797420fb616aaa5e952a", "tree": "61c857a895cdad9ce387a899f92824701259df32", "parents": [ "7090dfe84f78b1928fcbdfd664d0dd9ea52633ff" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Sun Sep 17 13:44:24 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Sep 18 10:57:06 2017 -0700" }, "message": "Clean up AtomicDexRefMap\n\nMake ClassReference, TypeReference, and MethodReference extend\nDexFileReference. This enables using all of these types as the key\nfor AtomicDexRefMap.\n\nTest: test-art-host\nBug: 63851220\nBug: 63756964\n\nChange-Id: Ida3c94cadb53272cb5057e5cebc5971c1ab4d366\n" }, { "commit": "94ec2db21332ee1dcdbbf254b99a9a999a304fe0", "tree": "6ced7e596731b61f95a3693f336527f55ea3cf3a", "parents": [ "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 06 17:21:03 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 11 15:12:51 2017 +0100" }, "message": "Use mmapped boot image class table for PIC app HLoadClass.\n\nImplement new HLoadClass load kind for boot image classes\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image ClassTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image classes compared to the kBssEntry\nas we can completely avoid the slow path and stack map\nunless we need to do the class initialization check.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20312800\n - after: 19775352 (-525KiB)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I13adb19a1fa7d095a72a41f09daa6101876e77a8\n" }, { "commit": "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63", "tree": "f92b309ddc43c2254b6067346a653170fbbf7316", "parents": [ "0f3c7003e08a42a4ed8c9f8dfffb1bee1118de59" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 25 13:26:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 07 17:52:35 2017 +0100" }, "message": "Use mmapped boot image intern table for PIC app HLoadString.\n\nImplement new HLoadString load kind for boot image strings\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image InternTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image strings compared to the kBssEntry\nas we can completely avoid the slow path and stack map.\n\nWe separate the InternedStrings and ClassTable sections of\nthe boot image (.art) file from the rest, aligning the\nstart of the InternedStrings section to a page boundary.\nThis may actually increase the size of the boot image file\nby a page but it also allows mprotecting() these tables as\nread-only. The ClassTable section is included in\nanticipation of a similar load kind for HLoadClass.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20862776\n - after: 20308512 (-541KiB)\nNote that 92KiB savings could have been achieved by simply\navoiding the read barrier, similar to the HLoadClass flag\nIsInBootImage(). Such flag is now unnecessary.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I5f2bf1fc0bb36a8483244317cfdfa69e192ef6c5\n" }, { "commit": "a663d9d5b32a525794a2b98fa43da54dd7c79e3b", "tree": "88c643ca5ebfb0dfe11f45a9b232f9a2592fb043", "parents": [ "b9463674919ba91fe131e65785ad67b4202e86b9" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jul 31 18:43:18 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Aug 18 15:29:31 2017 -0700" }, "message": "MIPS32: Allow some patched instructions in delay slots\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest32\nTest: testrunner.py --target --optimizing --32\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0\n" }, { "commit": "0cab65610a6a984a94ef4c3f232fe0273e78d95b", "tree": "669fa607f4cd9ad8eef9223bb124fb72265a06b3", "parents": [ "2e53f8f69f8c4175085e337445ec42aa045a2f7f" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jul 25 15:19:36 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Jul 30 20:09:26 2017 -0700" }, "message": "MIPS: Eliminate hard-coded offsets in branches\n\nThe bulk of the change is in the assemblers and their\ntests.\n\nThe main goal is to introduce \"bare\" branches to labels\n(as opposed to the existing bare branches with relative\noffsets, whose direct use we want to eliminate).\nThese branches\u0027 delay/forbidden slots are filled\nmanually and these branches do not promote to long (the\nbranch target must be within reach of the individual\nbranch instruction).\n\nThe secondary goal is to add more branch tests (mainly\nfor bare vs non-bare branches and a few extra) and\nrefactor and reorganize the branch test code a bit.\n\nThe third goal is to improve idiom recognition in the\ndisassembler, including branch idioms and a few others.\n\nFurther details:\n- introduce bare branches (R2 and R6) to labels, making\n R2 branches available for use on R6\n- make use of the above in the code generators\n- align beqz/bnez with their GNU assembler encoding to\n simplify and shorten the test code\n- update the CFI test because of the above\n- add trivial tests for bare and non-bare branches\n (addressing existing debt as well)\n- add MIPS32R6 tests for long beqc/beqzc/bc (debt)\n- add MIPS64R6 long beqzc test (debt)\n- group branch tests together\n- group constant/literal/address-loading tests together\n- make the disassembler recognize:\n - b/beqz/bnez (beq/bne with $zero reg)\n - nal (bltzal with $zero reg)\n - bal/bgezal (bal \u003d bgezal with $zero reg)\n - move (or with $zero reg)\n - li (ori/addiu with $zero reg)\n - dli (daddiu with $zero reg)\n- disassemble 16-bit immediate operands (in andi, ori,\n xori, li, dli) as signed or unsigned as appropriate\n- drop unused instructions (bltzl, bltzall, addi) from\n the disassembler as there are no plans to use them\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I62b74a6c00ce0651528114806ba24a59ba564a73\n" }, { "commit": "4147fcc43c2ee019a06e55384985e3eaf82dcb8c", "tree": "11ec92efbfddf7736bbc74ed35fcfb3756bfcfb0", "parents": [ "e8f48da635c4d07bbe431e5819da8e1fad91a8ef" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Jun 17 19:57:27 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Jul 19 15:03:10 2017 -0700" }, "message": "MIPS: Reduce Baker read barrier code size overhead\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32 and MIPS64 in QEMU with poisoning\n in configurations:\n - with Baker read barrier thunks\n - without Baker read barrier thunks\n - ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2\n" }, { "commit": "854df416f12c48b52239fe163ab8a7fcac4cddd3", "tree": "f5cf247f1e71a5242c797b8fab99ded21839267d", "parents": [ "e63a91111d13f33028c2988ded53a4659140ca2e" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Jun 27 14:41:39 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Jul 13 10:17:07 2017 +0200" }, "message": "MIPS: TLAB allocation entrypoints\n\nAdd fast paths for TLAB allocation entrypoints for MIPS32 and MIPS64.\nAlso improve rosalloc entrypoints.\n\nNote: All tests are executed on CI20 (MIPS32R2) and in QEMU (MIPS32R6\n and MIPS64R6), with and without ART_TEST_DEBUG_GC\u003dtrue.\n\nTest: ./testrunner.py --optimizing --target\nTest: mma test-art-target-gtest\nTest: mma test-art-host-gtest\n\nChange-Id: I92195d2d318b26a19afc5ac46a1844b13b2d5191\n" }, { "commit": "97c46466aea25ab63a99b3d1afc558f0d9f55abb", "tree": "afd225f51d28a77329bc2590a025400e088f260c", "parents": [ "00cca3a275562d110a8b35094b9b12fac37f67ab" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu May 11 14:04:03 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 11 17:43:27 2017 +0100" }, "message": "Introduce a Marking Register in ARM64 code generation.\n\nWhen generating code for ARM64, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register X20,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test\nBug: 37707231\nChange-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b\n" }, { "commit": "ca8c2951ea25e8f93eea9decc70d81937b4361dd", "tree": "72c811abe58895b4972cd88ee267c8ca66155fd1", "parents": [ "2e0a7e5047fde08ddd220aaa1a0e64d44ecbb420" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Mon May 29 11:31:46 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 06 14:06:33 2017 +0200" }, "message": "MIPS32: Saves 128-bit vector registers along SuspendCheckSlowPath\n\nWe need to save 128 bits of data. This is only done for vector\nregisters that are live, so overhead is not too big.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS)\nChange-Id: I0f792e9c98011be3e24d5fad35a8244faafcb9a0\n" }, { "commit": "8091ed8a26db4609c719ea8d905145ddfed7f498", "tree": "342d4459e8e9c61af7b69fc2ac2e0512592cf9f4", "parents": [ "61cfb15e2588ff1fe3c80efbfcf55973122b28cb", "5fa5c04ca39fb9c46bfef0e0807a18d0cd9a4ba7" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jul 03 11:48:56 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 03 11:48:56 2017 +0000" }, "message": "Merge \"MIPS: Shorten .bss string/class loads\"" }, { "commit": "8098da9cf3e3f7875546c2cd953f2337587b39db", "tree": "8f0b2d69f83a1de7a0bb80ce1c3f1412c429615d", "parents": [ "ebd4def76f4e60e442edb8d48f43a931bc3c773e" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Wed Jun 28 12:07:50 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Wed Jun 28 17:42:17 2017 +0200" }, "message": "MIPS32: MoveLocation refactoring\n\nMove32 and Move64 are removed so MoveLocation now handles all cases.\nReason for this are 128-bit (SIMDStackSlot, VectorRegister) moves\nwhich will be added in follow-up patch.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU\n\nChange-Id: I93496e74874f77337b11b2265aa4b470bc7c6ce2\n" }, { "commit": "5fa5c04ca39fb9c46bfef0e0807a18d0cd9a4ba7", "tree": "f902c5dad2486b8372c31989ac9b917715231fa8", "parents": [ "83b140474aa1759739c8ee4464bf226c4fa0f6d7" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Jun 01 21:07:52 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Jun 08 14:39:57 2017 -0700" }, "message": "MIPS: Shorten .bss string/class loads\n\nThis is a follow-up to\nhttps://android-review.googlesource.com/#/c/384033/.\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 and MIPS64 in QEMU in configurations:\n ART_USE_READ_BARRIER\u003dfalse,\n ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I4cb2f4ded13c0d9fc960c7eac55396f7931c1e38\n" }, { "commit": "0eb882bfc5d260e8014c26adfda11602065aa5d8", "tree": "e66dbebfb1e9a254c20954a2f2f98541aebfd5af", "parents": [ "b5f5d746ac3f2c3088292395603cb1470e7749d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 15 13:39:18 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 15:39:24 2017 +0100" }, "message": "Use ArtMethod* .bss entries for HInvokeStaticOrDirect.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug.\nBug: 30627598\nChange-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f\n" }, { "commit": "3c8a91250b3e4e87548ec16bf1ab1ea46dbb84a4", "tree": "b5da100b358d1335eab403372e4f616c5c2d607c", "parents": [ "0a87f31513e5f9da27856af054d2241452898b22", "e7197bf7d58c705a048e13e241d7ca320502cd40" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 10:38:10 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 07 10:38:11 2017 +0000" }, "message": "Merge \"Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\"" }, { "commit": "e7197bf7d58c705a048e13e241d7ca320502cd40", "tree": "496032b40145660b40002b9d5b7a78f1c2eeb44f", "parents": [ "4ee8e291a7d5b7b98f35f495eb97705836910871" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 17:00:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 06 15:26:42 2017 +0100" }, "message": "Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\n\nIn preparation for replacing the dex cache method array\nwith a hash-based array, get rid of one unnecessary use.\nThis method load kind is currently used only on mips for\nirreducible loops and OSR, so this should have no impact\non x86/x86-64/arm/arm64.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Repeat the above tests with manually changing\n kDexCachePcRelative to kRuntimeCall in sharpening.cc.\n (Ignore failures in 552-checker-sharpening.)\nBug: 30627598\nChange-Id: Ifce42645f2dcc350bbb88c2f4642e88fc5f98152\n" }, { "commit": "847e6ce98b4b822fd94c631975763845978ebaa3", "tree": "760e26dea1597d8219d8c515317d978b0213cdc1", "parents": [ "cff1b21b3e19c5d3a2d726fdb60dacd7de2a6f0d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 13:55:07 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 14:03:28 2017 +0100" }, "message": "Rename kDexCacheViaMethod to kRuntimeCall for HLoadClass/String.\n\nThe old name does not reflect the actual code anymore.\n\nTest: testrunner.py --host\nChange-Id: I2e13cf727bba9d901c4d3fc821bb526d38a775b8\n" }, { "commit": "6079dca3058e58bb9e12a60a10324a5218a99274", "tree": "19e3a8ccf7a8ac831c27658e0470c4f83debef74", "parents": [ "0a5ace58e973da278049f837bf2cdbaf7b44849c" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun May 28 19:10:28 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun May 28 20:17:39 2017 -0700" }, "message": "MIPS32R2: Fix MethodLoadKind::kBootImageLinkTimePcRelative\n\nThis makes MIPS32 boot again.\n\nThe issue was introduced in commit\n6597946d29be9108e2cc51223553d3db9290a3d9:\nStatic invokes in slow paths would sometimes get\nHMipsComputeBaseMethodAddress from the stack into the\nsame register where the art method pointer would later\nbe loaded (A0) with the former being overwritten in the\nprocess of loading the latter.\n\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: Ib584cf66795574175650f42b191c797fb3b3965f\n" }, { "commit": "6597946d29be9108e2cc51223553d3db9290a3d9", "tree": "cea6647a45cc59fa1423751179e647124f269990", "parents": [ "a654e0378a8d0bb149362399917e4da2959e6991" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 19 17:25:12 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 22 18:35:05 2017 +0100" }, "message": "Use PC-relative pointer to boot image methods.\n\nIn preparation for adding ArtMethod entries to the .bss\nsection, add direct PC-relative pointers to methods so that\nthe number of needed .bss entries for boot image is small.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target on Nexus 6P\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug\nBug: 30627598\nChange-Id: Ia89f5f9975b741ddac2816e1570077ba4b4c020f\n" }, { "commit": "764d454d1d51448deb81f6e8d2d7d317c7f4d1b4", "tree": "029f9e65cfe7e953df55b7af45e099924ffdbbac", "parents": [ "7974468d32b817be1d49dfcf513605f646c481bc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 10:31:41 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 15:08:55 2017 +0100" }, "message": "Remove LoadString/Class kind kBootImageLinkTimeAddress.\n\nWe no longer support non-PIC boot image compilation.\n\nAlso clean up some obsolete code for method patches\nand make JIT correctly report itself as non-PIC.\n\nTest: testrunner.py --host\nTest: testrunner.py --target\nBug: 33192586\nChange-Id: I593289c5c1b0e88b82b86a933038be97bbb15ad2\n" }, { "commit": "f4e23a8a671e27065bf1cbef7e41403de166f321", "tree": "d25d31f7c1c53f4baf746baafa76b891596c5d49", "parents": [ "d6705a0586377f1b0d7d14d3abe2b270bb0adb18" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Tue May 09 15:43:45 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri May 12 15:08:27 2017 +0200" }, "message": "MIPS: Drop unnecessary code for R6 (NAN2008)\n\nThe latest MIPS64R6 emulator supports NAN2008 standard (it correctly\nsets FCSR.NAN2008 to 1 as it is required from R6). Because of that,\nmany workarounds can be removed.\n\nThis simplifies code generator and intrinsics.\n\nTest: ./testrunner.py --target --optimizing in QEMU for MIPS64R6\nTest: ./testrunner.py --target --optimizing in QEMU for MIPS32R6\nTest: ./testrunner.py --target --optimizing in QEMU for MIPS32R2\n\nChange-Id: Ib5335835b61f55690ff574bca580ea8f809657bb\n" }, { "commit": "7d157fcaaae137cc98dbfb872aa1bdc0105a898f", "tree": "2b7d8affda23908e5bfbfaad446079db2ef1ee09", "parents": [ "58d7ddc678e5bcd2364c24c4bdc8a3cfbcfc5358" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 10 16:29:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 11 11:14:54 2017 +0100" }, "message": "Clean up some uses of \"auto\".\n\nMake actual types more explicit, either by replacing \"auto\"\nwith actual type or by assigning std::pair\u003c\u003e elements of\nan \"auto\" variable to typed variables. Avoid binding const\nreferences to temporaries. Avoid copying a container.\n\nTest: m test-art-host-gtest\nChange-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603\n" }, { "commit": "ddc38fe3e5618e3922ecc445193dacb2f39ef736", "tree": "090cf77abda6a5755371673966ceea83f858048c", "parents": [ "45f9865cc974d344c9a859508c8ec8ce101f4c52", "4e92c3ce7ef354620a785553bbada554fca83a67" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 10 10:55:45 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 10 10:55:47 2017 +0000" }, "message": "Merge \"Add runtime reasons for deopt.\"" }, { "commit": "4e92c3ce7ef354620a785553bbada554fca83a67", "tree": "42029deff4d3ba7f89b5fdbf79ff410da575f431", "parents": [ "549844e9ccf432d1396b19af890eedb602b8ba04" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 08 09:34:26 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 10 09:27:33 2017 +0100" }, "message": "Add runtime reasons for deopt.\n\nCurrently to help investigate. Also:\n1) Log when deoptimization happens (which method and what reason)\n2) Trace when deoptimization happens (to make it visible in systrace)\n\nbug:37655083\nTest: test-art-host test-art-target\nChange-Id: I0c2d87b40db09e8e475cf97a7c784a034c585e97\n" }, { "commit": "bf2dd4baecee0e82608a83eca9738205446bcb03", "tree": "a321c0bfb58a3d8caa1e4f95b1860656ab2fad97", "parents": [ "b9c3a99096c746b09af611e55e11b86600374011", "6d482aa01d2190e7f972553f359df7958d31af57" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon May 08 14:47:09 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 08 14:47:11 2017 +0000" }, "message": "Merge \"MIPS32: Implement branchless HCondition for longs\"" }, { "commit": "f3fb1fc453c253a075050910a558c89c1330b5af", "tree": "ca758f050dc3a892e360af094f36fde056e40fef", "parents": [ "9459127abb57b0892d3ddeb1e30ac0bf28c93761", "c61c0761150340263160b568d8a952e9a3d80d56" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu May 04 14:46:32 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 04 14:46:33 2017 +0000" }, "message": "Merge \"MIPS: Change remaining entrypoints to save everything.\"" }, { "commit": "d01745ef88bfd25df574a885d90a1a7785db5f5b", "tree": "058eb1593dbb0fe8a8e26b901909bec8aa01d474", "parents": [ "a57c334075b193de9690fff97acf6c1b1d1283fc" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Wed Apr 05 16:40:31 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue May 02 09:45:45 2017 -0700" }, "message": "optimizing: constructor fence redundancy elimination - remove dmb after LSE\n\nPart one of a few upcoming CLs to optimize constructor fences.\n\nThis improves load-store-elimination; all singleton objects that are not\nreturned will have their associated constructor fence removed.\n\nIf the allocation is removed, so is the fence. Even if allocation is not\nremoved, fences can sometimes be removed.\n\nThis change is enabled by tracking the \"this\" object associated with the\nconstructor fence as an input. Fence inputs are considered weak; they do not keep\nthe \"this\" object alive; if the instructions for \"this\" are all deleted,\nthe fence can also be deleted.\n\nBug: 36656456\nTest: art/test.py --host \u0026\u0026 art/test.py --target\nChange-Id: I05659ab07e20d6e2ecd4be051b722726776f4ab1\n" }, { "commit": "c61c0761150340263160b568d8a952e9a3d80d56", "tree": "105418862af2193d590fc5da868e4c72da7d6e6a", "parents": [ "a57c334075b193de9690fff97acf6c1b1d1283fc" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Apr 10 13:54:23 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Apr 30 15:30:58 2017 -0700" }, "message": "MIPS: Change remaining entrypoints to save everything.\n\nThis also fixes two issues:\n1. Missing restore of the callee-clobbered gp register on\n MIPS32\n2. Incorrect DCHECK causing test 916-obsolete-jit to fail\n on MIPS32 in the ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n configuration\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: booted MIPS64 (with 2nd arch MIPS32R2) in QEMU\nTest: same tests as above for both MIPS32R6 and MIPS64R6\nTest: repeat all of the above in two configurations:\n ART_READ_BARRIER_TYPE\u003dTABLELOOKUP,\n ART_USE_READ_BARRIER\u003dfalse.\n\nChange-Id: I06a3c24579242a632ec8c373c233217d558a8401\n" }, { "commit": "cd0295d81b6d53bbade117a0531b2453e8cb7c7f", "tree": "eceada4e7329ce8fc2e993f414f515c186b81f10", "parents": [ "ef6787bd892b55588ebb2835cc3a3bc4e9e08d04" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Mar 31 15:26:54 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Apr 10 10:19:30 2017 -0700" }, "message": "MIPS: Use Lsa/Dlsa when possible.\n\nFor MIPS32R6 replace instances of \"sll/addu\" to calculate the\naddress of an item in an array with \"lsa\". For other versions of\nMIPS32 use the \"sll/addu\" sequence. Encapsulate this logic in an\nassembler method to eliminate having a lot of statements like\n\"if (IsR6()) { ... } else { ... }\" scattered throughout the code.\n\nMIPS64 always supports R6. This means that all instances of\n\"dsll/daddu\" used to calculate the address of an item in an array\ncan be replaced by \"dlsa\" so there is no need to encapsulate\nconditional logic in a special method. The code can just emit\n\"dlsa\" directly.\n\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTested on MIPS32, and MIPS64 QEMU.\nTest: \"make test-art-target-gtest32\" on CI20 board.\nTest: \"cd art; test/testrunner/testrunner.py --target --optimizing --32\"\n on CI20 board.\n\nChange-Id: Ibe5facc1bc2a6a7a6584e23d3a48e163ae38077d\n" }, { "commit": "1595815c2a914a78df7dfb6f0082f47d4e82bb36", "tree": "8fd53c3c91158b33e744e43cc655b2e2a180a3fc", "parents": [ "4ba18fdfc2581a2328ab745c2707e3ed375d9e64" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Feb 09 19:08:30 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Mar 28 23:35:34 2017 -0700" }, "message": "MIPS: Implement read barriers.\n\nThis is the core functionality. Further improvements\nwill be done separately.\n\nThis also adds/moves memory barriers where they belong and\nremoves the UnsafeGetLongVolatile and UnsafePutLongVolatile\nMIPS32 intrinsics as they need to load/store a pair of\nregisters atomically, which is not supported directly by\nthe CPU.\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"testrunner.py --target --optimizing -j1\"\nTest: same MIPS64 boot/test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\nTest: \"testrunner.py --target --optimizing --32 -j2\" on CI20\nTest: same CI20 test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I0ff91525fefba3ec1cc019f50316478a888acced\n" }, { "commit": "68fdd5a22024f70a65159bcb8929296fc93b807d", "tree": "d0d5256fde2f91b61bde97d0632436cabb0b23db", "parents": [ "02a4d7ff633e67d0a5113f0fc742116dcdc5b7f6", "c52f3034b06c03632e937aff07d46c2bdcadfef5" ], "author": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Thu Mar 09 08:33:03 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 09 08:33:04 2017 +0000" }, "message": "Merge \"Remove --include-patch-information option from dex2oat.\"" }, { "commit": "f02253d12be42a5b980791265f0eb61d875396e3", "tree": "1f908e9a9523658bf2e244b90508852e1885a222", "parents": [ "d419beb312816edbf2186c12b15321d11c29996d", "66b69ad6d1a2ddd38bf533a3c887c5cdaf512634" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Mar 08 23:58:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 08 23:58:25 2017 +0000" }, "message": "Merge \"MIPS: Optimize code generation of check-cast and instance-of.\"" }, { "commit": "c52f3034b06c03632e937aff07d46c2bdcadfef5", "tree": "031e4d1b2ca0961014e57e4987d80d7aa2c435b0", "parents": [ "ef81e988d0eb4db390e576aac346701b2d820916" ], "author": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Thu Mar 02 13:45:45 2017 +0000" }, "committer": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Wed Mar 08 10:55:17 2017 +0000" }, "message": "Remove --include-patch-information option from dex2oat.\n\nBecause we no longer support running patchoat on npic oat files, which\nmeans the included patch information is unused .\n\nBug: 33192586\nTest: m test-art-host\n\nChange-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67\n" }, { "commit": "6d482aa01d2190e7f972553f359df7958d31af57", "tree": "f5db8123f0b4bb1444bd076f86fda47eafdd249a", "parents": [ "2ec053fa337c1934ccb803136b56b57bcc06a32f" ], "author": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Fri Feb 03 13:24:08 2017 +0100" }, "committer": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Wed Mar 08 11:09:22 2017 +0100" }, "message": "MIPS32: Implement branchless HCondition for longs\n\nTest: booted MIPS32 in QEMU\nTest: mma test-art-target-run-test\nTest: mma test-art-target-gtest-codegen_test\n\nChange-Id: Ie4eac862fa5577905db9f3f0746c2f7dc58f7a2b\n" }, { "commit": "5743386b4d161f3884275c66b0783bd3cc3a8050", "tree": "6794f8047586e7bc02702cc560bca51d1ab5bcc3", "parents": [ "425b5d23e2c60d295471817a75b1b554481c5334" ], "author": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Tue Jan 17 16:59:03 2017 +0100" }, "committer": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Fri Mar 03 09:36:43 2017 +0100" }, "message": "MIPS64: Refactor implicit null checks in array/field get/set\n\nRationale: on MIPS64 64-bit loads and stores may be performed\nas pairs of 32-bit loads/stores. Implicit null checks must be\nassociated with the first 32-bit load/store in a pair and not\nthe last. This change ensures proper association of said checks\n(a few were done after the last 32-bit load/store in a pair)\nand lays ground for further improvements in array/field get/set.\n\nAdditionally ported to MIPS32.\n\nTest: mma test-art-target-run-test in QEMU\nTest: mma test-art-host-gtest\n\nChange-Id: If2612df62c21522959e69c637a36cc4ea962a32e\n" }, { "commit": "66b69ad6d1a2ddd38bf533a3c887c5cdaf512634", "tree": "d4462b96af0f0f2b28207dc6533a2b83e9b5e434", "parents": [ "fddc19338d9fdee24c4e10b758db1a6997004e2e" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Feb 24 00:51:44 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Mar 01 12:25:19 2017 -0800" }, "message": "MIPS: Optimize code generation of check-cast and instance-of.\n\nThis is in preparation for read barrier support.\n\nTest: test-art-host-gtest\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target\nTest: booted MIPS64 (with 2nd arch MIPS32R2) in QEMU\nTest: test-art-target (MIPS64R6 only)\n\nNote: built with ART_HEAP_POISONING\u003dtrue.\n\nChange-Id: I072ad41944a5ef390c81458c0ba49a71684cb2a9\n" }, { "commit": "c061de1236e98fdd34d0214a9bbcc0e2149ff226", "tree": "31f6644cf080613d8493db8f510810a89cc6a718", "parents": [ "4c9c57054578022d9ab8442264fbc661769f97f5" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Feb 14 13:27:23 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Feb 22 14:10:59 2017 -0800" }, "message": "MIPS: Implement heap poisoning in ART\u0027s Optimizing compiler.\n\nThis is in preparation for read barrier support.\n\nBug: 12687968\n\nTest: test-art-host-gtest\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target (both MIPS64R6 and MIPS32R6)\n\nNote: built with ART_HEAP_POISONING\u003dtrue.\n\nChange-Id: I0e6e04ff8de2fc8ca6126388409fa218e6920734\n" }, { "commit": "f94fa81e20d00929ef52707cd577353b95d40284", "tree": "cb79d0e0610775a41f0511b4cacfe87136bbba60", "parents": [ "806ac631e53f12061cb0ae7640aa9cd0dd79243d" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Feb 10 17:48:52 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Feb 13 09:05:26 2017 +0000" }, "message": "String Compression for MIPS32 and MIPS64\n\nChanges on intrinsics and Code Generation on MIPS32 and MIPS64 for\nstring compression feature.\n\nTesting is done with STRING_COMPRESSION_ENABLED \u003d true (in libcore),\nmirror::kUseStringCompression \u003d true and STRING_COMPRESSION_FEATURE set\nto 1.\n\nTest: booted MIPS32 and MIPS64 in QEMU\nTest: mma test-art-target-run-test on CI20 (MIPS32R2)\nTest: mma test-art-target-run-test in QEMU (MIPS64R6)\n\nChange-Id: If50a6b6c0792bfa34d4fdff6bf2c7542211d2689\n" }, { "commit": "fe076a51b0498c2771341cc09a77db15b437328f", "tree": "6f6e0c250e2ecc450567f90a7792f51f8d6b3384", "parents": [ "8781fe65fe41d971173bb2d05afe0dc00b5c08ce", "83c8e27a292e6e002fb3b3def75cf6d8653378e8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 06 08:27:55 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Feb 06 08:27:56 2017 +0000" }, "message": "Merge \"Code refactoring around sharpening HLoadClass.\"" }, { "commit": "83c8e27a292e6e002fb3b3def75cf6d8653378e8", "tree": "f49ff5c239f318a0290a0d1e0a5b4d9a1ee1d2ba", "parents": [ "357dcb73934356239292c46d6fbedba734da5e00" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 31 14:36:37 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 03 15:12:46 2017 +0000" }, "message": "Code refactoring around sharpening HLoadClass.\n\nEven if the class is not accessible through the dex cache, we\ncan access it by other means (eg boot class, jit table). So rewrite\nstatic field access instruction builder to not bail out if a class\ncannot be accessed through the dex cache.\n\nbug:34966607\n\ntest: test-art-host test-art-target\nChange-Id: I88e4e09951a002b480eb8f271726b56f981291bd\n" }, { "commit": "627c1a0e573b4512e68f097771d7fdd4d8c7f7de", "tree": "5e9590d470e32e205f862d694cebd95da5cf0a97", "parents": [ "318797a758f81e7f8a0b440129238b9b5eb1b74e" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jan 30 19:28:14 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Feb 01 15:29:43 2017 -0800" }, "message": "MIPS: Support kJitTableAddress kinds of string/class loads.\n\nAlso remove a few stale comments.\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dfalse\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dtrue\n test-art-target-run-test\"\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I8914b8e6594e030f8137e7fface1ae20b6d6b971\n" }, { "commit": "6b892cd757db7e163b54c8a0ef5ba777b1a4772c", "tree": "b0e65b596158ef9207983305517ae66ab5f87b67", "parents": [ "e38436063fb4baf88152344b465eeeb1b7f6dce5" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jan 03 17:11:38 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jan 30 09:05:44 2017 -0800" }, "message": "MIPS32R6: Improve PC-relative string/class loads and invokes.\n\nUse PC-relative addressing on MIPS32R6 instead of\nHMipsDexCacheArraysBase and allow such PC-relative\naddressing in presence of irreducible loops.\n\nAlso save a couple of instructions when handling\nstring and class loads from bss.\n\nTest: test-art-host-gtest\nTest: booted MIPS32R2 in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test\"\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test32\"\n\nChange-Id: I5d0fcbf271541294a3d4479987d52e2aaff084d9\n" }, { "commit": "a2f526f889be06f96ea59624c9dfb1223b3839f3", "tree": "769f517e6664de0e89abeadf07a39d5410fcee42", "parents": [ "64e50021845b1ad9d8851596e8aaddf18be217c2" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jan 19 14:48:48 2017 -0800" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Jan 20 15:47:06 2017 -0800" }, "message": "Compressed native PC for stack maps\n\nCompress native PC based on instruction alignment. This reduces the\nsize of stack maps, boot.oat is 0.4% smaller for arm64.\n\nTest: test-art-host, test-art-target, N6P booting\n\nChange-Id: I2b70eecabda88b06fa80a85688fd992070d54278\n" }, { "commit": "e761bccf9f0d884cc4d4ec104568cef968296492", "tree": "05a2d20d61c0e91270df2747f0c242433b5ce62b", "parents": [ "b0355130e38034db6b904783a00f74a3524e1881" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 19 08:59:37 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 19 09:32:17 2017 +0000" }, "message": "Revert \"Revert \"Load the array class in the compiler for allocations.\"\"\n\nThis reverts commit fee255039e30c1c3dfc70c426c3d176221c3cdf9.\n\nChange-Id: I02b45f9a659d872feeb35df40b42c1be9878413a\n" }, { "commit": "fee255039e30c1c3dfc70c426c3d176221c3cdf9", "tree": "8207b72cc76513fed9f7b3c01aaa32cd54a87f1c", "parents": [ "cc99df230feb46ba717252f002d0cc2da6828421" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 19 02:11:15 2017 +0000" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 19 02:11:15 2017 +0000" }, "message": "Revert \"Load the array class in the compiler for allocations.\"\n\nlibcore test fails.\n\nThis reverts commit cc99df230feb46ba717252f002d0cc2da6828421.\n\nChange-Id: I5bac595acd2b240886062e8c1f11f9095ff6a9ed\n" }, { "commit": "cc99df230feb46ba717252f002d0cc2da6828421", "tree": "73ac045673e150fa367a8da4d46874f28e928491", "parents": [ "4507fdcb70bd570d5f3968061bf991f0a1233a93" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 17 23:00:24 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 18 15:16:32 2017 +0000" }, "message": "Load the array class in the compiler for allocations.\n\nRemoving one other dependency for needing to pass\nthe current method, and having dex_cache_resolved_types_\nin ArtMethod.\n\noat file increase:\n- x64: 0.25%\n- arm32: 0.30%\n- x86: 0.28%\n\ntest: test-art-host, test-art-target\nChange-Id: Ibca4fa00d3e31954db2ccb1f65a584b8c67cb230\n" }, { "commit": "5247c08fb186a5a2ac02226827cf6b994f41a681", "tree": "8b1305f9fb918024302382b8e8aa43962098e9fa", "parents": [ "0d478f289f0e33f19693d135f1d562b57427ed32" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 13 14:17:29 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 16 23:42:09 2017 +0000" }, "message": "Put the resolved class in HLoadClass.\n\nTo avoid repeated lookups in sharpening/rtp/inlining.\n\nTest: test-art-host test-art-target\nChange-Id: I08d0da36a4bb061cdaa490ea2af3a3217a875bbe\n" }, { "commit": "1998cd02603197f2acdc0734397a6d48b2f59b80", "tree": "aa639c7ec96f71d7aaf5d0c865a8a133dbc457c3", "parents": [ "6bec91c7d4670905cd67440991ec76fd54d0f000" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 13 13:02:58 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 13:39:24 2017 +0000" }, "message": "Implement HLoadClass/kBssEntry for boot image.\n\nTest: m test-art-host\nTest: m test-art-host with CC\nTest: m test-art-target on Nexus 9\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng\nBug: 30627598\nChange-Id: I168f24dedd5fb54a1e4215ecafb947ffb0dc3280\n" }, { "commit": "6bec91c7d4670905cd67440991ec76fd54d0f000", "tree": "05f4ba288e629270773c65b34b71be7bae5e92ff", "parents": [ "4155998a2f5c7a252a6611e3926943e931ea280a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 09 15:03:12 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Store resolved types for AOT code in .bss.\n\nTest: m test-art-host\nTest: m test-art-target on Nexus 9.\nTest: Nexus 9 boots.\nTest: Build aosp_mips64-eng.\nBug: 30627598\nBug: 34193123\nChange-Id: I8ec60a98eb488cb46ae3ea56341f5709dad4f623\n" }, { "commit": "4155998a2f5c7a252a6611e3926943e931ea280a", "tree": "3495370417d54a9bf7d0acedeefe89bd511062e0", "parents": [ "48886c2ee655a16224870fee52dc8721a52babcf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 06 14:04:23 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Make runtime call on main for HLoadClass/kDexCacheViaMethod.\n\nRemove dependency of the compiled code on types dex cache\narray in preparation for changing to a hash-based array.\n\nTest: m test-art-host\nTest: m test-art-target on Nexus 9\nBug: 30627598\nChange-Id: I3c426ed762c12eb9eb4bb61ea9a23a0659abf0a2\n" }, { "commit": "48886c2ee655a16224870fee52dc8721a52babcf", "tree": "debc8b7d9c99a83e2c056c47a8e0718be00c12c3", "parents": [ "58207cfd229d9f0b39fc634cff489dac83e1c010" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 06 11:45:47 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 16 12:09:53 2017 +0000" }, "message": "Remove HLoadClass::LoadKind::kDexCachePcRelative.\n\nTest: m test-art-host\nTest: m test-art-target-run-test-552-checker-sharpening\nBug: 30627598\nChange-Id: Ic809b0f3a8ed0bd4dc7ab67aa64866f9cdff9bdb\n" }, { "commit": "ac141397dc29189ad2b2df41f8d4312246beec60", "tree": "a2f481463a14695bf9327fd2f549878ecf30c77b", "parents": [ "5c9f90c5ecf2ff6f93ada0f7b18b46d866c59ea1" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri Jan 13 11:53:47 2017 +0000" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Sun Jan 15 15:18:07 2017 +0000" }, "message": "Revert \"Revert \"ART: Compiler support for invoke-polymorphic.\"\"\n\nThis reverts commit 0fb5af1c8287b1ec85c55c306a1c43820c38a337.\n\nThis takes us back to the original change and attempts to fix the\nissues encountered:\n\n- Adds transition record push/pop around artInvokePolymorphic.\n- Changes X86/X64 relocations for MacSDK.\n- Implements MIPS entrypoint for art_quick_invoke_polymorphic.\n- Corrects size of returned reference in art_quick_invoke_polymorphic\n on ARM.\n\nBug: 30550796,33191393\nTest: art/test/run-test 953\nTest: m test-art-run-test\n\nChange-Id: Ib6b93e00b37b9d4ab743a3470ab3d77fe857cda8\n" }, { "commit": "0d3998b5ff619364acf47bec0b541e7a49bd6fe7", "tree": "a4763c0660372f6311b612c09267cbbc2fe71e89", "parents": [ "aa89a4c6fca095904521842c018399f1e3501a45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 12 15:35:12 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 12 16:51:12 2017 +0000" }, "message": "Revert \"Revert \"Make object allocation entrypoints only take a class.\"\"\n\nThis reverts commit f7aaacd97881c6924b8212c7f8fe4a4c8721ef53.\n\nChange-Id: I6756cd1e6110bb45231f62f5e388f16c044cb145\n" }, { "commit": "c8144cdad955b77988a48777cfbdc6fd2e8c1916", "tree": "354e00610ec25279a8c4b77e8b685e380815813f", "parents": [ "d1a277954284c4dd4b5b14fd4e58f1854daed848", "f7aaacd97881c6924b8212c7f8fe4a4c8721ef53" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jan 12 06:19:22 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 12 06:19:23 2017 +0000" }, "message": "Merge \"Revert \"Make object allocation entrypoints only take a class.\"\"" }, { "commit": "f7aaacd97881c6924b8212c7f8fe4a4c8721ef53", "tree": "780209ac8e992fa63307062977f672aa5bb55d9e", "parents": [ "2b615ba29c4dfcf54aaf44955f2eac60f5080b2e" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 12 02:58:38 2017 +0000" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 12 02:58:38 2017 +0000" }, "message": "Revert \"Make object allocation entrypoints only take a class.\"\n\n960-default-smali64 is failing.\n\nThis reverts commit 2b615ba29c4dfcf54aaf44955f2eac60f5080b2e.\n\nChange-Id: Iebb8ee5a917fa84c5f01660ce432798524d078ef\n" }, { "commit": "dcf52765ab5886abdd85a4436fa0358b2a31341d", "tree": "b68ee975792a5bf488ed93cfbe09a37f80008288", "parents": [ "a28ddf5140cd1f4a2ae93dbf8be2f200b1552003", "0fb5af1c8287b1ec85c55c306a1c43820c38a337" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Wed Jan 11 19:18:51 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 11 19:18:51 2017 +0000" }, "message": "Merge \"Revert \"ART: Compiler support for invoke-polymorphic.\"\"" }, { "commit": "0fb5af1c8287b1ec85c55c306a1c43820c38a337", "tree": "66239e7f745fae54e1630e91fb44a859bff615d6", "parents": [ "02e3092f8d98f339588e48691db77f227b48ac1e" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Wed Jan 11 18:58:15 2017 +0000" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Wed Jan 11 19:17:33 2017 +0000" }, "message": "Revert \"ART: Compiler support for invoke-polymorphic.\"\n\nThis reverts commit 02e3092f8d98f339588e48691db77f227b48ac1e.\n\nReasons for revert:\n\n- Breaks MIPS/MIPS64 build.\n- Fails under GCStress test on x64.\n- Different x64 build configuration doesn\u0027t like relocation.\n\nChange-Id: I512555b38165d05f8a07e8aed528f00302061001\n" }, { "commit": "79f9928fc9e0a88430f3329069bfb2f9a0d37f0c", "tree": "e3142e4829c808c3df1059f3b05c0b3a37193ce9", "parents": [ "716eb25353390f699778a79d69006a5b8d8289c2", "02e3092f8d98f339588e48691db77f227b48ac1e" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Jan 11 18:08:03 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 11 18:08:04 2017 +0000" }, "message": "Merge \"ART: Compiler support for invoke-polymorphic.\"" }, { "commit": "02e3092f8d98f339588e48691db77f227b48ac1e", "tree": "127dd23346206b0547b7c6453a776253252b3c6e", "parents": [ "bc7d0deda4549f314e68ee3e0e6afd68c4a8fd06" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu Dec 01 10:33:51 2016 +0000" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Wed Jan 11 16:26:43 2017 +0000" }, "message": "ART: Compiler support for invoke-polymorphic.\n\nAdds basic support to invoke method handles in compiled code.\n\nEnables method verification for methods containing invoke-polymorphic.\n\nAdds k45cc/k45rc output to Instruction::DumpString() which\nwas found to be missing when enabling verification.\n\nInclude stack traces in test 957-methodhandle-transforms for\nfailures so they can be easily identified.\n\nBug: 30550796,33191393\nTest: art/test/run-test 953\nTest: m test-art-run-test\nChange-Id: Ic9a96ea24906087597d96ad8159a5bc349d06950\n" }, { "commit": "db47a144d816e0976c5b4c00461b80b07ce97c60", "tree": "628ffda55e75f18889161b684ac2b4e578d562b7", "parents": [ "f62455a422baf040d901db964bdd3c6e18185c13", "f0acfe7a812a332122011832074142718c278dae" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 11 14:05:08 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 11 14:05:09 2017 +0000" }, "message": "Merge \"Keep resolved String in HLoadString.\"" }, { "commit": "2b615ba29c4dfcf54aaf44955f2eac60f5080b2e", "tree": "0a2fe5f9243645a054d4aa094bff5a69cc1abb88", "parents": [ "c9a060f2688599d4a402ee6234db46c2e9b7463f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 06 14:40:07 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 11 10:34:10 2017 +0000" }, "message": "Make object allocation entrypoints only take a class.\n\nChange motivated by:\n- Dex cache compression: having the allocation fast path do a\n dex cache lookup will be too expensive. So instead, rely on the\n compiler having direct access to the class (either through BSS for\n AOT, or JIT tables for JIT).\n- Inlining: the entrypoints relied on the caller of the allocation to\n have the same dex cache as the outer method (stored at the bottom of\n the stack). This meant we could not inline methods from a different\n dex file that do allocations. By avoiding the dex cache lookup in\n the entrypoint, we can now remove this restriction.\n\nCode expansion on average for Docs/Gms/FB/Framework (go/lem numbers):\n- Around 0.8% on arm64\n- Around 1% for x64, arm\n- Around 1.5% on x86\n\nTest: test-art-host, test-art-target, ART_USE_READ_BARRIER\u003dtrue/false\nTest: test-art-host, test-art-target, ART_DEFAULT_GC_TYPE\u003dSS ART_USE_TLAB\u003dtrue\n\nChange-Id: I41f3748bb4d251996aaf6a90fae4c50176f9295f\n" }, { "commit": "f0acfe7a812a332122011832074142718c278dae", "tree": "49c4fc481cebd03323aaf0109066859165508303", "parents": [ "91db41f315f6c2366b7098c531224bee01170364" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 09 20:54:52 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 10 21:26:23 2017 +0000" }, "message": "Keep resolved String in HLoadString.\n\nFor the following reasons:\n- Avoids needing to do a lookup again in CodeGenerator::EmitJitRoots.\n- Fixes races where we the string was GC\u0027ed before CodeGenerator::EmitJitRoots.\n- Makes it possible to do GVN on the same string but defined in different\n dex files.\n\nTest: test-art-host, test-art-target\nChange-Id: If2b5d3079f7555427b1b96ab04546b3373fcf921\n" }, { "commit": "e114da261e49083beaddb8b13328b2a16a0e537e", "tree": "26e65dba14b521ed417cf0a693d00078267e2a76", "parents": [ "6a14c622700e088173ba909799c1e1785aeb4b34" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Dec 26 14:21:43 2016 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Dec 26 14:23:53 2016 +0100" }, "message": "MIPS32: Don\u0027t always do a null test in MarkGCCard\n\nTest: mma test-art-target-run-test on CI20\n\nChange-Id: I38fac492bb76b06b9cffc9be16944fb22ed2db70\n" }, { "commit": "c1a42cf3873be202c8c0ca3c4e67500b470ab075", "tree": "f2bffbd14e1f9d5429dd8514d19be4fa6dfa392f", "parents": [ "06ce6d4359ed897f1d1b39be4e748f0c4f3ca2ff" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Dec 18 15:52:36 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 20 13:29:45 2016 +0000" }, "message": "Remove soon to be obsolete call kinds for direct calls.\n\nAnd remove CompilerDriver::GetCodeAndMethodForDirectCall in\npreparation of removing non-PIC prebuild and non-PIC on-device\nboot image compilation.\n\nTest: test-art-host test-art-target\nbug:33192586\nChange-Id: Ic48e3e8b9d7605dd0e66f31d458a182198ba9578\n" }, { "commit": "f63f569eeefe3907c48a175494a2a0ba351b641a", "tree": "c2ba1621cbcd77571378b8261ec6d47c754953aa", "parents": [ "2c43590dc2bb7fb4a3a015b1b65543bb8705ffe8" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 13 17:43:11 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Dec 19 14:47:16 2016 -0800" }, "message": "MIPS64: Improve string and class loads.\n\nThis adds most kinds of string/class loads.\nJIT string/class loads are TBD separately.\n\nThis also fixes Mips64Assembler::LoadLabelAddress()\n(adding a constant to a 64-bit address must be done\nusing daddiu, not addiu).\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test64\"\n\nChange-Id: I1f94ece4cd202382c11167e1ed958e9d08d92822\n" }, { "commit": "c641842008b449890d2a63ed34a240ed7c7aa75d", "tree": "66c0e16eead7ea0c64029c205aea56c724bb5dc1", "parents": [ "a248587487ad23eaccd6a5877d97c7735120118e" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Dec 05 16:31:55 2016 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Dec 14 10:22:48 2016 +0100" }, "message": "Implement VisitShouldDeoptimizeFlag for MIPS/MIPS64\n\nThis is follow-up change for I18bf716a601b6413b46312e925a6ad9e4008efa4.\n\nTest: mma ART_TEST_JIT\u003dtrue test-art-target-run-test-jit on CI20 and QEMU\n\nChange-Id: I750814ae740a4549f1a2af11be7ae4318ae26a2f\n" }, { "commit": "22384aeab988df7fa5ccdc48a668589c5f602c39", "tree": "daca06adfc92c93017618c3729af54ed40214ba4", "parents": [ "0ee6447c63e354131dec78743ccabcbc964129e3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 22:33:36 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 23:06:38 2016 +0000" }, "message": "Revert \"Revert \"Add kJitTableAddress for HLoadClass.\"\"\n\nThis reverts commit d2d5262c8370309e1f2a009f00aafc24f1cf00a0.\n\nChange-Id: I6149d5c7d5df0b0fc5cb646a802a2eea8d01ac08\n" }, { "commit": "4dd3f7d2e9319bc622e89cbe110620d85d14ffca", "tree": "eb5203121c5b8d1d6b33f39e1c8b2ff45ad26ca8", "parents": [ "7d81bf2c9de138a65ea7189df18bc88f2c4fe6c5", "d2d5262c8370309e1f2a009f00aafc24f1cf00a0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 16:29:18 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Dec 12 16:29:18 2016 +0000" }, "message": "Merge \"Revert \"Add kJitTableAddress for HLoadClass.\"\"" }, { "commit": "d2d5262c8370309e1f2a009f00aafc24f1cf00a0", "tree": "15b542ac079f30043cd3654cf5d3c40ae3ea34d0", "parents": [ "5b12f7973636bfea29da3956a9baa7a6bbe2b666" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 16:28:54 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 16:28:54 2016 +0000" }, "message": "Revert \"Add kJitTableAddress for HLoadClass.\"\n\nOne test failure after merge.\n\nThis reverts commit 5b12f7973636bfea29da3956a9baa7a6bbe2b666.\n\nChange-Id: I120c49e53274471fc1c82a10d52e99c83f5f85cc\n" }, { "commit": "7d81bf2c9de138a65ea7189df18bc88f2c4fe6c5", "tree": "4fd804520510a1701a5bf8aaa74171a583152f27", "parents": [ "c836b5a8a5ea00b0cd332d5e60c9ec10ae1e74fb", "5b12f7973636bfea29da3956a9baa7a6bbe2b666" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 15:26:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Dec 12 15:26:11 2016 +0000" }, "message": "Merge \"Add kJitTableAddress for HLoadClass.\"" }, { "commit": "5b12f7973636bfea29da3956a9baa7a6bbe2b666", "tree": "a2cd41c1d3c09abc594a76af11b7bebc302a2870", "parents": [ "0dd27eb2b51d030866c25dbf8e7bb737eb35a888" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 09 11:26:35 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 12 11:50:24 2016 +0000" }, "message": "Add kJitTableAddress for HLoadClass.\n\nThis new kind loads classes from the root table associated with\nJIT compiled code.\n\nAlso remove kDexCacheAddress, which is replaced by kJitTableAddress.\n\ntest: ART_TEST_JIT\u003dtrue test-art-host-jit test-art-target-jit\nChange-Id: Ia23029688d1a60c178bf2ffa7463927c5d5de4d0\n" }, { "commit": "b08265b2d61cd3923dd6fc01d6c82f73d5230e82", "tree": "cebb0dd2570ed90265dc376d89c17768700fd90d", "parents": [ "b4ee681c21564ee9afe0202e1006cfa21019e88b", "1b8464d17c2266763714ae18be7c4dc26e28bf61" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 07 17:15:08 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Dec 07 17:15:08 2016 +0000" }, "message": "Merge \"MIPS32: Pass more arguments in registers.\"" }, { "commit": "1b8464d17c2266763714ae18be7c4dc26e28bf61", "tree": "19ab81b439fc216e289cb14be8a7618dbafb4f50", "parents": [ "d7a7c7f3e93de9fa915e66d54dfc799efcc12ffb" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Nov 12 17:22:05 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 06 13:57:04 2016 -0800" }, "message": "MIPS32: Pass more arguments in registers.\n\nSpecifically, use A0-A3,T0-T1 for non-floats and F8-F19 for floats.\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R2) on CI20\nTest: test-art-target-gtest (MIPS32R2) on CI20\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R6) in QEMU\nTest: test-art-target-gtest (MIPS32R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: Ib8b0310a109d9f3d70119c1e605e54b013e60728\n" } ], "next": "063fc772b5b8aed7d769cd7cccb6ddc7619326ee" }